1 /*- 2 * Copyright (c) 1990 The Regents of the University of California. 3 * Copyright (c) 2014-2016 The FreeBSD Foundation 4 * All rights reserved. 5 * 6 * This code is derived from software contributed to Berkeley by 7 * William Jolitz. 8 * 9 * Portions of this software were developed by Andrew Turner 10 * under sponsorship from the FreeBSD Foundation 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. Neither the name of the University nor the names of its contributors 21 * may be used to endorse or promote products derived from this software 22 * without specific prior written permission. 23 * 24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * from: @(#)cpu.h 5.4 (Berkeley) 5/9/91 37 * from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29 38 * $FreeBSD$ 39 */ 40 41 #ifndef _MACHINE_CPU_H_ 42 #define _MACHINE_CPU_H_ 43 44 #include <machine/atomic.h> 45 #include <machine/frame.h> 46 #include <machine/armreg.h> 47 48 #define TRAPF_PC(tfp) ((tfp)->tf_lr) 49 #define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t) 50 51 #define cpu_getstack(td) ((td)->td_frame->tf_sp) 52 #define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp)) 53 #define cpu_spinwait() __asm __volatile("yield" ::: "memory") 54 55 /* Extract CPU affinity levels 0-3 */ 56 #define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff) 57 #define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff) 58 #define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff) 59 #define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff) 60 #define CPU_AFF0_MASK 0xffUL 61 #define CPU_AFF1_MASK 0xff00UL 62 #define CPU_AFF2_MASK 0xff0000UL 63 #define CPU_AFF3_MASK 0xff00000000UL 64 #define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \ 65 CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */ 66 67 #ifdef _KERNEL 68 69 #define CPU_IMPL_ARM 0x41 70 #define CPU_IMPL_BROADCOM 0x42 71 #define CPU_IMPL_CAVIUM 0x43 72 #define CPU_IMPL_DEC 0x44 73 #define CPU_IMPL_INFINEON 0x49 74 #define CPU_IMPL_FREESCALE 0x4D 75 #define CPU_IMPL_NVIDIA 0x4E 76 #define CPU_IMPL_APM 0x50 77 #define CPU_IMPL_QUALCOMM 0x51 78 #define CPU_IMPL_MARVELL 0x56 79 #define CPU_IMPL_INTEL 0x69 80 81 /* ARM Part numbers */ 82 #define CPU_PART_FOUNDATION 0xD00 83 #define CPU_PART_CORTEX_A35 0xD04 84 #define CPU_PART_CORTEX_A53 0xD03 85 #define CPU_PART_CORTEX_A55 0xD05 86 #define CPU_PART_CORTEX_A57 0xD07 87 #define CPU_PART_CORTEX_A72 0xD08 88 #define CPU_PART_CORTEX_A73 0xD09 89 #define CPU_PART_CORTEX_A75 0xD0A 90 91 /* Cavium Part numbers */ 92 #define CPU_PART_THUNDERX 0x0A1 93 #define CPU_PART_THUNDERX_81XX 0x0A2 94 #define CPU_PART_THUNDERX_83XX 0x0A3 95 #define CPU_PART_THUNDERX2 0x0AF 96 97 #define CPU_REV_THUNDERX_1_0 0x00 98 #define CPU_REV_THUNDERX_1_1 0x01 99 100 #define CPU_REV_THUNDERX2_0 0x00 101 102 #define CPU_IMPL(midr) (((midr) >> 24) & 0xff) 103 #define CPU_PART(midr) (((midr) >> 4) & 0xfff) 104 #define CPU_VAR(midr) (((midr) >> 20) & 0xf) 105 #define CPU_REV(midr) (((midr) >> 0) & 0xf) 106 107 #define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24) 108 #define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4) 109 #define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20) 110 #define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0) 111 112 #define CPU_IMPL_MASK (0xff << 24) 113 #define CPU_PART_MASK (0xfff << 4) 114 #define CPU_VAR_MASK (0xf << 20) 115 #define CPU_REV_MASK (0xf << 0) 116 117 #define CPU_ID_RAW(impl, part, var, rev) \ 118 (CPU_IMPL_TO_MIDR((impl)) | \ 119 CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \ 120 CPU_REV_TO_MIDR((rev))) 121 122 #define CPU_MATCH(mask, impl, part, var, rev) \ 123 (((mask) & PCPU_GET(midr)) == \ 124 ((mask) & CPU_ID_RAW((impl), (part), (var), (rev)))) 125 126 #define CPU_MATCH_RAW(mask, devid) \ 127 (((mask) & PCPU_GET(midr)) == ((mask) & (devid))) 128 129 /* 130 * Chip-specific errata. This defines are intended to be 131 * booleans used within if statements. When an appropriate 132 * kernel option is disabled, these defines must be defined 133 * as 0 to allow the compiler to remove a dead code thus 134 * produce better optimized kernel image. 135 */ 136 /* 137 * Vendor: Cavium 138 * Chip: ThunderX 139 * Revision(s): Pass 1.0, Pass 1.1 140 */ 141 #ifdef THUNDERX_PASS_1_1_ERRATA 142 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \ 143 (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 144 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \ 145 CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \ 146 CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1)) 147 #else 148 #define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0 149 #endif 150 151 152 extern char btext[]; 153 extern char etext[]; 154 155 extern uint64_t __cpu_affinity[]; 156 157 void cpu_halt(void) __dead2; 158 void cpu_reset(void) __dead2; 159 void fork_trampoline(void); 160 void identify_cpu(void); 161 void install_cpu_errata(void); 162 void print_cpu_features(u_int); 163 void swi_vm(void *v); 164 165 #define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)] 166 #define CPU_CURRENT_SOCKET \ 167 (CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid)))) 168 169 static __inline uint64_t 170 get_cyclecount(void) 171 { 172 uint64_t ret; 173 174 ret = READ_SPECIALREG(cntvct_el0); 175 176 return (ret); 177 } 178 179 #define ADDRESS_TRANSLATE_FUNC(stage) \ 180 static inline uint64_t \ 181 arm64_address_translate_ ##stage (uint64_t addr) \ 182 { \ 183 uint64_t ret; \ 184 \ 185 __asm __volatile( \ 186 "at " __STRING(stage) ", %1 \n" \ 187 "mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \ 188 \ 189 return (ret); \ 190 } 191 192 ADDRESS_TRANSLATE_FUNC(s1e0r) 193 ADDRESS_TRANSLATE_FUNC(s1e0w) 194 ADDRESS_TRANSLATE_FUNC(s1e1r) 195 ADDRESS_TRANSLATE_FUNC(s1e1w) 196 197 #endif 198 199 #endif /* !_MACHINE_CPU_H_ */ 200