1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2021, 2022 Soren Schmidt <sos@deepcore.dk> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 */ 28 29 #include <sys/cdefs.h> 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <sys/mutex.h> 35 #include <sys/rman.h> 36 #include <machine/bus.h> 37 38 #include <dev/ofw/openfirm.h> 39 #include <dev/ofw/ofw_bus.h> 40 #include <dev/ofw/ofw_bus_subr.h> 41 42 #include <dev/fdt/simple_mfd.h> 43 44 #include <dev/extres/clk/clk.h> 45 #include <dev/extres/hwreset/hwreset.h> 46 #include <dev/extres/regulator/regulator.h> 47 #include <dev/extres/syscon/syscon.h> 48 #include <dev/extres/phy/phy.h> 49 50 #include <contrib/device-tree/include/dt-bindings/phy/phy.h> 51 52 #include "syscon_if.h" 53 #include "phydev_if.h" 54 #include "phynode_if.h" 55 56 #define GRF_PCIE30PHY_CON1 0x04 57 #define GRF_PCIE30PHY_CON4 0x10 58 #define GRF_PCIE30PHY_CON6 0x18 59 #define GRF_BIFURCATION_LANE_0_1 (1 << 0) 60 #define GRF_BIFURCATION_LANE_2_3 (1 << 1) 61 #define GRF_PCIE30PHY_WR_EN (0xf << 16) 62 #define GRF_PCIE30PHY_CON9 0x24 63 #define GRF_PCIE30PHY_DA_OCM ((1 << 15) | (1 << (15 + 16))) 64 #define GRF_PCIE30PHY_STATUS0 0x80 65 #define SRAM_INIT_DONE (1 << 14) 66 67 static struct ofw_compat_data compat_data[] = { 68 {"rockchip,rk3568-pcie3-phy", 1}, 69 {NULL, 0} 70 }; 71 72 struct rk3568_pciephy_softc { 73 device_t dev; 74 phandle_t node; 75 struct resource *mem; 76 struct phynode *phynode; 77 struct syscon *phy_grf; 78 clk_t refclk_m; 79 clk_t refclk_n; 80 clk_t pclk; 81 hwreset_t phy_reset; 82 }; 83 84 85 /* PHY class and methods */ 86 static int 87 rk3568_pciephy_enable(struct phynode *phynode, bool enable) 88 { 89 device_t dev = phynode_get_device(phynode); 90 struct rk3568_pciephy_softc *sc = device_get_softc(dev); 91 int count; 92 93 if (enable) { 94 /* Deassert PCIe PMA output clamp mode */ 95 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON9, 96 GRF_PCIE30PHY_DA_OCM); 97 98 /* Set bifurcation according to DT entry */ 99 if (OF_hasprop(sc->node, "rockchip,bifurcation")) { 100 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON6, 101 GRF_PCIE30PHY_WR_EN | GRF_BIFURCATION_LANE_0_1); 102 SYSCON_WRITE_4(sc->phy_grf, GRF_PCIE30PHY_CON1, 103 GRF_PCIE30PHY_DA_OCM); 104 device_printf(dev, "setup 2 x PCIeX1\n"); 105 } 106 else 107 device_printf(dev, "setup 1 x PCIeX2\n"); 108 109 hwreset_deassert(sc->phy_reset); 110 111 /* Poll for SRAM loaded and ready */ 112 for (count = 100; count; count--) { 113 if (SYSCON_READ_4(sc->phy_grf, GRF_PCIE30PHY_STATUS0) & 114 SRAM_INIT_DONE) 115 break; 116 DELAY(10000); 117 if (count == 0) { 118 device_printf(dev, "SRAM init timeout!\n"); 119 return (ENXIO); 120 } 121 } 122 } 123 return (0); 124 } 125 126 static phynode_method_t rk3568_pciephy_phynode_methods[] = { 127 PHYNODEMETHOD(phynode_enable, rk3568_pciephy_enable), 128 129 PHYNODEMETHOD_END 130 }; 131 DEFINE_CLASS_1(rk3568_pciephy_phynode, rk3568_pciephy_phynode_class, 132 rk3568_pciephy_phynode_methods, 0, phynode_class); 133 134 135 /* Device class and methods */ 136 static int 137 rk3568_pciephy_probe(device_t dev) 138 { 139 140 if (!ofw_bus_status_okay(dev)) 141 return (ENXIO); 142 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 143 return (ENXIO); 144 device_set_desc(dev, "RockChip PCIe PHY"); 145 return (BUS_PROBE_DEFAULT); 146 } 147 148 static int 149 rk3568_pciephy_attach(device_t dev) 150 { 151 struct rk3568_pciephy_softc *sc = device_get_softc(dev); 152 struct phynode_init_def phy_init; 153 struct phynode *phynode; 154 int rid = 0; 155 156 sc->dev = dev; 157 sc->node = ofw_bus_get_node(dev); 158 159 /* Get memory resource */ 160 if (!(sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 161 RF_ACTIVE))) { 162 device_printf(dev, "Cannot allocate memory resources\n"); 163 return (ENXIO); 164 } 165 166 /* Get syncons handle */ 167 if (OF_hasprop(sc->node, "rockchip,phy-grf") && 168 syscon_get_by_ofw_property(dev, sc->node, "rockchip,phy-grf", 169 &sc->phy_grf)) 170 return (ENXIO); 171 172 /* Get & enable clocks */ 173 if (clk_get_by_ofw_name(dev, 0, "refclk_m", &sc->refclk_m)) { 174 device_printf(dev, "getting refclk_m failed\n"); 175 return (ENXIO); 176 } 177 if (clk_enable(sc->refclk_m)) 178 device_printf(dev, "enable refclk_m failed\n"); 179 if (clk_get_by_ofw_name(dev, 0, "refclk_n", &sc->refclk_n)) { 180 device_printf(dev, "getting refclk_n failed\n"); 181 return (ENXIO); 182 } 183 if (clk_enable(sc->refclk_n)) 184 device_printf(dev, "enable refclk_n failed\n"); 185 if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->pclk)) { 186 device_printf(dev, "getting pclk failed\n"); 187 return (ENXIO); 188 } 189 if (clk_enable(sc->pclk)) 190 device_printf(dev, "enable pclk failed\n"); 191 192 /* Get & assert reset */ 193 if (hwreset_get_by_ofw_idx(dev, sc->node, 0, &sc->phy_reset)) { 194 device_printf(dev, "Cannot get reset\n"); 195 } 196 else 197 hwreset_assert(sc->phy_reset); 198 199 /* Set RC/EP mode not implemented yet (RC mode only) */ 200 201 bzero(&phy_init, sizeof(phy_init)); 202 phy_init.id = PHY_NONE; 203 phy_init.ofw_node = sc->node; 204 if (!(phynode = phynode_create(dev, &rk3568_pciephy_phynode_class, 205 &phy_init))) { 206 device_printf(dev, "failed to create pciephy PHY\n"); 207 return (ENXIO); 208 } 209 if (!phynode_register(phynode)) { 210 device_printf(dev, "failed to register pciephy PHY\n"); 211 return (ENXIO); 212 } 213 sc->phynode = phynode; 214 215 return (0); 216 } 217 218 static device_method_t rk3568_pciephy_methods[] = { 219 DEVMETHOD(device_probe, rk3568_pciephy_probe), 220 DEVMETHOD(device_attach, rk3568_pciephy_attach), 221 222 DEVMETHOD_END 223 }; 224 225 DEFINE_CLASS_1(rk3568_pciephy, rk3568_pciephy_driver, rk3568_pciephy_methods, 226 sizeof(struct simple_mfd_softc), simple_mfd_driver); 227 EARLY_DRIVER_MODULE(rk3568_pciephy, simplebus, rk3568_pciephy_driver, 228 0, 0, BUS_PASS_RESOURCE + BUS_PASS_ORDER_LATE); 229