1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 37 #include <sys/kernel.h> 38 #include <sys/module.h> 39 #include <sys/rman.h> 40 #include <sys/lock.h> 41 #include <sys/mutex.h> 42 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <machine/intr.h> 46 47 #include <dev/fdt/simplebus.h> 48 49 #include <dev/ofw/ofw_bus.h> 50 #include <dev/ofw/ofw_bus_subr.h> 51 52 #include <dev/fdt/fdt_pinctrl.h> 53 54 #include <dev/extres/syscon/syscon.h> 55 56 #include "syscon_if.h" 57 58 #include "opt_soc.h" 59 60 struct rk_pinctrl_pin_drive { 61 uint32_t value; 62 uint32_t ma; 63 }; 64 65 struct rk_pinctrl_bank { 66 uint32_t bank_num; 67 uint32_t subbank_num; 68 uint32_t offset; 69 uint32_t nbits; 70 }; 71 72 struct rk_pinctrl_pin_fixup { 73 uint32_t bank; 74 uint32_t subbank; 75 uint32_t pin; 76 uint32_t reg; 77 uint32_t bit; 78 uint32_t mask; 79 }; 80 81 struct rk_pinctrl_conf { 82 struct rk_pinctrl_bank *iomux_conf; 83 uint32_t iomux_nbanks; 84 struct rk_pinctrl_pin_fixup *pin_fixup; 85 uint32_t npin_fixup; 86 struct rk_pinctrl_pin_drive *pin_drive; 87 uint32_t npin_drive; 88 uint32_t pd_offset; 89 uint32_t drive_offset; 90 }; 91 92 struct rk_pinctrl_softc { 93 struct simplebus_softc simplebus_sc; 94 device_t dev; 95 struct syscon *grf; 96 struct rk_pinctrl_conf *conf; 97 }; 98 99 static struct rk_pinctrl_bank rk3328_iomux_bank[] = { 100 { 101 .bank_num = 0, 102 .subbank_num = 0, 103 .offset = 0x00, 104 .nbits = 2, 105 }, 106 { 107 .bank_num = 0, 108 .subbank_num = 1, 109 .offset = 0x04, 110 .nbits = 2, 111 }, 112 { 113 .bank_num = 0, 114 .subbank_num = 2, 115 .offset = 0x08, 116 .nbits = 2, 117 }, 118 { 119 .bank_num = 0, 120 .subbank_num = 3, 121 .offset = 0xc, 122 .nbits = 2, 123 }, 124 { 125 .bank_num = 1, 126 .subbank_num = 0, 127 .offset = 0x10, 128 .nbits = 2, 129 }, 130 { 131 .bank_num = 1, 132 .subbank_num = 1, 133 .offset = 0x14, 134 .nbits = 2, 135 }, 136 { 137 .bank_num = 1, 138 .subbank_num = 2, 139 .offset = 0x18, 140 .nbits = 2, 141 }, 142 { 143 .bank_num = 1, 144 .subbank_num = 3, 145 .offset = 0x1C, 146 .nbits = 2, 147 }, 148 { 149 .bank_num = 2, 150 .subbank_num = 0, 151 .offset = 0x20, 152 .nbits = 2, 153 }, 154 { 155 .bank_num = 2, 156 .subbank_num = 1, 157 .offset = 0x24, 158 .nbits = 3, 159 }, 160 { 161 .bank_num = 2, 162 .subbank_num = 2, 163 .offset = 0x2c, 164 .nbits = 3, 165 }, 166 { 167 .bank_num = 2, 168 .subbank_num = 3, 169 .offset = 0x34, 170 .nbits = 2, 171 }, 172 { 173 .bank_num = 3, 174 .subbank_num = 0, 175 .offset = 0x38, 176 .nbits = 3, 177 }, 178 { 179 .bank_num = 3, 180 .subbank_num = 1, 181 .offset = 0x40, 182 .nbits = 3, 183 }, 184 { 185 .bank_num = 3, 186 .subbank_num = 2, 187 .offset = 0x48, 188 .nbits = 3, 189 }, 190 { 191 .bank_num = 3, 192 .subbank_num = 3, 193 .offset = 0x4c, 194 .nbits = 3, 195 }, 196 }; 197 198 static struct rk_pinctrl_pin_fixup rk3328_pin_fixup[] = { 199 { 200 .bank = 2, 201 .pin = 12, 202 .reg = 0x24, 203 .bit = 8, 204 .mask = 0x300, 205 }, 206 { 207 .bank = 2, 208 .pin = 15, 209 .reg = 0x28, 210 .bit = 0, 211 .mask = 0x7, 212 }, 213 { 214 .bank = 2, 215 .pin = 23, 216 .reg = 0x30, 217 .bit = 14, 218 .mask = 0x6000, 219 }, 220 }; 221 222 static struct rk_pinctrl_pin_drive rk3328_pin_drive[] = { 223 { 224 .value = 0, 225 .ma = 2, 226 }, 227 { 228 .value = 1, 229 .ma = 4, 230 }, 231 { 232 .value = 2, 233 .ma = 8, 234 }, 235 { 236 .value = 3, 237 .ma = 12, 238 }, 239 }; 240 241 struct rk_pinctrl_conf rk3328_conf = { 242 .iomux_conf = rk3328_iomux_bank, 243 .iomux_nbanks = nitems(rk3328_iomux_bank), 244 .pin_fixup = rk3328_pin_fixup, 245 .npin_fixup = nitems(rk3328_pin_fixup), 246 .pin_drive = rk3328_pin_drive, 247 .npin_drive = nitems(rk3328_pin_drive), 248 .pd_offset = 0x100, 249 .drive_offset = 0x200, 250 }; 251 252 static struct ofw_compat_data compat_data[] = { 253 #ifdef SOC_ROCKCHIP_RK3328 254 {"rockchip,rk3328-pinctrl", (uintptr_t)&rk3328_conf}, 255 #endif 256 {NULL, 0} 257 }; 258 259 static int 260 rk_pinctrl_parse_bias(phandle_t node) 261 { 262 if (OF_hasprop(node, "bias-disable")) 263 return (0); 264 if (OF_hasprop(node, "bias-pull-up")) 265 return (1); 266 if (OF_hasprop(node, "bias-pull-down")) 267 return (2); 268 269 return (-1); 270 } 271 272 static int rk_pinctrl_parse_drive(struct rk_pinctrl_softc *sc, phandle_t node, 273 uint32_t *drive) 274 { 275 uint32_t value; 276 int i; 277 278 if (OF_getencprop(node, "drive-strength", &value, 279 sizeof(value)) != 0) 280 return (-1); 281 282 /* Map to the correct drive value */ 283 for (i = 0; i < sc->conf->npin_drive; i++) 284 if (sc->conf->pin_drive[i].ma == value) { 285 *drive = sc->conf->pin_drive[i].value; 286 return (0); 287 } 288 289 return (-1); 290 } 291 292 static void 293 rk_pinctrl_get_fixup(struct rk_pinctrl_softc *sc, uint32_t bank, uint32_t pin, 294 uint32_t *reg, uint32_t *mask, uint32_t *bit) 295 { 296 int i; 297 298 for (i = 0; i < sc->conf->npin_fixup; i++) 299 if (sc->conf->pin_fixup[i].bank == bank && 300 sc->conf->pin_fixup[i].pin == pin) { 301 *reg = sc->conf->pin_fixup[i].reg; 302 *mask = sc->conf->pin_fixup[i].mask; 303 *bit = sc->conf->pin_fixup[i].bit; 304 305 return; 306 } 307 } 308 309 static void 310 rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, uint32_t *pindata) 311 { 312 phandle_t pin_conf; 313 uint32_t bank, subbank, pin, function, bias; 314 uint32_t bit, mask, reg, drive; 315 int i; 316 317 bank = pindata[0]; 318 pin = pindata[1]; 319 function = pindata[2]; 320 pin_conf = OF_node_from_xref(pindata[3]); 321 subbank = pin / 8; 322 323 for (i = 0; i < sc->conf->iomux_nbanks; i++) 324 if (sc->conf->iomux_conf[i].bank_num == bank && 325 sc->conf->iomux_conf[i].subbank_num == subbank) 326 break; 327 328 if (i == sc->conf->iomux_nbanks) { 329 device_printf(sc->dev, "Unknown pin %d in bank %d\n", pin, 330 bank); 331 return; 332 } 333 334 /* Parse pin function */ 335 reg = sc->conf->iomux_conf[i].offset; 336 switch (sc->conf->iomux_conf[i].nbits) { 337 case 3: 338 if ((pin % 8) >= 5) 339 reg += 4; 340 bit = (pin % 8 % 5) * 3; 341 mask = (0x7 << bit) << 16; 342 break; 343 case 2: 344 default: 345 bit = (pin % 8) * 2; 346 mask = (0x3 << bit) << 16; 347 break; 348 } 349 rk_pinctrl_get_fixup(sc, bank, pin, ®, &mask, &bit); 350 SYSCON_WRITE_4(sc->grf, reg, function << bit | mask); 351 352 /* Pull-Up/Down */ 353 bias = rk_pinctrl_parse_bias(pin_conf); 354 if (bias >= 0) { 355 reg = sc->conf->pd_offset; 356 357 reg += bank * 0x10 + ((pin / 8) * 0x4); 358 bit = (pin % 8) * 2; 359 mask = (0x3 << bit) << 16; 360 SYSCON_WRITE_4(sc->grf, reg, bias << bit | mask); 361 } 362 363 /* Drive Strength */ 364 if (rk_pinctrl_parse_drive(sc, pin_conf, &drive) == 0) { 365 reg = sc->conf->drive_offset; 366 367 reg += bank * 0x10 + ((pin / 8) * 0x4); 368 bit = (pin % 8) * 2; 369 mask = (0x3 << bit) << 16; 370 SYSCON_WRITE_4(sc->grf, reg, bias << bit | mask); 371 } 372 } 373 374 static int 375 rk_pinctrl_configure_pins(device_t dev, phandle_t cfgxref) 376 { 377 struct rk_pinctrl_softc *sc; 378 phandle_t node; 379 uint32_t *pins; 380 int i, npins; 381 382 sc = device_get_softc(dev); 383 node = OF_node_from_xref(cfgxref); 384 385 npins = OF_getencprop_alloc_multi(node, "rockchip,pins", sizeof(*pins), 386 (void **)&pins); 387 if (npins <= 0) 388 return (ENOENT); 389 390 for (i = 0; i != npins; i += 4) 391 rk_pinctrl_configure_pin(sc, pins + i); 392 393 return (0); 394 } 395 396 static int 397 rk_pinctrl_probe(device_t dev) 398 { 399 400 if (!ofw_bus_status_okay(dev)) 401 return (ENXIO); 402 403 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 404 return (ENXIO); 405 406 device_set_desc(dev, "RockChip Pinctrl controller"); 407 return (BUS_PROBE_DEFAULT); 408 } 409 410 static int 411 rk_pinctrl_attach(device_t dev) 412 { 413 struct rk_pinctrl_softc *sc; 414 phandle_t node; 415 device_t cdev; 416 417 sc = device_get_softc(dev); 418 sc->dev = dev; 419 420 node = ofw_bus_get_node(dev); 421 422 if (OF_hasprop(node, "rockchip,grf") && 423 syscon_get_by_ofw_property(dev, node, 424 "rockchip,grf", &sc->grf) != 0) { 425 device_printf(dev, "cannot get grf driver handle\n"); 426 return (ENXIO); 427 } 428 429 sc->conf = (struct rk_pinctrl_conf *)ofw_bus_search_compatible(dev, 430 compat_data)->ocd_data; 431 432 fdt_pinctrl_register(dev, "rockchip,pins"); 433 fdt_pinctrl_configure_tree(dev); 434 435 simplebus_init(dev, node); 436 437 bus_generic_probe(dev); 438 439 /* Attach child devices */ 440 for (node = OF_child(node); node > 0; node = OF_peer(node)) { 441 cdev = simplebus_add_device(dev, node, 0, NULL, -1, NULL); 442 if (cdev != NULL) 443 device_probe_and_attach(cdev); 444 } 445 446 return (bus_generic_attach(dev)); 447 } 448 449 static int 450 rk_pinctrl_detach(device_t dev) 451 { 452 453 return (EBUSY); 454 } 455 456 static device_method_t rk_pinctrl_methods[] = { 457 /* Device interface */ 458 DEVMETHOD(device_probe, rk_pinctrl_probe), 459 DEVMETHOD(device_attach, rk_pinctrl_attach), 460 DEVMETHOD(device_detach, rk_pinctrl_detach), 461 462 /* fdt_pinctrl interface */ 463 DEVMETHOD(fdt_pinctrl_configure,rk_pinctrl_configure_pins), 464 465 DEVMETHOD_END 466 }; 467 468 static devclass_t rk_pinctrl_devclass; 469 470 DEFINE_CLASS_1(rk_pinctrl, rk_pinctrl_driver, rk_pinctrl_methods, 471 sizeof(struct rk_pinctrl_softc), simplebus_driver); 472 473 EARLY_DRIVER_MODULE(rk_pinctrl, simplebus, rk_pinctrl_driver, 474 rk_pinctrl_devclass, 0, 0, BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 475 MODULE_VERSION(rk_pinctrl, 1); 476