176bd547bSAdrian Chadd /*
276bd547bSAdrian Chadd * Copyright (c) 2013 Qualcomm Atheros, Inc.
376bd547bSAdrian Chadd *
476bd547bSAdrian Chadd * Permission to use, copy, modify, and/or distribute this software for any
576bd547bSAdrian Chadd * purpose with or without fee is hereby granted, provided that the above
676bd547bSAdrian Chadd * copyright notice and this permission notice appear in all copies.
776bd547bSAdrian Chadd *
876bd547bSAdrian Chadd * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH
976bd547bSAdrian Chadd * REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY
1076bd547bSAdrian Chadd * AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT,
1176bd547bSAdrian Chadd * INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM
1276bd547bSAdrian Chadd * LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
1376bd547bSAdrian Chadd * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
1476bd547bSAdrian Chadd * PERFORMANCE OF THIS SOFTWARE.
1576bd547bSAdrian Chadd */
1676bd547bSAdrian Chadd
1776bd547bSAdrian Chadd #ifndef _ATH_AR9300_EEP_H_
1876bd547bSAdrian Chadd #define _ATH_AR9300_EEP_H_
1976bd547bSAdrian Chadd
2076bd547bSAdrian Chadd #include "opt_ah.h"
2176bd547bSAdrian Chadd #include "ah.h"
2276bd547bSAdrian Chadd
2376bd547bSAdrian Chadd #if defined(WIN32) || defined(WIN64)
2476bd547bSAdrian Chadd #pragma pack (push, ar9300, 1)
2576bd547bSAdrian Chadd #endif
2676bd547bSAdrian Chadd
2741137b06SAdrian Chadd /* Ensure that AH_BYTE_ORDER is defined */
2841137b06SAdrian Chadd #ifndef AH_BYTE_ORDER
2941137b06SAdrian Chadd #error AH_BYTE_ORDER needs to be defined!
3041137b06SAdrian Chadd #endif
3141137b06SAdrian Chadd
32e113789bSAdrian Chadd /* FreeBSD extras - should be in ah_eeprom.h ? */
33e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001
34e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_AES_DIS 0x0002
35e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004
36e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_BURST_DIS 0x0008
37e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_MAXQCU 0x01F0
38e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_MAXQCU_S 4
39e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200
40e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000
41e113789bSAdrian Chadd #define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12
42e113789bSAdrian Chadd
4376bd547bSAdrian Chadd
4476bd547bSAdrian Chadd #define MSTATE 100
4576bd547bSAdrian Chadd #define MOUTPUT 2048
4676bd547bSAdrian Chadd #define MDEFAULT 15
4776bd547bSAdrian Chadd #define MVALUE 100
4876bd547bSAdrian Chadd
4976bd547bSAdrian Chadd enum CompressAlgorithm
5076bd547bSAdrian Chadd {
5176bd547bSAdrian Chadd _compress_none = 0,
5276bd547bSAdrian Chadd _compress_lzma,
5376bd547bSAdrian Chadd _compress_pairs,
5476bd547bSAdrian Chadd _compress_block,
5576bd547bSAdrian Chadd _compress4,
5676bd547bSAdrian Chadd _compress5,
5776bd547bSAdrian Chadd _compress6,
5876bd547bSAdrian Chadd _compress7,
5976bd547bSAdrian Chadd };
6076bd547bSAdrian Chadd
6176bd547bSAdrian Chadd
6276bd547bSAdrian Chadd enum
6376bd547bSAdrian Chadd {
6476bd547bSAdrian Chadd calibration_data_none = 0,
6576bd547bSAdrian Chadd calibration_data_dram,
6676bd547bSAdrian Chadd calibration_data_flash,
6776bd547bSAdrian Chadd calibration_data_eeprom,
6876bd547bSAdrian Chadd calibration_data_otp,
6976bd547bSAdrian Chadd #ifdef ATH_CAL_NAND_FLASH
7076bd547bSAdrian Chadd calibration_data_nand,
7176bd547bSAdrian Chadd #endif
7276bd547bSAdrian Chadd CalibrationDataDontLoad,
7376bd547bSAdrian Chadd };
7476bd547bSAdrian Chadd #define HOST_CALDATA_SIZE (16*1024)
7576bd547bSAdrian Chadd
7676bd547bSAdrian Chadd //
7776bd547bSAdrian Chadd // DO NOT CHANGE THE DEFINTIONS OF THESE SYMBOLS.
7876bd547bSAdrian Chadd // Add additional definitions to the end.
7976bd547bSAdrian Chadd // Yes, the first one is 2. Do not use 0 or 1.
8076bd547bSAdrian Chadd //
8176bd547bSAdrian Chadd enum Ar9300EepromTemplate
8276bd547bSAdrian Chadd {
8376bd547bSAdrian Chadd ar9300_eeprom_template_generic = 2,
8476bd547bSAdrian Chadd ar9300_eeprom_template_hb112 = 3,
8576bd547bSAdrian Chadd ar9300_eeprom_template_hb116 = 4,
8676bd547bSAdrian Chadd ar9300_eeprom_template_xb112 = 5,
8776bd547bSAdrian Chadd ar9300_eeprom_template_xb113 = 6,
8876bd547bSAdrian Chadd ar9300_eeprom_template_xb114 = 7,
8976bd547bSAdrian Chadd ar9300_eeprom_template_tb417 = 8,
9076bd547bSAdrian Chadd ar9300_eeprom_template_ap111 = 9,
9176bd547bSAdrian Chadd ar9300_eeprom_template_ap121 = 10,
9276bd547bSAdrian Chadd ar9300_eeprom_template_hornet_generic = 11,
9376bd547bSAdrian Chadd ar9300_eeprom_template_wasp_2 = 12,
9476bd547bSAdrian Chadd ar9300_eeprom_template_wasp_k31 = 13,
9576bd547bSAdrian Chadd ar9300_eeprom_template_osprey_k31 = 14,
9676bd547bSAdrian Chadd ar9300_eeprom_template_aphrodite = 15
9776bd547bSAdrian Chadd };
9876bd547bSAdrian Chadd
9976bd547bSAdrian Chadd #define ar9300_eeprom_template_default ar9300_eeprom_template_generic
10076bd547bSAdrian Chadd #define Ar9300EepromFormatDefault 2
10176bd547bSAdrian Chadd
10276bd547bSAdrian Chadd #define reference_current 0
10376bd547bSAdrian Chadd #define compression_header_length 4
10476bd547bSAdrian Chadd #define compression_checksum_length 2
10576bd547bSAdrian Chadd
10676bd547bSAdrian Chadd #define OSPREY_EEP_VER 0xD000
10776bd547bSAdrian Chadd #define OSPREY_EEP_VER_MINOR_MASK 0xFFF
10876bd547bSAdrian Chadd #define OSPREY_EEP_MINOR_VER_1 0x1
10976bd547bSAdrian Chadd #define OSPREY_EEP_MINOR_VER OSPREY_EEP_MINOR_VER_1
11076bd547bSAdrian Chadd
11176bd547bSAdrian Chadd // 16-bit offset location start of calibration struct
11276bd547bSAdrian Chadd #define OSPREY_EEP_START_LOC 256
11376bd547bSAdrian Chadd #define OSPREY_NUM_5G_CAL_PIERS 8
11476bd547bSAdrian Chadd #define OSPREY_NUM_2G_CAL_PIERS 3
11576bd547bSAdrian Chadd #define OSPREY_NUM_5G_20_TARGET_POWERS 8
11676bd547bSAdrian Chadd #define OSPREY_NUM_5G_40_TARGET_POWERS 8
11776bd547bSAdrian Chadd #define OSPREY_NUM_2G_CCK_TARGET_POWERS 2
11876bd547bSAdrian Chadd #define OSPREY_NUM_2G_20_TARGET_POWERS 3
11976bd547bSAdrian Chadd #define OSPREY_NUM_2G_40_TARGET_POWERS 3
12076bd547bSAdrian Chadd //#define OSPREY_NUM_CTLS 21
12176bd547bSAdrian Chadd #define OSPREY_NUM_CTLS_5G 9
12276bd547bSAdrian Chadd #define OSPREY_NUM_CTLS_2G 12
12376bd547bSAdrian Chadd #define OSPREY_CTL_MODE_M 0xF
12476bd547bSAdrian Chadd #define OSPREY_NUM_BAND_EDGES_5G 8
12576bd547bSAdrian Chadd #define OSPREY_NUM_BAND_EDGES_2G 4
12676bd547bSAdrian Chadd #define OSPREY_NUM_PD_GAINS 4
12776bd547bSAdrian Chadd #define OSPREY_PD_GAINS_IN_MASK 4
12876bd547bSAdrian Chadd #define OSPREY_PD_GAIN_ICEPTS 5
12976bd547bSAdrian Chadd #define OSPREY_EEPROM_MODAL_SPURS 5
13076bd547bSAdrian Chadd #define OSPREY_MAX_RATE_POWER 63
13176bd547bSAdrian Chadd #define OSPREY_NUM_PDADC_VALUES 128
13276bd547bSAdrian Chadd #define OSPREY_NUM_RATES 16
13376bd547bSAdrian Chadd #define OSPREY_BCHAN_UNUSED 0xFF
13476bd547bSAdrian Chadd #define OSPREY_MAX_PWR_RANGE_IN_HALF_DB 64
13576bd547bSAdrian Chadd #define OSPREY_OPFLAGS_11A 0x01
13676bd547bSAdrian Chadd #define OSPREY_OPFLAGS_11G 0x02
13776bd547bSAdrian Chadd #define OSPREY_OPFLAGS_5G_HT40 0x04
13876bd547bSAdrian Chadd #define OSPREY_OPFLAGS_2G_HT40 0x08
13976bd547bSAdrian Chadd #define OSPREY_OPFLAGS_5G_HT20 0x10
14076bd547bSAdrian Chadd #define OSPREY_OPFLAGS_2G_HT20 0x20
14176bd547bSAdrian Chadd #define OSPREY_EEPMISC_BIG_ENDIAN 0x01
14276bd547bSAdrian Chadd #define OSPREY_EEPMISC_WOW 0x02
14376bd547bSAdrian Chadd #define OSPREY_CUSTOMER_DATA_SIZE 20
14476bd547bSAdrian Chadd
14576bd547bSAdrian Chadd #define FREQ2FBIN(x,y) \
1461696e1f2SSean Bruno (u_int8_t)(((y) == HAL_FREQ_BAND_2GHZ) ? ((x) - 2300) : (((x) - 4800) / 5))
14776bd547bSAdrian Chadd #define FBIN2FREQ(x,y) \
14876bd547bSAdrian Chadd (((y) == HAL_FREQ_BAND_2GHZ) ? (2300 + x) : (4800 + 5 * x))
14976bd547bSAdrian Chadd #define OSPREY_MAX_CHAINS 3
15076bd547bSAdrian Chadd #define OSPREY_ANT_16S 25
15176bd547bSAdrian Chadd #define OSPREY_FUTURE_MODAL_SZ 6
15276bd547bSAdrian Chadd
15376bd547bSAdrian Chadd #define OSPREY_NUM_ANT_CHAIN_FIELDS 7
15476bd547bSAdrian Chadd #define OSPREY_NUM_ANT_COMMON_FIELDS 4
15576bd547bSAdrian Chadd #define OSPREY_SIZE_ANT_CHAIN_FIELD 3
15676bd547bSAdrian Chadd #define OSPREY_SIZE_ANT_COMMON_FIELD 4
15776bd547bSAdrian Chadd #define OSPREY_ANT_CHAIN_MASK 0x7
15876bd547bSAdrian Chadd #define OSPREY_ANT_COMMON_MASK 0xf
15976bd547bSAdrian Chadd #define OSPREY_CHAIN_0_IDX 0
16076bd547bSAdrian Chadd #define OSPREY_CHAIN_1_IDX 1
16176bd547bSAdrian Chadd #define OSPREY_CHAIN_2_IDX 2
16276bd547bSAdrian Chadd #define OSPREY_1_CHAINMASK 1
16376bd547bSAdrian Chadd #define OSPREY_2LOHI_CHAINMASK 5
16476bd547bSAdrian Chadd #define OSPREY_2LOMID_CHAINMASK 3
16576bd547bSAdrian Chadd #define OSPREY_3_CHAINMASK 7
16676bd547bSAdrian Chadd
16776bd547bSAdrian Chadd #define AR928X_NUM_ANT_CHAIN_FIELDS 6
16876bd547bSAdrian Chadd #define AR928X_SIZE_ANT_CHAIN_FIELD 2
16976bd547bSAdrian Chadd #define AR928X_ANT_CHAIN_MASK 0x3
17076bd547bSAdrian Chadd
17176bd547bSAdrian Chadd /* Delta from which to start power to pdadc table */
17276bd547bSAdrian Chadd /* This offset is used in both open loop and closed loop power control
17376bd547bSAdrian Chadd * schemes. In open loop power control, it is not really needed, but for
17476bd547bSAdrian Chadd * the "sake of consistency" it was kept.
17576bd547bSAdrian Chadd * For certain AP designs, this value is overwritten by the value in the flag
17676bd547bSAdrian Chadd * "pwrTableOffset" just before writing the pdadc vs pwr into the chip registers.
17776bd547bSAdrian Chadd */
17876bd547bSAdrian Chadd #define OSPREY_PWR_TABLE_OFFSET 0
17976bd547bSAdrian Chadd
18076bd547bSAdrian Chadd //enable flags for voltage and temp compensation
18176bd547bSAdrian Chadd #define ENABLE_TEMP_COMPENSATION 0x01
18276bd547bSAdrian Chadd #define ENABLE_VOLT_COMPENSATION 0x02
18376bd547bSAdrian Chadd
18476bd547bSAdrian Chadd #define FLASH_BASE_CALDATA_OFFSET 0x1000
18576bd547bSAdrian Chadd #define AR9300_EEPROM_SIZE 16*1024 // byte addressable
18676bd547bSAdrian Chadd #define FIXED_CCA_THRESHOLD 15
18776bd547bSAdrian Chadd
18876bd547bSAdrian Chadd typedef struct eepFlags {
18976bd547bSAdrian Chadd u_int8_t op_flags;
19076bd547bSAdrian Chadd u_int8_t eepMisc;
19176bd547bSAdrian Chadd } __packed EEP_FLAGS;
19276bd547bSAdrian Chadd
19376bd547bSAdrian Chadd typedef enum targetPowerHTRates {
19476bd547bSAdrian Chadd HT_TARGET_RATE_0_8_16,
19576bd547bSAdrian Chadd HT_TARGET_RATE_1_3_9_11_17_19,
19676bd547bSAdrian Chadd HT_TARGET_RATE_4,
19776bd547bSAdrian Chadd HT_TARGET_RATE_5,
19876bd547bSAdrian Chadd HT_TARGET_RATE_6,
19976bd547bSAdrian Chadd HT_TARGET_RATE_7,
20076bd547bSAdrian Chadd HT_TARGET_RATE_12,
20176bd547bSAdrian Chadd HT_TARGET_RATE_13,
20276bd547bSAdrian Chadd HT_TARGET_RATE_14,
20376bd547bSAdrian Chadd HT_TARGET_RATE_15,
20476bd547bSAdrian Chadd HT_TARGET_RATE_20,
20576bd547bSAdrian Chadd HT_TARGET_RATE_21,
20676bd547bSAdrian Chadd HT_TARGET_RATE_22,
20776bd547bSAdrian Chadd HT_TARGET_RATE_23
20876bd547bSAdrian Chadd }TARGET_POWER_HT_RATES;
20976bd547bSAdrian Chadd
21076bd547bSAdrian Chadd const static int mapRate2Index[24]=
21176bd547bSAdrian Chadd {
21276bd547bSAdrian Chadd 0,1,1,1,2,
21376bd547bSAdrian Chadd 3,4,5,0,1,
21476bd547bSAdrian Chadd 1,1,6,7,8,
21576bd547bSAdrian Chadd 9,0,1,1,1,
21676bd547bSAdrian Chadd 10,11,12,13
21776bd547bSAdrian Chadd };
21876bd547bSAdrian Chadd
21976bd547bSAdrian Chadd typedef enum targetPowerLegacyRates {
22076bd547bSAdrian Chadd LEGACY_TARGET_RATE_6_24,
22176bd547bSAdrian Chadd LEGACY_TARGET_RATE_36,
22276bd547bSAdrian Chadd LEGACY_TARGET_RATE_48,
22376bd547bSAdrian Chadd LEGACY_TARGET_RATE_54
22476bd547bSAdrian Chadd }TARGET_POWER_LEGACY_RATES;
22576bd547bSAdrian Chadd
22676bd547bSAdrian Chadd typedef enum targetPowerCckRates {
22776bd547bSAdrian Chadd LEGACY_TARGET_RATE_1L_5L,
22876bd547bSAdrian Chadd LEGACY_TARGET_RATE_5S,
22976bd547bSAdrian Chadd LEGACY_TARGET_RATE_11L,
23076bd547bSAdrian Chadd LEGACY_TARGET_RATE_11S
23176bd547bSAdrian Chadd }TARGET_POWER_CCK_RATES;
23276bd547bSAdrian Chadd
23376bd547bSAdrian Chadd #define MAX_MODAL_RESERVED 11
23476bd547bSAdrian Chadd #define MAX_MODAL_FUTURE 5
23576bd547bSAdrian Chadd #define MAX_BASE_EXTENSION_FUTURE 2
23676bd547bSAdrian Chadd #define MAX_TEMP_SLOPE 8
23776bd547bSAdrian Chadd #define OSPREY_CHECKSUM_LOCATION (OSPREY_EEP_START_LOC + 1)
23876bd547bSAdrian Chadd
23976bd547bSAdrian Chadd typedef struct osprey_BaseEepHeader {
24076bd547bSAdrian Chadd u_int16_t reg_dmn[2]; //Does this need to be outside of this structure, if it gets written after calibration
24176bd547bSAdrian Chadd u_int8_t txrx_mask; //4 bits tx and 4 bits rx
24276bd547bSAdrian Chadd EEP_FLAGS op_cap_flags;
24376bd547bSAdrian Chadd u_int8_t rf_silent;
24476bd547bSAdrian Chadd u_int8_t blue_tooth_options;
24576bd547bSAdrian Chadd u_int8_t device_cap;
24676bd547bSAdrian Chadd u_int8_t device_type; // takes lower byte in eeprom location
24776bd547bSAdrian Chadd int8_t pwrTableOffset; // offset in dB to be added to beginning of pdadc table in calibration
24876bd547bSAdrian Chadd u_int8_t params_for_tuning_caps[2]; //placeholder, get more details from Don
24976bd547bSAdrian Chadd u_int8_t feature_enable; //bit0 - enable tx temp comp
25076bd547bSAdrian Chadd //bit1 - enable tx volt comp
25176bd547bSAdrian Chadd //bit2 - enable fastClock - default to 1
25276bd547bSAdrian Chadd //bit3 - enable doubling - default to 1
25376bd547bSAdrian Chadd //bit4 - enable internal regulator - default to 1
25476bd547bSAdrian Chadd //bit5 - enable paprd - default to 0
25576bd547bSAdrian Chadd //bit6 - enable TuningCaps - default to 0
25676bd547bSAdrian Chadd //bit7 - enable tx_frame_to_xpa_on - default to 0
25776bd547bSAdrian Chadd u_int8_t misc_configuration; //misc flags: bit0 - turn down drivestrength
25876bd547bSAdrian Chadd // bit 1:2 - 0=don't force, 1=force to thermometer 0, 2=force to thermometer 1, 3=force to thermometer 2
25976bd547bSAdrian Chadd // bit 3 - reduce chain mask from 0x7 to 0x3 on 2 stream rates
26076bd547bSAdrian Chadd // bit 4 - enable quick drop
26176bd547bSAdrian Chadd // bit 5 - enable 8 temp slop
26276bd547bSAdrian Chadd // bit 6; enable xLNA_bias_strength
26376bd547bSAdrian Chadd // bit 7; enable rf_gain_cap
26476bd547bSAdrian Chadd u_int8_t eeprom_write_enable_gpio;
26576bd547bSAdrian Chadd u_int8_t wlan_disable_gpio;
26676bd547bSAdrian Chadd u_int8_t wlan_led_gpio;
26776bd547bSAdrian Chadd u_int8_t rx_band_select_gpio;
26876bd547bSAdrian Chadd u_int8_t txrxgain;
26976bd547bSAdrian Chadd u_int32_t swreg; // SW controlled internal regulator fields
27076bd547bSAdrian Chadd } __packed OSPREY_BASE_EEP_HEADER;
27176bd547bSAdrian Chadd
27276bd547bSAdrian Chadd typedef struct osprey_BaseExtension_1 {
27376bd547bSAdrian Chadd u_int8_t ant_div_control;
27476bd547bSAdrian Chadd u_int8_t future[MAX_BASE_EXTENSION_FUTURE];
27576bd547bSAdrian Chadd u_int8_t misc_enable;
27676bd547bSAdrian Chadd int8_t tempslopextension[MAX_TEMP_SLOPE];
27776bd547bSAdrian Chadd int8_t quick_drop_low;
27876bd547bSAdrian Chadd int8_t quick_drop_high;
27976bd547bSAdrian Chadd } __packed OSPREY_BASE_EXTENSION_1;
28076bd547bSAdrian Chadd
28176bd547bSAdrian Chadd typedef struct osprey_BaseExtension_2 {
28276bd547bSAdrian Chadd int8_t temp_slope_low;
28376bd547bSAdrian Chadd int8_t temp_slope_high;
28476bd547bSAdrian Chadd u_int8_t xatten1_db_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
28576bd547bSAdrian Chadd u_int8_t xatten1_margin_low[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
28676bd547bSAdrian Chadd u_int8_t xatten1_db_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
28776bd547bSAdrian Chadd u_int8_t xatten1_margin_high[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
28876bd547bSAdrian Chadd } __packed OSPREY_BASE_EXTENSION_2;
28976bd547bSAdrian Chadd
29076bd547bSAdrian Chadd typedef struct spurChanStruct {
29176bd547bSAdrian Chadd u_int16_t spur_chan;
29276bd547bSAdrian Chadd u_int8_t spurRangeLow;
29376bd547bSAdrian Chadd u_int8_t spurRangeHigh;
29476bd547bSAdrian Chadd } __packed SPUR_CHAN;
29576bd547bSAdrian Chadd
29676bd547bSAdrian Chadd //Note the order of the fields in this structure has been optimized to put all fields likely to change together
29776bd547bSAdrian Chadd typedef struct ospreyModalEepHeader {
29876bd547bSAdrian Chadd u_int32_t ant_ctrl_common; // 4 idle, t1, t2, b (4 bits per setting)
29976bd547bSAdrian Chadd u_int32_t ant_ctrl_common2; // 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12
30076bd547bSAdrian Chadd u_int16_t ant_ctrl_chain[OSPREY_MAX_CHAINS]; // 6 idle, t, r, rx1, rx12, b (2 bits each)
30176bd547bSAdrian Chadd u_int8_t xatten1_db[OSPREY_MAX_CHAINS]; // 3 //xatten1_db for merlin (0xa20c/b20c 5:0)
30276bd547bSAdrian Chadd u_int8_t xatten1_margin[OSPREY_MAX_CHAINS]; // 3 //xatten1_margin for merlin (0xa20c/b20c 16:12
30376bd547bSAdrian Chadd int8_t temp_slope;
30476bd547bSAdrian Chadd int8_t voltSlope;
30576bd547bSAdrian Chadd u_int8_t spur_chans[OSPREY_EEPROM_MODAL_SPURS]; // spur channels in usual fbin coding format
30676bd547bSAdrian Chadd int8_t noise_floor_thresh_ch[OSPREY_MAX_CHAINS];// 3 //Check if the register is per chain
30776bd547bSAdrian Chadd u_int8_t reserved[MAX_MODAL_RESERVED];
30876bd547bSAdrian Chadd int8_t quick_drop;
30976bd547bSAdrian Chadd u_int8_t xpa_bias_lvl; // 1
31076bd547bSAdrian Chadd u_int8_t tx_frame_to_data_start; // 1
31176bd547bSAdrian Chadd u_int8_t tx_frame_to_pa_on; // 1
31276bd547bSAdrian Chadd u_int8_t txClip; // 4 bits tx_clip, 4 bits dac_scale_cck
31376bd547bSAdrian Chadd int8_t antenna_gain; // 1
31476bd547bSAdrian Chadd u_int8_t switchSettling; // 1
31576bd547bSAdrian Chadd int8_t adcDesiredSize; // 1
31676bd547bSAdrian Chadd u_int8_t tx_end_to_xpa_off; // 1
31776bd547bSAdrian Chadd u_int8_t txEndToRxOn; // 1
31876bd547bSAdrian Chadd u_int8_t tx_frame_to_xpa_on; // 1
31976bd547bSAdrian Chadd u_int8_t thresh62; // 1
32076bd547bSAdrian Chadd u_int32_t paprd_rate_mask_ht20;
32176bd547bSAdrian Chadd u_int32_t paprd_rate_mask_ht40;
32276bd547bSAdrian Chadd u_int16_t switchcomspdt;
32376bd547bSAdrian Chadd u_int8_t xLNA_bias_strength; // bit: 0,1:chain0, 2,3:chain1, 4,5:chain2
32476bd547bSAdrian Chadd u_int8_t rf_gain_cap;
32576bd547bSAdrian Chadd u_int8_t tx_gain_cap; // bit0:4 txgain cap, txgain index for max_txgain + 20 (10dBm higher than max txgain)
32676bd547bSAdrian Chadd u_int8_t futureModal[MAX_MODAL_FUTURE];
32776bd547bSAdrian Chadd // last 12 bytes stolen and moved to newly created base extension structure
32876bd547bSAdrian Chadd } __packed OSPREY_MODAL_EEP_HEADER; // == 100 B
32976bd547bSAdrian Chadd
33076bd547bSAdrian Chadd typedef struct ospCalDataPerFreqOpLoop {
33176bd547bSAdrian Chadd int8_t ref_power; /* */
33276bd547bSAdrian Chadd u_int8_t volt_meas; /* pdadc voltage at power measurement */
33376bd547bSAdrian Chadd u_int8_t temp_meas; /* pcdac used for power measurement */
33476bd547bSAdrian Chadd int8_t rx_noisefloor_cal; /*range is -60 to -127 create a mapping equation 1db resolution */
33576bd547bSAdrian Chadd int8_t rx_noisefloor_power; /*range is same as noisefloor */
33676bd547bSAdrian Chadd u_int8_t rxTempMeas; /*temp measured when noisefloor cal was performed */
33776bd547bSAdrian Chadd } __packed OSP_CAL_DATA_PER_FREQ_OP_LOOP;
33876bd547bSAdrian Chadd
33976bd547bSAdrian Chadd typedef struct CalTargetPowerLegacy {
34076bd547bSAdrian Chadd u_int8_t t_pow2x[4];
34176bd547bSAdrian Chadd } __packed CAL_TARGET_POWER_LEG;
34276bd547bSAdrian Chadd
34376bd547bSAdrian Chadd typedef struct ospCalTargetPowerHt {
34476bd547bSAdrian Chadd u_int8_t t_pow2x[14];
34576bd547bSAdrian Chadd } __packed OSP_CAL_TARGET_POWER_HT;
34676bd547bSAdrian Chadd
34776bd547bSAdrian Chadd #if AH_BYTE_ORDER == AH_BIG_ENDIAN
34876bd547bSAdrian Chadd typedef struct CalCtlEdgePwr {
34976bd547bSAdrian Chadd u_int8_t flag :2,
35076bd547bSAdrian Chadd t_power :6;
35176bd547bSAdrian Chadd } __packed CAL_CTL_EDGE_PWR;
35241137b06SAdrian Chadd #elif AH_BYTE_ORDER == AH_LITTLE_ENDIAN
35376bd547bSAdrian Chadd typedef struct CalCtlEdgePwr {
35476bd547bSAdrian Chadd u_int8_t t_power :6,
35576bd547bSAdrian Chadd flag :2;
35676bd547bSAdrian Chadd } __packed CAL_CTL_EDGE_PWR;
35741137b06SAdrian Chadd #else
35841137b06SAdrian Chadd #error AH_BYTE_ORDER undefined!
35976bd547bSAdrian Chadd #endif
36076bd547bSAdrian Chadd
36176bd547bSAdrian Chadd typedef struct ospCalCtlData_5G {
36276bd547bSAdrian Chadd CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_5G];
36376bd547bSAdrian Chadd } __packed OSP_CAL_CTL_DATA_5G;
36476bd547bSAdrian Chadd
36576bd547bSAdrian Chadd typedef struct ospCalCtlData_2G {
36676bd547bSAdrian Chadd CAL_CTL_EDGE_PWR ctl_edges[OSPREY_NUM_BAND_EDGES_2G];
36776bd547bSAdrian Chadd } __packed OSP_CAL_CTL_DATA_2G;
36876bd547bSAdrian Chadd
36976bd547bSAdrian Chadd typedef struct ospreyEeprom {
37076bd547bSAdrian Chadd u_int8_t eeprom_version;
37176bd547bSAdrian Chadd u_int8_t template_version;
37276bd547bSAdrian Chadd u_int8_t mac_addr[6];
37376bd547bSAdrian Chadd u_int8_t custData[OSPREY_CUSTOMER_DATA_SIZE];
37476bd547bSAdrian Chadd
37576bd547bSAdrian Chadd OSPREY_BASE_EEP_HEADER base_eep_header;
37676bd547bSAdrian Chadd
37776bd547bSAdrian Chadd OSPREY_MODAL_EEP_HEADER modal_header_2g;
37876bd547bSAdrian Chadd OSPREY_BASE_EXTENSION_1 base_ext1;
37976bd547bSAdrian Chadd u_int8_t cal_freq_pier_2g[OSPREY_NUM_2G_CAL_PIERS];
38076bd547bSAdrian Chadd OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_2g[OSPREY_MAX_CHAINS][OSPREY_NUM_2G_CAL_PIERS];
38176bd547bSAdrian Chadd u_int8_t cal_target_freqbin_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
38276bd547bSAdrian Chadd u_int8_t cal_target_freqbin_2g[OSPREY_NUM_2G_20_TARGET_POWERS];
38376bd547bSAdrian Chadd u_int8_t cal_target_freqbin_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS];
38476bd547bSAdrian Chadd u_int8_t cal_target_freqbin_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS];
38576bd547bSAdrian Chadd CAL_TARGET_POWER_LEG cal_target_power_cck[OSPREY_NUM_2G_CCK_TARGET_POWERS];
38676bd547bSAdrian Chadd CAL_TARGET_POWER_LEG cal_target_power_2g[OSPREY_NUM_2G_20_TARGET_POWERS];
38776bd547bSAdrian Chadd OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht20[OSPREY_NUM_2G_20_TARGET_POWERS];
38876bd547bSAdrian Chadd OSP_CAL_TARGET_POWER_HT cal_target_power_2g_ht40[OSPREY_NUM_2G_40_TARGET_POWERS];
38976bd547bSAdrian Chadd u_int8_t ctl_index_2g[OSPREY_NUM_CTLS_2G];
39076bd547bSAdrian Chadd u_int8_t ctl_freqbin_2G[OSPREY_NUM_CTLS_2G][OSPREY_NUM_BAND_EDGES_2G];
39176bd547bSAdrian Chadd OSP_CAL_CTL_DATA_2G ctl_power_data_2g[OSPREY_NUM_CTLS_2G];
39276bd547bSAdrian Chadd
39376bd547bSAdrian Chadd OSPREY_MODAL_EEP_HEADER modal_header_5g;
39476bd547bSAdrian Chadd OSPREY_BASE_EXTENSION_2 base_ext2;
39576bd547bSAdrian Chadd u_int8_t cal_freq_pier_5g[OSPREY_NUM_5G_CAL_PIERS];
39676bd547bSAdrian Chadd OSP_CAL_DATA_PER_FREQ_OP_LOOP cal_pier_data_5g[OSPREY_MAX_CHAINS][OSPREY_NUM_5G_CAL_PIERS];
39776bd547bSAdrian Chadd u_int8_t cal_target_freqbin_5g[OSPREY_NUM_5G_20_TARGET_POWERS];
39876bd547bSAdrian Chadd u_int8_t cal_target_freqbin_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS];
39976bd547bSAdrian Chadd u_int8_t cal_target_freqbin_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS];
40076bd547bSAdrian Chadd CAL_TARGET_POWER_LEG cal_target_power_5g[OSPREY_NUM_5G_20_TARGET_POWERS];
40176bd547bSAdrian Chadd OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht20[OSPREY_NUM_5G_20_TARGET_POWERS];
40276bd547bSAdrian Chadd OSP_CAL_TARGET_POWER_HT cal_target_power_5g_ht40[OSPREY_NUM_5G_40_TARGET_POWERS];
40376bd547bSAdrian Chadd u_int8_t ctl_index_5g[OSPREY_NUM_CTLS_5G];
40476bd547bSAdrian Chadd u_int8_t ctl_freqbin_5G[OSPREY_NUM_CTLS_5G][OSPREY_NUM_BAND_EDGES_5G];
40576bd547bSAdrian Chadd OSP_CAL_CTL_DATA_5G ctl_power_data_5g[OSPREY_NUM_CTLS_5G];
40676bd547bSAdrian Chadd } __packed ar9300_eeprom_t;
40776bd547bSAdrian Chadd
40876bd547bSAdrian Chadd
40976bd547bSAdrian Chadd /*
41076bd547bSAdrian Chadd ** SWAP Functions
41176bd547bSAdrian Chadd ** used to read EEPROM data, which is apparently stored in little
41276bd547bSAdrian Chadd ** endian form. We have included both forms of the swap functions,
41376bd547bSAdrian Chadd ** one for big endian and one for little endian. The indices of the
41476bd547bSAdrian Chadd ** array elements are the differences
41576bd547bSAdrian Chadd */
41676bd547bSAdrian Chadd #if AH_BYTE_ORDER == AH_BIG_ENDIAN
41776bd547bSAdrian Chadd
41876bd547bSAdrian Chadd #define AR9300_EEPROM_MAGIC 0x5aa5
41976bd547bSAdrian Chadd #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[0] ) |\
42076bd547bSAdrian Chadd ( ( (const u_int8_t *)( &_x ) )[1]<< 8) ) )
42176bd547bSAdrian Chadd
42276bd547bSAdrian Chadd #define SWAP32(_x) ((u_int32_t)( \
42376bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[0]) | \
42476bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[1]<< 8) | \
42576bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[2]<<16) | \
42676bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[3]<<24)))
42776bd547bSAdrian Chadd
42876bd547bSAdrian Chadd #else // AH_BYTE_ORDER
42976bd547bSAdrian Chadd
43076bd547bSAdrian Chadd #define AR9300_EEPROM_MAGIC 0xa55a
43176bd547bSAdrian Chadd #define SWAP16(_x) ( (u_int16_t)( (((const u_int8_t *)(&_x))[1] ) |\
43276bd547bSAdrian Chadd ( ( (const u_int8_t *)( &_x ) )[0]<< 8) ) )
43376bd547bSAdrian Chadd
43476bd547bSAdrian Chadd #define SWAP32(_x) ((u_int32_t)( \
43576bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[3]) | \
43676bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[2]<< 8) | \
43776bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[1]<<16) | \
43876bd547bSAdrian Chadd (((const u_int8_t *)(&_x))[0]<<24)))
43976bd547bSAdrian Chadd
44076bd547bSAdrian Chadd #endif // AH_BYTE_ORDER
44176bd547bSAdrian Chadd
44276bd547bSAdrian Chadd // OTP registers for OSPREY
44376bd547bSAdrian Chadd
44476bd547bSAdrian Chadd #define AR_GPIO_IN_OUT 0x4048 // GPIO input / output register
44576bd547bSAdrian Chadd #define OTP_MEM_START_ADDRESS 0x14000
44676bd547bSAdrian Chadd #define OTP_STATUS0_OTP_SM_BUSY 0x00015f18
44776bd547bSAdrian Chadd #define OTP_STATUS1_EFUSE_READ_DATA 0x00015f1c
44876bd547bSAdrian Chadd
44976bd547bSAdrian Chadd #define OTP_LDO_CONTROL_ENABLE 0x00015f24
45076bd547bSAdrian Chadd #define OTP_LDO_STATUS_POWER_ON 0x00015f2c
45176bd547bSAdrian Chadd #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00015f00
45276bd547bSAdrian Chadd // OTP register for Jupiter
45376bd547bSAdrian Chadd #define GLB_OTP_LDO_CONTROL_ENABLE 0x00020020
45476bd547bSAdrian Chadd #define GLB_OTP_LDO_STATUS_POWER_ON 0x00020028
45576bd547bSAdrian Chadd #define OTP_PGENB_SETUP_HOLD_TIME_DELAY 0x15f34
45676bd547bSAdrian Chadd
45776bd547bSAdrian Chadd // OTP register for Jupiter BT
45876bd547bSAdrian Chadd #define BTOTP_MEM_START_ADDRESS 0x64000
45976bd547bSAdrian Chadd #define BTOTP_STATUS0_OTP_SM_BUSY 0x00065f18
46076bd547bSAdrian Chadd #define BTOTP_STATUS1_EFUSE_READ_DATA 0x00065f1c
46176bd547bSAdrian Chadd #define BTOTP_INTF0_EFUSE_WR_ENABLE_REG_V 0x00065f00
46276bd547bSAdrian Chadd #define BTOTP_INTF2 0x00065f08
46376bd547bSAdrian Chadd #define BTOTP_PGENB_SETUP_HOLD_TIME_DELAY 0x65f34
46476bd547bSAdrian Chadd #define BT_RESET_CTL 0x44000
46576bd547bSAdrian Chadd #define BT_CLOCK_CONTROL 0x44028
46676bd547bSAdrian Chadd
46776bd547bSAdrian Chadd
46876bd547bSAdrian Chadd // OTP register for WASP
46976bd547bSAdrian Chadd #define OTP_MEM_START_ADDRESS_WASP 0x00030000
47076bd547bSAdrian Chadd #define OTP_STATUS0_OTP_SM_BUSY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1018)
47176bd547bSAdrian Chadd #define OTP_STATUS1_EFUSE_READ_DATA_WASP (OTP_MEM_START_ADDRESS_WASP + 0x101C)
47276bd547bSAdrian Chadd #define OTP_LDO_CONTROL_ENABLE_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1024)
47376bd547bSAdrian Chadd #define OTP_LDO_STATUS_POWER_ON_WASP (OTP_MEM_START_ADDRESS_WASP + 0x102C)
47476bd547bSAdrian Chadd #define OTP_INTF0_EFUSE_WR_ENABLE_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1000)
47576bd547bSAdrian Chadd // Below control the access timing of OTP read/write
47676bd547bSAdrian Chadd #define OTP_PG_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1008)
47776bd547bSAdrian Chadd #define OTP_RD_STROBE_PW_REG_V_WASP (OTP_MEM_START_ADDRESS_WASP + 0x100C)
47876bd547bSAdrian Chadd #define OTP_VDDQ_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1030)
47976bd547bSAdrian Chadd #define OTP_PGENB_SETUP_HOLD_TIME_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1034)
48076bd547bSAdrian Chadd #define OTP_STROBE_PULSE_INTERVAL_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x1038)
48176bd547bSAdrian Chadd #define OTP_CSB_ADDR_LOAD_SETUP_HOLD_DELAY_WASP (OTP_MEM_START_ADDRESS_WASP + 0x103C)
48276bd547bSAdrian Chadd
48376bd547bSAdrian Chadd #define AR9300_EEPROM_MAGIC_OFFSET 0x0
48476bd547bSAdrian Chadd /* reg_off = 4 * (eep_off) */
48576bd547bSAdrian Chadd #define AR9300_EEPROM_S 2
48676bd547bSAdrian Chadd #define AR9300_EEPROM_OFFSET 0x2000
48776bd547bSAdrian Chadd #ifdef AR9100
48876bd547bSAdrian Chadd #define AR9300_EEPROM_START_ADDR 0x1fff1000
48976bd547bSAdrian Chadd #else
49076bd547bSAdrian Chadd #define AR9300_EEPROM_START_ADDR 0x503f1200
49176bd547bSAdrian Chadd #endif
49276bd547bSAdrian Chadd #define AR9300_FLASH_CAL_START_OFFSET 0x1000
49376bd547bSAdrian Chadd #define AR9300_EEPROM_MAX 0xae0
49476bd547bSAdrian Chadd #define IS_EEP_MINOR_V3(_ahp) (ar9300_eeprom_get((_ahp), EEP_MINOR_REV) >= AR9300_EEP_MINOR_VER_3)
49576bd547bSAdrian Chadd
49676bd547bSAdrian Chadd #define ar9300_get_ntxchains(_txchainmask) \
49776bd547bSAdrian Chadd (((_txchainmask >> 2) & 1) + ((_txchainmask >> 1) & 1) + (_txchainmask & 1))
49876bd547bSAdrian Chadd
49976bd547bSAdrian Chadd /* RF silent fields in \ */
50076bd547bSAdrian Chadd #define EEP_RFSILENT_ENABLED 0x0001 /* bit 0: enabled/disabled */
50176bd547bSAdrian Chadd #define EEP_RFSILENT_ENABLED_S 0 /* bit 0: enabled/disabled */
50276bd547bSAdrian Chadd #define EEP_RFSILENT_POLARITY 0x0002 /* bit 1: polarity */
50376bd547bSAdrian Chadd #define EEP_RFSILENT_POLARITY_S 1 /* bit 1: polarity */
50476bd547bSAdrian Chadd #define EEP_RFSILENT_GPIO_SEL 0x00fc /* bits 2..7: gpio PIN */
50576bd547bSAdrian Chadd #define EEP_RFSILENT_GPIO_SEL_S 2 /* bits 2..7: gpio PIN */
50676bd547bSAdrian Chadd #define AR9300_EEP_VER 0xE
50776bd547bSAdrian Chadd #define AR9300_BCHAN_UNUSED 0xFF
50876bd547bSAdrian Chadd #define AR9300_MAX_RATE_POWER 63
50976bd547bSAdrian Chadd
51076bd547bSAdrian Chadd typedef enum {
51176bd547bSAdrian Chadd CALDATA_AUTO=0,
51276bd547bSAdrian Chadd CALDATA_EEPROM,
51376bd547bSAdrian Chadd CALDATA_FLASH,
51476bd547bSAdrian Chadd CALDATA_OTP
51576bd547bSAdrian Chadd } CALDATA_TYPE;
51676bd547bSAdrian Chadd
51776bd547bSAdrian Chadd typedef enum {
51876bd547bSAdrian Chadd EEP_NFTHRESH_5,
51976bd547bSAdrian Chadd EEP_NFTHRESH_2,
52076bd547bSAdrian Chadd EEP_MAC_MSW,
52176bd547bSAdrian Chadd EEP_MAC_MID,
52276bd547bSAdrian Chadd EEP_MAC_LSW,
52376bd547bSAdrian Chadd EEP_REG_0,
52476bd547bSAdrian Chadd EEP_REG_1,
52576bd547bSAdrian Chadd EEP_OP_CAP,
52676bd547bSAdrian Chadd EEP_OP_MODE,
52776bd547bSAdrian Chadd EEP_RF_SILENT,
52876bd547bSAdrian Chadd EEP_OB_5,
52976bd547bSAdrian Chadd EEP_DB_5,
53076bd547bSAdrian Chadd EEP_OB_2,
53176bd547bSAdrian Chadd EEP_DB_2,
53276bd547bSAdrian Chadd EEP_MINOR_REV,
53376bd547bSAdrian Chadd EEP_TX_MASK,
53476bd547bSAdrian Chadd EEP_RX_MASK,
53576bd547bSAdrian Chadd EEP_FSTCLK_5G,
53676bd547bSAdrian Chadd EEP_RXGAIN_TYPE,
53776bd547bSAdrian Chadd EEP_OL_PWRCTRL,
53876bd547bSAdrian Chadd EEP_TXGAIN_TYPE,
53976bd547bSAdrian Chadd EEP_RC_CHAIN_MASK,
54076bd547bSAdrian Chadd EEP_DAC_HPWR_5G,
54176bd547bSAdrian Chadd EEP_FRAC_N_5G,
54276bd547bSAdrian Chadd EEP_DEV_TYPE,
54376bd547bSAdrian Chadd EEP_TEMPSENSE_SLOPE,
54476bd547bSAdrian Chadd EEP_TEMPSENSE_SLOPE_PAL_ON,
54576bd547bSAdrian Chadd EEP_PWR_TABLE_OFFSET,
54676bd547bSAdrian Chadd EEP_DRIVE_STRENGTH,
54776bd547bSAdrian Chadd EEP_INTERNAL_REGULATOR,
54876bd547bSAdrian Chadd EEP_SWREG,
54976bd547bSAdrian Chadd EEP_PAPRD_ENABLED,
55076bd547bSAdrian Chadd EEP_ANTDIV_control,
55176bd547bSAdrian Chadd EEP_CHAIN_MASK_REDUCE,
55276bd547bSAdrian Chadd } EEPROM_PARAM;
55376bd547bSAdrian Chadd
55476bd547bSAdrian Chadd #define AR9300_RATES_OFDM_OFFSET 0
55576bd547bSAdrian Chadd #define AR9300_RATES_CCK_OFFSET 4
55676bd547bSAdrian Chadd #define AR9300_RATES_HT20_OFFSET 8
55776bd547bSAdrian Chadd #define AR9300_RATES_HT40_OFFSET 22
55876bd547bSAdrian Chadd typedef enum ar9300_Rates {
55976bd547bSAdrian Chadd ALL_TARGET_LEGACY_6_24,
56076bd547bSAdrian Chadd ALL_TARGET_LEGACY_36,
56176bd547bSAdrian Chadd ALL_TARGET_LEGACY_48,
56276bd547bSAdrian Chadd ALL_TARGET_LEGACY_54,
56376bd547bSAdrian Chadd ALL_TARGET_LEGACY_1L_5L,
56476bd547bSAdrian Chadd ALL_TARGET_LEGACY_5S,
56576bd547bSAdrian Chadd ALL_TARGET_LEGACY_11L,
56676bd547bSAdrian Chadd ALL_TARGET_LEGACY_11S,
56776bd547bSAdrian Chadd ALL_TARGET_HT20_0_8_16,
56876bd547bSAdrian Chadd ALL_TARGET_HT20_1_3_9_11_17_19,
56976bd547bSAdrian Chadd ALL_TARGET_HT20_4,
57076bd547bSAdrian Chadd ALL_TARGET_HT20_5,
57176bd547bSAdrian Chadd ALL_TARGET_HT20_6,
57276bd547bSAdrian Chadd ALL_TARGET_HT20_7,
57376bd547bSAdrian Chadd ALL_TARGET_HT20_12,
57476bd547bSAdrian Chadd ALL_TARGET_HT20_13,
57576bd547bSAdrian Chadd ALL_TARGET_HT20_14,
57676bd547bSAdrian Chadd ALL_TARGET_HT20_15,
57776bd547bSAdrian Chadd ALL_TARGET_HT20_20,
57876bd547bSAdrian Chadd ALL_TARGET_HT20_21,
57976bd547bSAdrian Chadd ALL_TARGET_HT20_22,
58076bd547bSAdrian Chadd ALL_TARGET_HT20_23,
58176bd547bSAdrian Chadd ALL_TARGET_HT40_0_8_16,
58276bd547bSAdrian Chadd ALL_TARGET_HT40_1_3_9_11_17_19,
58376bd547bSAdrian Chadd ALL_TARGET_HT40_4,
58476bd547bSAdrian Chadd ALL_TARGET_HT40_5,
58576bd547bSAdrian Chadd ALL_TARGET_HT40_6,
58676bd547bSAdrian Chadd ALL_TARGET_HT40_7,
58776bd547bSAdrian Chadd ALL_TARGET_HT40_12,
58876bd547bSAdrian Chadd ALL_TARGET_HT40_13,
58976bd547bSAdrian Chadd ALL_TARGET_HT40_14,
59076bd547bSAdrian Chadd ALL_TARGET_HT40_15,
59176bd547bSAdrian Chadd ALL_TARGET_HT40_20,
59276bd547bSAdrian Chadd ALL_TARGET_HT40_21,
59376bd547bSAdrian Chadd ALL_TARGET_HT40_22,
59476bd547bSAdrian Chadd ALL_TARGET_HT40_23,
59576bd547bSAdrian Chadd ar9300_rate_size
59676bd547bSAdrian Chadd } AR9300_RATES;
59776bd547bSAdrian Chadd
59876bd547bSAdrian Chadd
59976bd547bSAdrian Chadd /**************************************************************************
60076bd547bSAdrian Chadd * fbin2freq
60176bd547bSAdrian Chadd *
60276bd547bSAdrian Chadd * Get channel value from binary representation held in eeprom
60376bd547bSAdrian Chadd * RETURNS: the frequency in MHz
60476bd547bSAdrian Chadd */
60576bd547bSAdrian Chadd static inline u_int16_t
fbin2freq(u_int8_t fbin,HAL_BOOL is_2ghz)60676bd547bSAdrian Chadd fbin2freq(u_int8_t fbin, HAL_BOOL is_2ghz)
60776bd547bSAdrian Chadd {
60876bd547bSAdrian Chadd /*
60976bd547bSAdrian Chadd * Reserved value 0xFF provides an empty definition both as
61076bd547bSAdrian Chadd * an fbin and as a frequency - do not convert
61176bd547bSAdrian Chadd */
61276bd547bSAdrian Chadd if (fbin == AR9300_BCHAN_UNUSED)
61376bd547bSAdrian Chadd {
61476bd547bSAdrian Chadd return fbin;
61576bd547bSAdrian Chadd }
61676bd547bSAdrian Chadd
61776bd547bSAdrian Chadd return (u_int16_t)((is_2ghz) ? (2300 + fbin) : (4800 + 5 * fbin));
61876bd547bSAdrian Chadd }
61976bd547bSAdrian Chadd
62076bd547bSAdrian Chadd extern int CompressionHeaderUnpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor);
62176bd547bSAdrian Chadd extern void Ar9300EepromFormatConvert(ar9300_eeprom_t *mptr);
62276bd547bSAdrian Chadd extern HAL_BOOL ar9300_eeprom_restore(struct ath_hal *ah);
62376bd547bSAdrian Chadd extern int ar9300_eeprom_restore_internal(struct ath_hal *ah, ar9300_eeprom_t *mptr, int /*msize*/);
62476bd547bSAdrian Chadd extern int ar9300_eeprom_base_address(struct ath_hal *ah);
62576bd547bSAdrian Chadd extern int ar9300_eeprom_volatile(struct ath_hal *ah);
62676bd547bSAdrian Chadd extern int ar9300_eeprom_low_limit(struct ath_hal *ah);
62776bd547bSAdrian Chadd extern u_int16_t ar9300_compression_checksum(u_int8_t *data, int dsize);
62876bd547bSAdrian Chadd extern int ar9300_compression_header_unpack(u_int8_t *best, int *code, int *reference, int *length, int *major, int *minor);
62976bd547bSAdrian Chadd
63076bd547bSAdrian Chadd extern u_int16_t ar9300_eeprom_struct_size(void);
63176bd547bSAdrian Chadd extern ar9300_eeprom_t *ar9300EepromStructInit(int default_index);
63276bd547bSAdrian Chadd extern ar9300_eeprom_t *ar9300EepromStructGet(void);
63376bd547bSAdrian Chadd extern ar9300_eeprom_t *ar9300_eeprom_struct_default(int default_index);
63476bd547bSAdrian Chadd extern ar9300_eeprom_t *ar9300_eeprom_struct_default_find_by_id(int ver);
63576bd547bSAdrian Chadd extern int ar9300_eeprom_struct_default_many(void);
63676bd547bSAdrian Chadd extern int ar9300EepromUpdateCalPier(int pierIdx, int freq, int chain,
63776bd547bSAdrian Chadd int pwrCorrection, int volt_meas, int temp_meas);
63876bd547bSAdrian Chadd extern int ar9300_power_control_override(struct ath_hal *ah, int frequency, int *correction, int *voltage, int *temperature);
63976bd547bSAdrian Chadd
64076bd547bSAdrian Chadd extern void ar9300EepromDisplayCalData(int for2GHz);
64176bd547bSAdrian Chadd extern void ar9300EepromDisplayAll(void);
64276bd547bSAdrian Chadd extern void ar9300_set_target_power_from_eeprom(struct ath_hal *ah, u_int16_t freq,
64376bd547bSAdrian Chadd u_int8_t *target_power_val_t2);
64476bd547bSAdrian Chadd extern HAL_BOOL ar9300_eeprom_set_power_per_rate_table(struct ath_hal *ah,
64576bd547bSAdrian Chadd ar9300_eeprom_t *p_eep_data,
646e113789bSAdrian Chadd const struct ieee80211_channel *chan,
64776bd547bSAdrian Chadd u_int8_t *p_pwr_array,
64876bd547bSAdrian Chadd u_int16_t cfg_ctl,
64976bd547bSAdrian Chadd u_int16_t antenna_reduction,
65076bd547bSAdrian Chadd u_int16_t twice_max_regulatory_power,
65176bd547bSAdrian Chadd u_int16_t power_limit,
65276bd547bSAdrian Chadd u_int8_t chainmask);
65376bd547bSAdrian Chadd extern int ar9300_transmit_power_reg_write(struct ath_hal *ah, u_int8_t *p_pwr_array);
65476bd547bSAdrian Chadd
65576bd547bSAdrian Chadd extern u_int8_t ar9300_eeprom_get_legacy_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
65676bd547bSAdrian Chadd extern u_int8_t ar9300_eeprom_get_ht20_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
65776bd547bSAdrian Chadd extern u_int8_t ar9300_eeprom_get_ht40_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq, HAL_BOOL is_2ghz);
65876bd547bSAdrian Chadd extern u_int8_t ar9300_eeprom_get_cck_trgt_pwr(struct ath_hal *ah, u_int16_t rate_index, u_int16_t freq);
65976bd547bSAdrian Chadd extern HAL_BOOL ar9300_internal_regulator_apply(struct ath_hal *ah);
66076bd547bSAdrian Chadd extern HAL_BOOL ar9300_drive_strength_apply(struct ath_hal *ah);
66176bd547bSAdrian Chadd extern HAL_BOOL ar9300_attenuation_apply(struct ath_hal *ah, u_int16_t channel);
66276bd547bSAdrian Chadd extern int32_t ar9300_thermometer_get(struct ath_hal *ah);
66376bd547bSAdrian Chadd extern HAL_BOOL ar9300_thermometer_apply(struct ath_hal *ah);
66476bd547bSAdrian Chadd extern HAL_BOOL ar9300_xpa_timing_control_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
66576bd547bSAdrian Chadd extern HAL_BOOL ar9300_x_lNA_bias_strength_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
66676bd547bSAdrian Chadd
66776bd547bSAdrian Chadd extern int32_t ar9300MacAdressGet(u_int8_t *mac);
66876bd547bSAdrian Chadd extern int32_t ar9300CustomerDataGet(u_int8_t *data, int32_t len);
66976bd547bSAdrian Chadd extern int32_t ar9300ReconfigDriveStrengthGet(void);
67076bd547bSAdrian Chadd extern int32_t ar9300EnableTempCompensationGet(void);
67176bd547bSAdrian Chadd extern int32_t ar9300EnableVoltCompensationGet(void);
67276bd547bSAdrian Chadd extern int32_t ar9300FastClockEnableGet(void);
67376bd547bSAdrian Chadd extern int32_t ar9300EnableDoublingGet(void);
67476bd547bSAdrian Chadd
67576bd547bSAdrian Chadd extern u_int16_t *ar9300_regulatory_domain_get(struct ath_hal *ah);
67676bd547bSAdrian Chadd extern int32_t ar9300_eeprom_write_enable_gpio_get(struct ath_hal *ah);
67776bd547bSAdrian Chadd extern int32_t ar9300_wlan_led_gpio_get(struct ath_hal *ah);
67876bd547bSAdrian Chadd extern int32_t ar9300_wlan_disable_gpio_get(struct ath_hal *ah);
67976bd547bSAdrian Chadd extern int32_t ar9300_rx_band_select_gpio_get(struct ath_hal *ah);
68076bd547bSAdrian Chadd extern int32_t ar9300_rx_gain_index_get(struct ath_hal *ah);
68176bd547bSAdrian Chadd extern int32_t ar9300_tx_gain_index_get(struct ath_hal *ah);
68276bd547bSAdrian Chadd extern int32_t ar9300_xpa_bias_level_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
68376bd547bSAdrian Chadd extern HAL_BOOL ar9300_xpa_bias_level_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
68476bd547bSAdrian Chadd extern u_int32_t ar9300_ant_ctrl_common_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
68576bd547bSAdrian Chadd extern u_int32_t ar9300_ant_ctrl_common2_get(struct ath_hal *ah, HAL_BOOL is_2ghz);
68676bd547bSAdrian Chadd extern u_int16_t ar9300_ant_ctrl_chain_get(struct ath_hal *ah, int chain, HAL_BOOL is_2ghz);
68776bd547bSAdrian Chadd extern HAL_BOOL ar9300_ant_ctrl_apply(struct ath_hal *ah, HAL_BOOL is_2ghz);
68876bd547bSAdrian Chadd /* since valid noise floor values are negative, returns 1 on error */
68976bd547bSAdrian Chadd extern int32_t ar9300_noise_floor_cal_or_power_get(
69076bd547bSAdrian Chadd struct ath_hal *ah, int32_t frequency, int32_t ichain, HAL_BOOL use_cal);
69176bd547bSAdrian Chadd #define ar9300NoiseFloorGet(ah, frequency, ichain) \
69276bd547bSAdrian Chadd ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 1/*use_cal*/)
69376bd547bSAdrian Chadd #define ar9300NoiseFloorPowerGet(ah, frequency, ichain) \
69476bd547bSAdrian Chadd ar9300_noise_floor_cal_or_power_get(ah, frequency, ichain, 0/*use_cal*/)
69576bd547bSAdrian Chadd extern void ar9300_eeprom_template_preference(int32_t value);
69676bd547bSAdrian Chadd extern int32_t ar9300_eeprom_template_install(struct ath_hal *ah, int32_t value);
69776bd547bSAdrian Chadd extern void ar9300_calibration_data_set(struct ath_hal *ah, int32_t source);
69876bd547bSAdrian Chadd extern int32_t ar9300_calibration_data_get(struct ath_hal *ah);
69976bd547bSAdrian Chadd extern int32_t ar9300_calibration_data_address_get(struct ath_hal *ah);
70076bd547bSAdrian Chadd extern void ar9300_calibration_data_address_set(struct ath_hal *ah, int32_t source);
70176bd547bSAdrian Chadd extern HAL_BOOL ar9300_calibration_data_read_flash(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
70276bd547bSAdrian Chadd extern HAL_BOOL ar9300_calibration_data_read_eeprom(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
70376bd547bSAdrian Chadd extern HAL_BOOL ar9300_calibration_data_read_otp(struct ath_hal *ah, long address, u_int8_t *buffer, int many, HAL_BOOL is_wifi);
70476bd547bSAdrian Chadd extern HAL_BOOL ar9300_calibration_data_read(struct ath_hal *ah, long address, u_int8_t *buffer, int many);
70576bd547bSAdrian Chadd extern int32_t ar9300_eeprom_size(struct ath_hal *ah);
70676bd547bSAdrian Chadd extern int32_t ar9300_otp_size(struct ath_hal *ah);
70776bd547bSAdrian Chadd extern HAL_BOOL ar9300_calibration_data_read_array(struct ath_hal *ah, int address, u_int8_t *buffer, int many);
70876bd547bSAdrian Chadd
70976bd547bSAdrian Chadd
71076bd547bSAdrian Chadd
71176bd547bSAdrian Chadd #if defined(WIN32) || defined(WIN64)
71276bd547bSAdrian Chadd #pragma pack (pop, ar9300)
71376bd547bSAdrian Chadd #endif
71476bd547bSAdrian Chadd
71576bd547bSAdrian Chadd #endif /* _ATH_AR9300_EEP_H_ */
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