1 // SPDX-License-Identifier: BSD-3-Clause-Clear 2 /* Copyright (c) 2020 The Linux Foundation. All rights reserved. */ 3 4 #include <linux/msi.h> 5 #include <linux/pci.h> 6 #if defined(CONFIG_OF) 7 #include <linux/of.h> 8 #endif 9 #include <linux/of_address.h> 10 #include <linux/ioport.h> 11 #if defined(__FreeBSD__) 12 #include <linux/delay.h> 13 #endif 14 15 #include "core.h" 16 #include "debug.h" 17 #include "mhi.h" 18 #include "pci.h" 19 20 #define MHI_TIMEOUT_DEFAULT_MS 90000 21 22 static struct mhi_channel_config ath11k_mhi_channels_qca6390[] = { 23 { 24 .num = 0, 25 .name = "LOOPBACK", 26 .num_elements = 32, 27 .event_ring = 0, 28 .dir = DMA_TO_DEVICE, 29 .ee_mask = 0x4, 30 .pollcfg = 0, 31 .doorbell = MHI_DB_BRST_DISABLE, 32 .lpm_notify = false, 33 .offload_channel = false, 34 .doorbell_mode_switch = false, 35 .auto_queue = false, 36 }, 37 { 38 .num = 1, 39 .name = "LOOPBACK", 40 .num_elements = 32, 41 .event_ring = 0, 42 .dir = DMA_FROM_DEVICE, 43 .ee_mask = 0x4, 44 .pollcfg = 0, 45 .doorbell = MHI_DB_BRST_DISABLE, 46 .lpm_notify = false, 47 .offload_channel = false, 48 .doorbell_mode_switch = false, 49 .auto_queue = false, 50 }, 51 { 52 .num = 20, 53 .name = "IPCR", 54 .num_elements = 64, 55 .event_ring = 1, 56 .dir = DMA_TO_DEVICE, 57 .ee_mask = 0x4, 58 .pollcfg = 0, 59 .doorbell = MHI_DB_BRST_DISABLE, 60 .lpm_notify = false, 61 .offload_channel = false, 62 .doorbell_mode_switch = false, 63 .auto_queue = false, 64 }, 65 { 66 .num = 21, 67 .name = "IPCR", 68 .num_elements = 64, 69 .event_ring = 1, 70 .dir = DMA_FROM_DEVICE, 71 .ee_mask = 0x4, 72 .pollcfg = 0, 73 .doorbell = MHI_DB_BRST_DISABLE, 74 .lpm_notify = false, 75 .offload_channel = false, 76 .doorbell_mode_switch = false, 77 .auto_queue = true, 78 }, 79 }; 80 81 static struct mhi_event_config ath11k_mhi_events_qca6390[] = { 82 { 83 .num_elements = 32, 84 .irq_moderation_ms = 0, 85 .irq = 1, 86 .mode = MHI_DB_BRST_DISABLE, 87 .data_type = MHI_ER_CTRL, 88 .hardware_event = false, 89 .client_managed = false, 90 .offload_channel = false, 91 }, 92 { 93 .num_elements = 256, 94 .irq_moderation_ms = 1, 95 .irq = 2, 96 .mode = MHI_DB_BRST_DISABLE, 97 .priority = 1, 98 .hardware_event = false, 99 .client_managed = false, 100 .offload_channel = false, 101 }, 102 }; 103 104 static struct mhi_controller_config ath11k_mhi_config_qca6390 = { 105 .max_channels = 128, 106 .timeout_ms = 2000, 107 .use_bounce_buf = false, 108 .buf_len = 0, 109 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390), 110 .ch_cfg = ath11k_mhi_channels_qca6390, 111 .num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390), 112 .event_cfg = ath11k_mhi_events_qca6390, 113 }; 114 115 static struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = { 116 { 117 .num = 0, 118 .name = "LOOPBACK", 119 .num_elements = 32, 120 .event_ring = 1, 121 .dir = DMA_TO_DEVICE, 122 .ee_mask = 0x14, 123 .pollcfg = 0, 124 .doorbell = MHI_DB_BRST_DISABLE, 125 .lpm_notify = false, 126 .offload_channel = false, 127 .doorbell_mode_switch = false, 128 .auto_queue = false, 129 }, 130 { 131 .num = 1, 132 .name = "LOOPBACK", 133 .num_elements = 32, 134 .event_ring = 1, 135 .dir = DMA_FROM_DEVICE, 136 .ee_mask = 0x14, 137 .pollcfg = 0, 138 .doorbell = MHI_DB_BRST_DISABLE, 139 .lpm_notify = false, 140 .offload_channel = false, 141 .doorbell_mode_switch = false, 142 .auto_queue = false, 143 }, 144 { 145 .num = 20, 146 .name = "IPCR", 147 .num_elements = 32, 148 .event_ring = 1, 149 .dir = DMA_TO_DEVICE, 150 .ee_mask = 0x14, 151 .pollcfg = 0, 152 .doorbell = MHI_DB_BRST_DISABLE, 153 .lpm_notify = false, 154 .offload_channel = false, 155 .doorbell_mode_switch = false, 156 .auto_queue = false, 157 }, 158 { 159 .num = 21, 160 .name = "IPCR", 161 .num_elements = 32, 162 .event_ring = 1, 163 .dir = DMA_FROM_DEVICE, 164 .ee_mask = 0x14, 165 .pollcfg = 0, 166 .doorbell = MHI_DB_BRST_DISABLE, 167 .lpm_notify = false, 168 .offload_channel = false, 169 .doorbell_mode_switch = false, 170 .auto_queue = true, 171 }, 172 }; 173 174 static struct mhi_event_config ath11k_mhi_events_qcn9074[] = { 175 { 176 .num_elements = 32, 177 .irq_moderation_ms = 0, 178 .irq = 1, 179 .data_type = MHI_ER_CTRL, 180 .mode = MHI_DB_BRST_DISABLE, 181 .hardware_event = false, 182 .client_managed = false, 183 .offload_channel = false, 184 }, 185 { 186 .num_elements = 256, 187 .irq_moderation_ms = 1, 188 .irq = 2, 189 .mode = MHI_DB_BRST_DISABLE, 190 .priority = 1, 191 .hardware_event = false, 192 .client_managed = false, 193 .offload_channel = false, 194 }, 195 }; 196 197 static struct mhi_controller_config ath11k_mhi_config_qcn9074 = { 198 .max_channels = 30, 199 .timeout_ms = 10000, 200 .use_bounce_buf = false, 201 .buf_len = 0, 202 .num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074), 203 .ch_cfg = ath11k_mhi_channels_qcn9074, 204 .num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074), 205 .event_cfg = ath11k_mhi_events_qcn9074, 206 }; 207 208 void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab) 209 { 210 u32 val; 211 212 val = ath11k_pci_read32(ab, MHISTATUS); 213 214 ath11k_dbg(ab, ATH11K_DBG_PCI, "MHISTATUS 0x%x\n", val); 215 216 /* Observed on QCA6390 that after SOC_GLOBAL_RESET, MHISTATUS 217 * has SYSERR bit set and thus need to set MHICTRL_RESET 218 * to clear SYSERR. 219 */ 220 ath11k_pci_write32(ab, MHICTRL, MHICTRL_RESET_MASK); 221 222 mdelay(10); 223 } 224 225 static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab) 226 { 227 ath11k_pci_write32(ab, PCIE_TXVECDB, 0); 228 } 229 230 static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab) 231 { 232 ath11k_pci_write32(ab, PCIE_TXVECSTATUS, 0); 233 } 234 235 static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab) 236 { 237 ath11k_pci_write32(ab, PCIE_RXVECDB, 0); 238 } 239 240 static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab) 241 { 242 ath11k_pci_write32(ab, PCIE_RXVECSTATUS, 0); 243 } 244 245 void ath11k_mhi_clear_vector(struct ath11k_base *ab) 246 { 247 ath11k_mhi_reset_txvecdb(ab); 248 ath11k_mhi_reset_txvecstatus(ab); 249 ath11k_mhi_reset_rxvecdb(ab); 250 ath11k_mhi_reset_rxvecstatus(ab); 251 } 252 253 static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci) 254 { 255 struct ath11k_base *ab = ab_pci->ab; 256 u32 user_base_data, base_vector; 257 int ret, num_vectors, i; 258 int *irq; 259 unsigned int msi_data; 260 261 ret = ath11k_pci_get_user_msi_assignment(ab_pci, 262 "MHI", &num_vectors, 263 &user_base_data, &base_vector); 264 if (ret) 265 return ret; 266 267 ath11k_dbg(ab, ATH11K_DBG_PCI, "Number of assigned MSI for MHI is %d, base vector is %d\n", 268 num_vectors, base_vector); 269 270 irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL); 271 if (!irq) 272 return -ENOMEM; 273 274 for (i = 0; i < num_vectors; i++) { 275 msi_data = base_vector; 276 277 if (test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 278 msi_data += i; 279 280 irq[i] = ath11k_pci_get_msi_irq(ab->dev, 281 msi_data); 282 } 283 284 ab_pci->mhi_ctrl->irq = irq; 285 ab_pci->mhi_ctrl->nr_irqs = num_vectors; 286 287 return 0; 288 } 289 290 static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl) 291 { 292 return 0; 293 } 294 295 static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl) 296 { 297 } 298 299 static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl, 300 enum mhi_callback cb) 301 { 302 struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev); 303 304 switch (cb) { 305 case MHI_CB_SYS_ERROR: 306 ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n"); 307 break; 308 default: 309 break; 310 } 311 } 312 313 static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl, 314 void __iomem *addr, 315 u32 *out) 316 { 317 *out = readl(addr); 318 319 return 0; 320 } 321 322 static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl, 323 void __iomem *addr, 324 u32 val) 325 { 326 writel(val, addr); 327 } 328 329 static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl) 330 { 331 #if defined(__linux__) 332 struct device_node *np; 333 struct resource res; 334 int ret; 335 336 np = of_find_node_by_type(NULL, "memory"); 337 if (!np) 338 return -ENOENT; 339 340 ret = of_address_to_resource(np, 0, &res); 341 of_node_put(np); 342 if (ret) 343 return ret; 344 345 mhi_ctrl->iova_start = res.start + 0x1000000; 346 mhi_ctrl->iova_stop = res.end; 347 348 return 0; 349 #elif defined(__FreeBSD__) 350 return -ENOENT; 351 #endif 352 } 353 354 int ath11k_mhi_register(struct ath11k_pci *ab_pci) 355 { 356 struct ath11k_base *ab = ab_pci->ab; 357 struct mhi_controller *mhi_ctrl; 358 struct mhi_controller_config *ath11k_mhi_config; 359 int ret; 360 361 mhi_ctrl = mhi_alloc_controller(); 362 if (!mhi_ctrl) 363 return -ENOMEM; 364 365 ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE, 366 ab_pci->amss_path, 367 sizeof(ab_pci->amss_path)); 368 369 ab_pci->mhi_ctrl = mhi_ctrl; 370 mhi_ctrl->cntrl_dev = ab->dev; 371 mhi_ctrl->fw_image = ab_pci->amss_path; 372 mhi_ctrl->regs = ab->mem; 373 mhi_ctrl->reg_len = ab->mem_len; 374 375 ret = ath11k_mhi_get_msi(ab_pci); 376 if (ret) { 377 ath11k_err(ab, "failed to get msi for mhi\n"); 378 mhi_free_controller(mhi_ctrl); 379 return ret; 380 } 381 382 if (!test_bit(ATH11K_PCI_FLAG_MULTI_MSI_VECTORS, &ab_pci->flags)) 383 mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING; 384 385 if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) { 386 ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl); 387 if (ret < 0) 388 return ret; 389 } else { 390 mhi_ctrl->iova_start = 0; 391 mhi_ctrl->iova_stop = 0xFFFFFFFF; 392 } 393 394 mhi_ctrl->sbl_size = SZ_512K; 395 mhi_ctrl->seg_len = SZ_512K; 396 mhi_ctrl->fbc_download = true; 397 mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get; 398 mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put; 399 mhi_ctrl->status_cb = ath11k_mhi_op_status_cb; 400 mhi_ctrl->read_reg = ath11k_mhi_op_read_reg; 401 mhi_ctrl->write_reg = ath11k_mhi_op_write_reg; 402 403 switch (ab->hw_rev) { 404 case ATH11K_HW_QCN9074_HW10: 405 ath11k_mhi_config = &ath11k_mhi_config_qcn9074; 406 break; 407 case ATH11K_HW_QCA6390_HW20: 408 case ATH11K_HW_WCN6855_HW20: 409 case ATH11K_HW_WCN6855_HW21: 410 ath11k_mhi_config = &ath11k_mhi_config_qca6390; 411 break; 412 default: 413 ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n", 414 ab->hw_rev); 415 mhi_free_controller(mhi_ctrl); 416 return -EINVAL; 417 } 418 419 ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config); 420 if (ret) { 421 ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret); 422 mhi_free_controller(mhi_ctrl); 423 return ret; 424 } 425 426 return 0; 427 } 428 429 void ath11k_mhi_unregister(struct ath11k_pci *ab_pci) 430 { 431 struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl; 432 433 mhi_unregister_controller(mhi_ctrl); 434 kfree(mhi_ctrl->irq); 435 mhi_free_controller(mhi_ctrl); 436 } 437 438 static char *ath11k_mhi_state_to_str(enum ath11k_mhi_state mhi_state) 439 { 440 switch (mhi_state) { 441 case ATH11K_MHI_INIT: 442 return "INIT"; 443 case ATH11K_MHI_DEINIT: 444 return "DEINIT"; 445 case ATH11K_MHI_POWER_ON: 446 return "POWER_ON"; 447 case ATH11K_MHI_POWER_OFF: 448 return "POWER_OFF"; 449 case ATH11K_MHI_FORCE_POWER_OFF: 450 return "FORCE_POWER_OFF"; 451 case ATH11K_MHI_SUSPEND: 452 return "SUSPEND"; 453 case ATH11K_MHI_RESUME: 454 return "RESUME"; 455 case ATH11K_MHI_TRIGGER_RDDM: 456 return "TRIGGER_RDDM"; 457 case ATH11K_MHI_RDDM_DONE: 458 return "RDDM_DONE"; 459 default: 460 return "UNKNOWN"; 461 } 462 }; 463 464 static void ath11k_mhi_set_state_bit(struct ath11k_pci *ab_pci, 465 enum ath11k_mhi_state mhi_state) 466 { 467 struct ath11k_base *ab = ab_pci->ab; 468 469 switch (mhi_state) { 470 case ATH11K_MHI_INIT: 471 set_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 472 break; 473 case ATH11K_MHI_DEINIT: 474 clear_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state); 475 break; 476 case ATH11K_MHI_POWER_ON: 477 set_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 478 break; 479 case ATH11K_MHI_POWER_OFF: 480 case ATH11K_MHI_FORCE_POWER_OFF: 481 clear_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state); 482 clear_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 483 clear_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 484 break; 485 case ATH11K_MHI_SUSPEND: 486 set_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 487 break; 488 case ATH11K_MHI_RESUME: 489 clear_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state); 490 break; 491 case ATH11K_MHI_TRIGGER_RDDM: 492 set_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state); 493 break; 494 case ATH11K_MHI_RDDM_DONE: 495 set_bit(ATH11K_MHI_RDDM_DONE, &ab_pci->mhi_state); 496 break; 497 default: 498 ath11k_err(ab, "unhandled mhi state (%d)\n", mhi_state); 499 } 500 } 501 502 static int ath11k_mhi_check_state_bit(struct ath11k_pci *ab_pci, 503 enum ath11k_mhi_state mhi_state) 504 { 505 struct ath11k_base *ab = ab_pci->ab; 506 507 switch (mhi_state) { 508 case ATH11K_MHI_INIT: 509 if (!test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state)) 510 return 0; 511 break; 512 case ATH11K_MHI_DEINIT: 513 case ATH11K_MHI_POWER_ON: 514 if (test_bit(ATH11K_MHI_INIT, &ab_pci->mhi_state) && 515 !test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 516 return 0; 517 break; 518 case ATH11K_MHI_FORCE_POWER_OFF: 519 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state)) 520 return 0; 521 break; 522 case ATH11K_MHI_POWER_OFF: 523 case ATH11K_MHI_SUSPEND: 524 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 525 !test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 526 return 0; 527 break; 528 case ATH11K_MHI_RESUME: 529 if (test_bit(ATH11K_MHI_SUSPEND, &ab_pci->mhi_state)) 530 return 0; 531 break; 532 case ATH11K_MHI_TRIGGER_RDDM: 533 if (test_bit(ATH11K_MHI_POWER_ON, &ab_pci->mhi_state) && 534 !test_bit(ATH11K_MHI_TRIGGER_RDDM, &ab_pci->mhi_state)) 535 return 0; 536 break; 537 case ATH11K_MHI_RDDM_DONE: 538 return 0; 539 default: 540 ath11k_err(ab, "unhandled mhi state: %s(%d)\n", 541 ath11k_mhi_state_to_str(mhi_state), mhi_state); 542 } 543 544 ath11k_err(ab, "failed to set mhi state %s(%d) in current mhi state (0x%lx)\n", 545 ath11k_mhi_state_to_str(mhi_state), mhi_state, 546 ab_pci->mhi_state); 547 548 return -EINVAL; 549 } 550 551 static int ath11k_mhi_set_state(struct ath11k_pci *ab_pci, 552 enum ath11k_mhi_state mhi_state) 553 { 554 struct ath11k_base *ab = ab_pci->ab; 555 int ret; 556 557 ret = ath11k_mhi_check_state_bit(ab_pci, mhi_state); 558 if (ret) 559 goto out; 560 561 ath11k_dbg(ab, ATH11K_DBG_PCI, "setting mhi state: %s(%d)\n", 562 ath11k_mhi_state_to_str(mhi_state), mhi_state); 563 564 switch (mhi_state) { 565 case ATH11K_MHI_INIT: 566 ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl); 567 break; 568 case ATH11K_MHI_DEINIT: 569 mhi_unprepare_after_power_down(ab_pci->mhi_ctrl); 570 ret = 0; 571 break; 572 case ATH11K_MHI_POWER_ON: 573 ret = mhi_async_power_up(ab_pci->mhi_ctrl); 574 break; 575 case ATH11K_MHI_POWER_OFF: 576 mhi_power_down(ab_pci->mhi_ctrl, true); 577 ret = 0; 578 break; 579 case ATH11K_MHI_FORCE_POWER_OFF: 580 mhi_power_down(ab_pci->mhi_ctrl, false); 581 ret = 0; 582 break; 583 case ATH11K_MHI_SUSPEND: 584 ret = mhi_pm_suspend(ab_pci->mhi_ctrl); 585 break; 586 case ATH11K_MHI_RESUME: 587 /* Do force MHI resume as some devices like QCA6390, WCN6855 588 * are not in M3 state but they are functional. So just ignore 589 * the MHI state while resuming. 590 */ 591 ret = mhi_pm_resume_force(ab_pci->mhi_ctrl); 592 break; 593 case ATH11K_MHI_TRIGGER_RDDM: 594 ret = mhi_force_rddm_mode(ab_pci->mhi_ctrl); 595 break; 596 case ATH11K_MHI_RDDM_DONE: 597 break; 598 default: 599 ath11k_err(ab, "unhandled MHI state (%d)\n", mhi_state); 600 ret = -EINVAL; 601 } 602 603 if (ret) 604 goto out; 605 606 ath11k_mhi_set_state_bit(ab_pci, mhi_state); 607 608 return 0; 609 610 out: 611 ath11k_err(ab, "failed to set mhi state: %s(%d)\n", 612 ath11k_mhi_state_to_str(mhi_state), mhi_state); 613 return ret; 614 } 615 616 int ath11k_mhi_start(struct ath11k_pci *ab_pci) 617 { 618 int ret; 619 620 ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS; 621 622 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_INIT); 623 if (ret) 624 goto out; 625 626 ret = ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_ON); 627 if (ret) 628 goto out; 629 630 return 0; 631 632 out: 633 return ret; 634 } 635 636 void ath11k_mhi_stop(struct ath11k_pci *ab_pci) 637 { 638 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_POWER_OFF); 639 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_DEINIT); 640 } 641 642 void ath11k_mhi_suspend(struct ath11k_pci *ab_pci) 643 { 644 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_SUSPEND); 645 } 646 647 void ath11k_mhi_resume(struct ath11k_pci *ab_pci) 648 { 649 ath11k_mhi_set_state(ab_pci, ATH11K_MHI_RESUME); 650 } 651