1bfcc09ddSBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2bfcc09ddSBjoern A. Zeeb /* 3d9836fb4SBjoern A. Zeeb * Copyright (C) 2005-2014, 2018-2022 Intel Corporation 4bfcc09ddSBjoern A. Zeeb * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5bfcc09ddSBjoern A. Zeeb * Copyright (C) 2016-2017 Intel Deutschland GmbH 6bfcc09ddSBjoern A. Zeeb */ 7bfcc09ddSBjoern A. Zeeb #ifndef __iwl_fw_api_debug_h__ 8bfcc09ddSBjoern A. Zeeb #define __iwl_fw_api_debug_h__ 9bfcc09ddSBjoern A. Zeeb 10bfcc09ddSBjoern A. Zeeb /** 11bfcc09ddSBjoern A. Zeeb * enum iwl_debug_cmds - debug commands 12bfcc09ddSBjoern A. Zeeb */ 13bfcc09ddSBjoern A. Zeeb enum iwl_debug_cmds { 14bfcc09ddSBjoern A. Zeeb /** 15bfcc09ddSBjoern A. Zeeb * @LMAC_RD_WR: 16bfcc09ddSBjoern A. Zeeb * LMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 17bfcc09ddSBjoern A. Zeeb * &struct iwl_dbg_mem_access_rsp 18bfcc09ddSBjoern A. Zeeb */ 19bfcc09ddSBjoern A. Zeeb LMAC_RD_WR = 0x0, 20bfcc09ddSBjoern A. Zeeb /** 21bfcc09ddSBjoern A. Zeeb * @UMAC_RD_WR: 22bfcc09ddSBjoern A. Zeeb * UMAC memory read/write, using &struct iwl_dbg_mem_access_cmd and 23bfcc09ddSBjoern A. Zeeb * &struct iwl_dbg_mem_access_rsp 24bfcc09ddSBjoern A. Zeeb */ 25bfcc09ddSBjoern A. Zeeb UMAC_RD_WR = 0x1, 26bfcc09ddSBjoern A. Zeeb /** 27bfcc09ddSBjoern A. Zeeb * @HOST_EVENT_CFG: 28bfcc09ddSBjoern A. Zeeb * updates the enabled event severities 29bfcc09ddSBjoern A. Zeeb * &struct iwl_dbg_host_event_cfg_cmd 30bfcc09ddSBjoern A. Zeeb */ 31bfcc09ddSBjoern A. Zeeb HOST_EVENT_CFG = 0x3, 32bfcc09ddSBjoern A. Zeeb /** 33bfcc09ddSBjoern A. Zeeb * @DBGC_SUSPEND_RESUME: 34bfcc09ddSBjoern A. Zeeb * DBGC suspend/resume commad. Uses a single dword as data: 35bfcc09ddSBjoern A. Zeeb * 0 - resume DBGC recording 36bfcc09ddSBjoern A. Zeeb * 1 - suspend DBGC recording 37bfcc09ddSBjoern A. Zeeb */ 38bfcc09ddSBjoern A. Zeeb DBGC_SUSPEND_RESUME = 0x7, 39bfcc09ddSBjoern A. Zeeb /** 40bfcc09ddSBjoern A. Zeeb * @BUFFER_ALLOCATION: 41bfcc09ddSBjoern A. Zeeb * passes DRAM buffers to a DBGC 42bfcc09ddSBjoern A. Zeeb * &struct iwl_buf_alloc_cmd 43bfcc09ddSBjoern A. Zeeb */ 44bfcc09ddSBjoern A. Zeeb BUFFER_ALLOCATION = 0x8, 45bfcc09ddSBjoern A. Zeeb /** 469af1bba4SBjoern A. Zeeb * @GET_TAS_STATUS: 479af1bba4SBjoern A. Zeeb * sends command to fw to get TAS status 489af1bba4SBjoern A. Zeeb * the response is &struct iwl_mvm_tas_status_resp 499af1bba4SBjoern A. Zeeb */ 509af1bba4SBjoern A. Zeeb GET_TAS_STATUS = 0xA, 519af1bba4SBjoern A. Zeeb /** 52d9836fb4SBjoern A. Zeeb * @FW_DUMP_COMPLETE_CMD: 53d9836fb4SBjoern A. Zeeb * sends command to fw once dump collection completed 54d9836fb4SBjoern A. Zeeb * &struct iwl_dbg_dump_complete_cmd 55d9836fb4SBjoern A. Zeeb */ 56d9836fb4SBjoern A. Zeeb FW_DUMP_COMPLETE_CMD = 0xB, 57d9836fb4SBjoern A. Zeeb /** 58bfcc09ddSBjoern A. Zeeb * @MFU_ASSERT_DUMP_NTF: 59bfcc09ddSBjoern A. Zeeb * &struct iwl_mfu_assert_dump_notif 60bfcc09ddSBjoern A. Zeeb */ 61bfcc09ddSBjoern A. Zeeb MFU_ASSERT_DUMP_NTF = 0xFE, 62bfcc09ddSBjoern A. Zeeb }; 63bfcc09ddSBjoern A. Zeeb 64bfcc09ddSBjoern A. Zeeb /* Error response/notification */ 65bfcc09ddSBjoern A. Zeeb enum { 66bfcc09ddSBjoern A. Zeeb FW_ERR_UNKNOWN_CMD = 0x0, 67bfcc09ddSBjoern A. Zeeb FW_ERR_INVALID_CMD_PARAM = 0x1, 68bfcc09ddSBjoern A. Zeeb FW_ERR_SERVICE = 0x2, 69bfcc09ddSBjoern A. Zeeb FW_ERR_ARC_MEMORY = 0x3, 70bfcc09ddSBjoern A. Zeeb FW_ERR_ARC_CODE = 0x4, 71bfcc09ddSBjoern A. Zeeb FW_ERR_WATCH_DOG = 0x5, 72bfcc09ddSBjoern A. Zeeb FW_ERR_WEP_GRP_KEY_INDX = 0x10, 73bfcc09ddSBjoern A. Zeeb FW_ERR_WEP_KEY_SIZE = 0x11, 74bfcc09ddSBjoern A. Zeeb FW_ERR_OBSOLETE_FUNC = 0x12, 75bfcc09ddSBjoern A. Zeeb FW_ERR_UNEXPECTED = 0xFE, 76bfcc09ddSBjoern A. Zeeb FW_ERR_FATAL = 0xFF 77bfcc09ddSBjoern A. Zeeb }; 78bfcc09ddSBjoern A. Zeeb 79bfcc09ddSBjoern A. Zeeb /** enum iwl_dbg_suspend_resume_cmds - dbgc suspend resume operations 80bfcc09ddSBjoern A. Zeeb * dbgc suspend resume command operations 81bfcc09ddSBjoern A. Zeeb * @DBGC_RESUME_CMD: resume dbgc recording 82bfcc09ddSBjoern A. Zeeb * @DBGC_SUSPEND_CMD: stop dbgc recording 83bfcc09ddSBjoern A. Zeeb */ 84bfcc09ddSBjoern A. Zeeb enum iwl_dbg_suspend_resume_cmds { 85bfcc09ddSBjoern A. Zeeb DBGC_RESUME_CMD, 86bfcc09ddSBjoern A. Zeeb DBGC_SUSPEND_CMD, 87bfcc09ddSBjoern A. Zeeb }; 88bfcc09ddSBjoern A. Zeeb 89bfcc09ddSBjoern A. Zeeb /** 90bfcc09ddSBjoern A. Zeeb * struct iwl_error_resp - FW error indication 91bfcc09ddSBjoern A. Zeeb * ( REPLY_ERROR = 0x2 ) 92bfcc09ddSBjoern A. Zeeb * @error_type: one of FW_ERR_* 93bfcc09ddSBjoern A. Zeeb * @cmd_id: the command ID for which the error occurred 94bfcc09ddSBjoern A. Zeeb * @reserved1: reserved 95bfcc09ddSBjoern A. Zeeb * @bad_cmd_seq_num: sequence number of the erroneous command 96bfcc09ddSBjoern A. Zeeb * @error_service: which service created the error, applicable only if 97bfcc09ddSBjoern A. Zeeb * error_type = 2, otherwise 0 98bfcc09ddSBjoern A. Zeeb * @timestamp: TSF in usecs. 99bfcc09ddSBjoern A. Zeeb */ 100bfcc09ddSBjoern A. Zeeb struct iwl_error_resp { 101bfcc09ddSBjoern A. Zeeb __le32 error_type; 102bfcc09ddSBjoern A. Zeeb u8 cmd_id; 103bfcc09ddSBjoern A. Zeeb u8 reserved1; 104bfcc09ddSBjoern A. Zeeb __le16 bad_cmd_seq_num; 105bfcc09ddSBjoern A. Zeeb __le32 error_service; 106bfcc09ddSBjoern A. Zeeb __le64 timestamp; 107bfcc09ddSBjoern A. Zeeb } __packed; 108bfcc09ddSBjoern A. Zeeb 109bfcc09ddSBjoern A. Zeeb #define TX_FIFO_MAX_NUM_9000 8 110bfcc09ddSBjoern A. Zeeb #define TX_FIFO_MAX_NUM 15 111bfcc09ddSBjoern A. Zeeb #define RX_FIFO_MAX_NUM 2 112bfcc09ddSBjoern A. Zeeb #define TX_FIFO_INTERNAL_MAX_NUM 6 113bfcc09ddSBjoern A. Zeeb 114bfcc09ddSBjoern A. Zeeb /** 115bfcc09ddSBjoern A. Zeeb * struct iwl_shared_mem_cfg_v2 - Shared memory configuration information 116bfcc09ddSBjoern A. Zeeb * 117bfcc09ddSBjoern A. Zeeb * @shared_mem_addr: shared memory addr (pre 8000 HW set to 0x0 as MARBH is not 118bfcc09ddSBjoern A. Zeeb * accessible) 119bfcc09ddSBjoern A. Zeeb * @shared_mem_size: shared memory size 120bfcc09ddSBjoern A. Zeeb * @sample_buff_addr: internal sample (mon/adc) buff addr (pre 8000 HW set to 121bfcc09ddSBjoern A. Zeeb * 0x0 as accessible only via DBGM RDAT) 122bfcc09ddSBjoern A. Zeeb * @sample_buff_size: internal sample buff size 123bfcc09ddSBjoern A. Zeeb * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB), (pre 124bfcc09ddSBjoern A. Zeeb * 8000 HW set to 0x0 as not accessible) 125bfcc09ddSBjoern A. Zeeb * @txfifo_size: size of TXF0 ... TXF7 126bfcc09ddSBjoern A. Zeeb * @rxfifo_size: RXF1, RXF2 sizes. If there is no RXF2, it'll have a value of 0 127bfcc09ddSBjoern A. Zeeb * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 128bfcc09ddSBjoern A. Zeeb * when paging is not supported this should be 0 129bfcc09ddSBjoern A. Zeeb * @page_buff_size: size of %page_buff_addr 130bfcc09ddSBjoern A. Zeeb * @rxfifo_addr: Start address of rxFifo 131bfcc09ddSBjoern A. Zeeb * @internal_txfifo_addr: start address of internalFifo 132bfcc09ddSBjoern A. Zeeb * @internal_txfifo_size: internal fifos' size 133bfcc09ddSBjoern A. Zeeb * 134bfcc09ddSBjoern A. Zeeb * NOTE: on firmware that don't have IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG 135bfcc09ddSBjoern A. Zeeb * set, the last 3 members don't exist. 136bfcc09ddSBjoern A. Zeeb */ 137bfcc09ddSBjoern A. Zeeb struct iwl_shared_mem_cfg_v2 { 138bfcc09ddSBjoern A. Zeeb __le32 shared_mem_addr; 139bfcc09ddSBjoern A. Zeeb __le32 shared_mem_size; 140bfcc09ddSBjoern A. Zeeb __le32 sample_buff_addr; 141bfcc09ddSBjoern A. Zeeb __le32 sample_buff_size; 142bfcc09ddSBjoern A. Zeeb __le32 txfifo_addr; 143bfcc09ddSBjoern A. Zeeb __le32 txfifo_size[TX_FIFO_MAX_NUM_9000]; 144bfcc09ddSBjoern A. Zeeb __le32 rxfifo_size[RX_FIFO_MAX_NUM]; 145bfcc09ddSBjoern A. Zeeb __le32 page_buff_addr; 146bfcc09ddSBjoern A. Zeeb __le32 page_buff_size; 147bfcc09ddSBjoern A. Zeeb __le32 rxfifo_addr; 148bfcc09ddSBjoern A. Zeeb __le32 internal_txfifo_addr; 149bfcc09ddSBjoern A. Zeeb __le32 internal_txfifo_size[TX_FIFO_INTERNAL_MAX_NUM]; 150bfcc09ddSBjoern A. Zeeb } __packed; /* SHARED_MEM_ALLOC_API_S_VER_2 */ 151bfcc09ddSBjoern A. Zeeb 152bfcc09ddSBjoern A. Zeeb /** 153bfcc09ddSBjoern A. Zeeb * struct iwl_shared_mem_lmac_cfg - LMAC shared memory configuration 154bfcc09ddSBjoern A. Zeeb * 155bfcc09ddSBjoern A. Zeeb * @txfifo_addr: start addr of TXF0 (excluding the context table 0.5KB) 156bfcc09ddSBjoern A. Zeeb * @txfifo_size: size of TX FIFOs 157bfcc09ddSBjoern A. Zeeb * @rxfifo1_addr: RXF1 addr 158bfcc09ddSBjoern A. Zeeb * @rxfifo1_size: RXF1 size 159bfcc09ddSBjoern A. Zeeb */ 160bfcc09ddSBjoern A. Zeeb struct iwl_shared_mem_lmac_cfg { 161bfcc09ddSBjoern A. Zeeb __le32 txfifo_addr; 162bfcc09ddSBjoern A. Zeeb __le32 txfifo_size[TX_FIFO_MAX_NUM]; 163bfcc09ddSBjoern A. Zeeb __le32 rxfifo1_addr; 164bfcc09ddSBjoern A. Zeeb __le32 rxfifo1_size; 165bfcc09ddSBjoern A. Zeeb 166bfcc09ddSBjoern A. Zeeb } __packed; /* SHARED_MEM_ALLOC_LMAC_API_S_VER_1 */ 167bfcc09ddSBjoern A. Zeeb 168bfcc09ddSBjoern A. Zeeb /** 169bfcc09ddSBjoern A. Zeeb * struct iwl_shared_mem_cfg - Shared memory configuration information 170bfcc09ddSBjoern A. Zeeb * 171bfcc09ddSBjoern A. Zeeb * @shared_mem_addr: shared memory address 172bfcc09ddSBjoern A. Zeeb * @shared_mem_size: shared memory size 173bfcc09ddSBjoern A. Zeeb * @sample_buff_addr: internal sample (mon/adc) buff addr 174bfcc09ddSBjoern A. Zeeb * @sample_buff_size: internal sample buff size 175bfcc09ddSBjoern A. Zeeb * @rxfifo2_addr: start addr of RXF2 176bfcc09ddSBjoern A. Zeeb * @rxfifo2_size: size of RXF2 177bfcc09ddSBjoern A. Zeeb * @page_buff_addr: used by UMAC and performance debug (page miss analysis), 178bfcc09ddSBjoern A. Zeeb * when paging is not supported this should be 0 179bfcc09ddSBjoern A. Zeeb * @page_buff_size: size of %page_buff_addr 180bfcc09ddSBjoern A. Zeeb * @lmac_num: number of LMACs (1 or 2) 181bfcc09ddSBjoern A. Zeeb * @lmac_smem: per - LMAC smem data 182bfcc09ddSBjoern A. Zeeb * @rxfifo2_control_addr: start addr of RXF2C 183bfcc09ddSBjoern A. Zeeb * @rxfifo2_control_size: size of RXF2C 184bfcc09ddSBjoern A. Zeeb */ 185bfcc09ddSBjoern A. Zeeb struct iwl_shared_mem_cfg { 186bfcc09ddSBjoern A. Zeeb __le32 shared_mem_addr; 187bfcc09ddSBjoern A. Zeeb __le32 shared_mem_size; 188bfcc09ddSBjoern A. Zeeb __le32 sample_buff_addr; 189bfcc09ddSBjoern A. Zeeb __le32 sample_buff_size; 190bfcc09ddSBjoern A. Zeeb __le32 rxfifo2_addr; 191bfcc09ddSBjoern A. Zeeb __le32 rxfifo2_size; 192bfcc09ddSBjoern A. Zeeb __le32 page_buff_addr; 193bfcc09ddSBjoern A. Zeeb __le32 page_buff_size; 194bfcc09ddSBjoern A. Zeeb __le32 lmac_num; 195bfcc09ddSBjoern A. Zeeb struct iwl_shared_mem_lmac_cfg lmac_smem[3]; 196bfcc09ddSBjoern A. Zeeb __le32 rxfifo2_control_addr; 197bfcc09ddSBjoern A. Zeeb __le32 rxfifo2_control_size; 198bfcc09ddSBjoern A. Zeeb } __packed; /* SHARED_MEM_ALLOC_API_S_VER_4 */ 199bfcc09ddSBjoern A. Zeeb 200bfcc09ddSBjoern A. Zeeb /** 201bfcc09ddSBjoern A. Zeeb * struct iwl_mfuart_load_notif_v1 - mfuart image version & status 202bfcc09ddSBjoern A. Zeeb * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 203bfcc09ddSBjoern A. Zeeb * @installed_ver: installed image version 204bfcc09ddSBjoern A. Zeeb * @external_ver: external image version 205bfcc09ddSBjoern A. Zeeb * @status: MFUART loading status 206bfcc09ddSBjoern A. Zeeb * @duration: MFUART loading time 207bfcc09ddSBjoern A. Zeeb */ 208bfcc09ddSBjoern A. Zeeb struct iwl_mfuart_load_notif_v1 { 209bfcc09ddSBjoern A. Zeeb __le32 installed_ver; 210bfcc09ddSBjoern A. Zeeb __le32 external_ver; 211bfcc09ddSBjoern A. Zeeb __le32 status; 212bfcc09ddSBjoern A. Zeeb __le32 duration; 213bfcc09ddSBjoern A. Zeeb } __packed; /* MFU_LOADER_NTFY_API_S_VER_1 */ 214bfcc09ddSBjoern A. Zeeb 215bfcc09ddSBjoern A. Zeeb /** 216bfcc09ddSBjoern A. Zeeb * struct iwl_mfuart_load_notif - mfuart image version & status 217bfcc09ddSBjoern A. Zeeb * ( MFUART_LOAD_NOTIFICATION = 0xb1 ) 218bfcc09ddSBjoern A. Zeeb * @installed_ver: installed image version 219bfcc09ddSBjoern A. Zeeb * @external_ver: external image version 220bfcc09ddSBjoern A. Zeeb * @status: MFUART loading status 221bfcc09ddSBjoern A. Zeeb * @duration: MFUART loading time 222bfcc09ddSBjoern A. Zeeb * @image_size: MFUART image size in bytes 223bfcc09ddSBjoern A. Zeeb */ 224bfcc09ddSBjoern A. Zeeb struct iwl_mfuart_load_notif { 225bfcc09ddSBjoern A. Zeeb __le32 installed_ver; 226bfcc09ddSBjoern A. Zeeb __le32 external_ver; 227bfcc09ddSBjoern A. Zeeb __le32 status; 228bfcc09ddSBjoern A. Zeeb __le32 duration; 229bfcc09ddSBjoern A. Zeeb /* image size valid only in v2 of the command */ 230bfcc09ddSBjoern A. Zeeb __le32 image_size; 231bfcc09ddSBjoern A. Zeeb } __packed; /* MFU_LOADER_NTFY_API_S_VER_2 */ 232bfcc09ddSBjoern A. Zeeb 233bfcc09ddSBjoern A. Zeeb /** 234bfcc09ddSBjoern A. Zeeb * struct iwl_mfu_assert_dump_notif - mfuart dump logs 235bfcc09ddSBjoern A. Zeeb * ( MFU_ASSERT_DUMP_NTF = 0xfe ) 236bfcc09ddSBjoern A. Zeeb * @assert_id: mfuart assert id that cause the notif 237bfcc09ddSBjoern A. Zeeb * @curr_reset_num: number of asserts since uptime 238bfcc09ddSBjoern A. Zeeb * @index_num: current chunk id 239bfcc09ddSBjoern A. Zeeb * @parts_num: total number of chunks 240bfcc09ddSBjoern A. Zeeb * @data_size: number of data bytes sent 241bfcc09ddSBjoern A. Zeeb * @data: data buffer 242bfcc09ddSBjoern A. Zeeb */ 243bfcc09ddSBjoern A. Zeeb struct iwl_mfu_assert_dump_notif { 244bfcc09ddSBjoern A. Zeeb __le32 assert_id; 245bfcc09ddSBjoern A. Zeeb __le32 curr_reset_num; 246bfcc09ddSBjoern A. Zeeb __le16 index_num; 247bfcc09ddSBjoern A. Zeeb __le16 parts_num; 248bfcc09ddSBjoern A. Zeeb __le32 data_size; 2499af1bba4SBjoern A. Zeeb __le32 data[]; 250bfcc09ddSBjoern A. Zeeb } __packed; /* MFU_DUMP_ASSERT_API_S_VER_1 */ 251bfcc09ddSBjoern A. Zeeb 252bfcc09ddSBjoern A. Zeeb /** 253bfcc09ddSBjoern A. Zeeb * enum iwl_mvm_marker_id - marker ids 254bfcc09ddSBjoern A. Zeeb * 255bfcc09ddSBjoern A. Zeeb * The ids for different type of markers to insert into the usniffer logs 256bfcc09ddSBjoern A. Zeeb * 257bfcc09ddSBjoern A. Zeeb * @MARKER_ID_TX_FRAME_LATENCY: TX latency marker 258bfcc09ddSBjoern A. Zeeb * @MARKER_ID_SYNC_CLOCK: sync FW time and systime 259bfcc09ddSBjoern A. Zeeb */ 260bfcc09ddSBjoern A. Zeeb enum iwl_mvm_marker_id { 261bfcc09ddSBjoern A. Zeeb MARKER_ID_TX_FRAME_LATENCY = 1, 262bfcc09ddSBjoern A. Zeeb MARKER_ID_SYNC_CLOCK = 2, 263bfcc09ddSBjoern A. Zeeb }; /* MARKER_ID_API_E_VER_2 */ 264bfcc09ddSBjoern A. Zeeb 265bfcc09ddSBjoern A. Zeeb /** 266bfcc09ddSBjoern A. Zeeb * struct iwl_mvm_marker - mark info into the usniffer logs 267bfcc09ddSBjoern A. Zeeb * 268bfcc09ddSBjoern A. Zeeb * (MARKER_CMD = 0xcb) 269bfcc09ddSBjoern A. Zeeb * 270bfcc09ddSBjoern A. Zeeb * Mark the UTC time stamp into the usniffer logs together with additional 271bfcc09ddSBjoern A. Zeeb * metadata, so the usniffer output can be parsed. 272bfcc09ddSBjoern A. Zeeb * In the command response the ucode will return the GP2 time. 273bfcc09ddSBjoern A. Zeeb * 274bfcc09ddSBjoern A. Zeeb * @dw_len: The amount of dwords following this byte including this byte. 275bfcc09ddSBjoern A. Zeeb * @marker_id: A unique marker id (iwl_mvm_marker_id). 276bfcc09ddSBjoern A. Zeeb * @reserved: reserved. 277bfcc09ddSBjoern A. Zeeb * @timestamp: in milliseconds since 1970-01-01 00:00:00 UTC 278bfcc09ddSBjoern A. Zeeb * @metadata: additional meta data that will be written to the unsiffer log 279bfcc09ddSBjoern A. Zeeb */ 280bfcc09ddSBjoern A. Zeeb struct iwl_mvm_marker { 281bfcc09ddSBjoern A. Zeeb u8 dw_len; 282bfcc09ddSBjoern A. Zeeb u8 marker_id; 283bfcc09ddSBjoern A. Zeeb __le16 reserved; 284bfcc09ddSBjoern A. Zeeb __le64 timestamp; 2859af1bba4SBjoern A. Zeeb __le32 metadata[]; 286bfcc09ddSBjoern A. Zeeb } __packed; /* MARKER_API_S_VER_1 */ 287bfcc09ddSBjoern A. Zeeb 288bfcc09ddSBjoern A. Zeeb /** 289bfcc09ddSBjoern A. Zeeb * struct iwl_mvm_marker_rsp - Response to marker cmd 290bfcc09ddSBjoern A. Zeeb * 291bfcc09ddSBjoern A. Zeeb * @gp2: The gp2 clock value in the FW 292bfcc09ddSBjoern A. Zeeb */ 293bfcc09ddSBjoern A. Zeeb struct iwl_mvm_marker_rsp { 294bfcc09ddSBjoern A. Zeeb __le32 gp2; 295bfcc09ddSBjoern A. Zeeb } __packed; 296bfcc09ddSBjoern A. Zeeb 297bfcc09ddSBjoern A. Zeeb /* Operation types for the debug mem access */ 298bfcc09ddSBjoern A. Zeeb enum { 299bfcc09ddSBjoern A. Zeeb DEBUG_MEM_OP_READ = 0, 300bfcc09ddSBjoern A. Zeeb DEBUG_MEM_OP_WRITE = 1, 301bfcc09ddSBjoern A. Zeeb DEBUG_MEM_OP_WRITE_BYTES = 2, 302bfcc09ddSBjoern A. Zeeb }; 303bfcc09ddSBjoern A. Zeeb 304bfcc09ddSBjoern A. Zeeb #define DEBUG_MEM_MAX_SIZE_DWORDS 32 305bfcc09ddSBjoern A. Zeeb 306bfcc09ddSBjoern A. Zeeb /** 307bfcc09ddSBjoern A. Zeeb * struct iwl_dbg_mem_access_cmd - Request the device to read/write memory 308bfcc09ddSBjoern A. Zeeb * @op: DEBUG_MEM_OP_* 309bfcc09ddSBjoern A. Zeeb * @addr: address to read/write from/to 310bfcc09ddSBjoern A. Zeeb * @len: in dwords, to read/write 311bfcc09ddSBjoern A. Zeeb * @data: for write opeations, contains the source buffer 312bfcc09ddSBjoern A. Zeeb */ 313bfcc09ddSBjoern A. Zeeb struct iwl_dbg_mem_access_cmd { 314bfcc09ddSBjoern A. Zeeb __le32 op; 315bfcc09ddSBjoern A. Zeeb __le32 addr; 316bfcc09ddSBjoern A. Zeeb __le32 len; 317bfcc09ddSBjoern A. Zeeb __le32 data[]; 318bfcc09ddSBjoern A. Zeeb } __packed; /* DEBUG_(U|L)MAC_RD_WR_CMD_API_S_VER_1 */ 319bfcc09ddSBjoern A. Zeeb 320bfcc09ddSBjoern A. Zeeb /* Status responses for the debug mem access */ 321bfcc09ddSBjoern A. Zeeb enum { 322bfcc09ddSBjoern A. Zeeb DEBUG_MEM_STATUS_SUCCESS = 0x0, 323bfcc09ddSBjoern A. Zeeb DEBUG_MEM_STATUS_FAILED = 0x1, 324bfcc09ddSBjoern A. Zeeb DEBUG_MEM_STATUS_LOCKED = 0x2, 325bfcc09ddSBjoern A. Zeeb DEBUG_MEM_STATUS_HIDDEN = 0x3, 326bfcc09ddSBjoern A. Zeeb DEBUG_MEM_STATUS_LENGTH = 0x4, 327bfcc09ddSBjoern A. Zeeb }; 328bfcc09ddSBjoern A. Zeeb 329bfcc09ddSBjoern A. Zeeb /** 330bfcc09ddSBjoern A. Zeeb * struct iwl_dbg_mem_access_rsp - Response to debug mem commands 331bfcc09ddSBjoern A. Zeeb * @status: DEBUG_MEM_STATUS_* 332bfcc09ddSBjoern A. Zeeb * @len: read dwords (0 for write operations) 333bfcc09ddSBjoern A. Zeeb * @data: contains the read DWs 334bfcc09ddSBjoern A. Zeeb */ 335bfcc09ddSBjoern A. Zeeb struct iwl_dbg_mem_access_rsp { 336bfcc09ddSBjoern A. Zeeb __le32 status; 337bfcc09ddSBjoern A. Zeeb __le32 len; 338bfcc09ddSBjoern A. Zeeb __le32 data[]; 339bfcc09ddSBjoern A. Zeeb } __packed; /* DEBUG_(U|L)MAC_RD_WR_RSP_API_S_VER_1 */ 340bfcc09ddSBjoern A. Zeeb 341bfcc09ddSBjoern A. Zeeb /** 342bfcc09ddSBjoern A. Zeeb * struct iwl_dbg_suspend_resume_cmd - dbgc suspend resume command 343bfcc09ddSBjoern A. Zeeb * @operation: suspend or resume operation, uses 344bfcc09ddSBjoern A. Zeeb * &enum iwl_dbg_suspend_resume_cmds 345bfcc09ddSBjoern A. Zeeb */ 346bfcc09ddSBjoern A. Zeeb struct iwl_dbg_suspend_resume_cmd { 347bfcc09ddSBjoern A. Zeeb __le32 operation; 348bfcc09ddSBjoern A. Zeeb } __packed; 349bfcc09ddSBjoern A. Zeeb 350bfcc09ddSBjoern A. Zeeb #define BUF_ALLOC_MAX_NUM_FRAGS 16 351bfcc09ddSBjoern A. Zeeb 352bfcc09ddSBjoern A. Zeeb /** 353bfcc09ddSBjoern A. Zeeb * struct iwl_buf_alloc_frag - a DBGC fragment 354bfcc09ddSBjoern A. Zeeb * @addr: base address of the fragment 355bfcc09ddSBjoern A. Zeeb * @size: size of the fragment 356bfcc09ddSBjoern A. Zeeb */ 357bfcc09ddSBjoern A. Zeeb struct iwl_buf_alloc_frag { 358bfcc09ddSBjoern A. Zeeb __le64 addr; 359bfcc09ddSBjoern A. Zeeb __le32 size; 360bfcc09ddSBjoern A. Zeeb } __packed; /* FRAGMENT_STRUCTURE_API_S_VER_1 */ 361bfcc09ddSBjoern A. Zeeb 362bfcc09ddSBjoern A. Zeeb /** 363bfcc09ddSBjoern A. Zeeb * struct iwl_buf_alloc_cmd - buffer allocation command 364bfcc09ddSBjoern A. Zeeb * @alloc_id: &enum iwl_fw_ini_allocation_id 365bfcc09ddSBjoern A. Zeeb * @buf_location: &enum iwl_fw_ini_buffer_location 366bfcc09ddSBjoern A. Zeeb * @num_frags: number of fragments 367bfcc09ddSBjoern A. Zeeb * @frags: fragments array 368bfcc09ddSBjoern A. Zeeb */ 369bfcc09ddSBjoern A. Zeeb struct iwl_buf_alloc_cmd { 370bfcc09ddSBjoern A. Zeeb __le32 alloc_id; 371bfcc09ddSBjoern A. Zeeb __le32 buf_location; 372bfcc09ddSBjoern A. Zeeb __le32 num_frags; 373bfcc09ddSBjoern A. Zeeb struct iwl_buf_alloc_frag frags[BUF_ALLOC_MAX_NUM_FRAGS]; 374bfcc09ddSBjoern A. Zeeb } __packed; /* BUFFER_ALLOCATION_CMD_API_S_VER_2 */ 375bfcc09ddSBjoern A. Zeeb 376bfcc09ddSBjoern A. Zeeb #define DRAM_INFO_FIRST_MAGIC_WORD 0x76543210 377bfcc09ddSBjoern A. Zeeb #define DRAM_INFO_SECOND_MAGIC_WORD 0x89ABCDEF 378bfcc09ddSBjoern A. Zeeb 379bfcc09ddSBjoern A. Zeeb /** 380bfcc09ddSBjoern A. Zeeb * struct iwL_dram_info - DRAM fragments allocation struct 381bfcc09ddSBjoern A. Zeeb * 382bfcc09ddSBjoern A. Zeeb * Driver will fill in the first 1K(+) of the pointed DRAM fragment 383bfcc09ddSBjoern A. Zeeb * 384bfcc09ddSBjoern A. Zeeb * @first_word: magic word value 385bfcc09ddSBjoern A. Zeeb * @second_word: magic word value 386bfcc09ddSBjoern A. Zeeb * @framfrags: DRAM fragmentaion detail 387bfcc09ddSBjoern A. Zeeb */ 388bfcc09ddSBjoern A. Zeeb struct iwl_dram_info { 389bfcc09ddSBjoern A. Zeeb __le32 first_word; 390bfcc09ddSBjoern A. Zeeb __le32 second_word; 391bfcc09ddSBjoern A. Zeeb struct iwl_buf_alloc_cmd dram_frags[IWL_FW_INI_ALLOCATION_NUM - 1]; 392bfcc09ddSBjoern A. Zeeb } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 393bfcc09ddSBjoern A. Zeeb 394bfcc09ddSBjoern A. Zeeb /** 395bfcc09ddSBjoern A. Zeeb * struct iwl_dbgc1_info - DBGC1 address and size 396bfcc09ddSBjoern A. Zeeb * 397bfcc09ddSBjoern A. Zeeb * Driver will fill the dbcg1 address and size at address based on config TLV. 398bfcc09ddSBjoern A. Zeeb * 399bfcc09ddSBjoern A. Zeeb * @first_word: all 0 set as identifier 400bfcc09ddSBjoern A. Zeeb * @dbgc1_add_lsb: LSB bits of DBGC1 physical address 401bfcc09ddSBjoern A. Zeeb * @dbgc1_add_msb: MSB bits of DBGC1 physical address 402bfcc09ddSBjoern A. Zeeb * @dbgc1_size: DBGC1 size 403bfcc09ddSBjoern A. Zeeb */ 404bfcc09ddSBjoern A. Zeeb struct iwl_dbgc1_info { 405bfcc09ddSBjoern A. Zeeb __le32 first_word; 406bfcc09ddSBjoern A. Zeeb __le32 dbgc1_add_lsb; 407bfcc09ddSBjoern A. Zeeb __le32 dbgc1_add_msb; 408bfcc09ddSBjoern A. Zeeb __le32 dbgc1_size; 409bfcc09ddSBjoern A. Zeeb } __packed; /* INIT_DRAM_FRAGS_ALLOCATIONS_S_VER_1 */ 410bfcc09ddSBjoern A. Zeeb 411bfcc09ddSBjoern A. Zeeb /** 412bfcc09ddSBjoern A. Zeeb * struct iwl_dbg_host_event_cfg_cmd 413bfcc09ddSBjoern A. Zeeb * @enabled_severities: enabled severities 414bfcc09ddSBjoern A. Zeeb */ 415bfcc09ddSBjoern A. Zeeb struct iwl_dbg_host_event_cfg_cmd { 416bfcc09ddSBjoern A. Zeeb __le32 enabled_severities; 417bfcc09ddSBjoern A. Zeeb } __packed; /* DEBUG_HOST_EVENT_CFG_CMD_API_S_VER_1 */ 418bfcc09ddSBjoern A. Zeeb 419d9836fb4SBjoern A. Zeeb /** 420d9836fb4SBjoern A. Zeeb * struct iwl_dbg_dump_complete_cmd - dump complete cmd 421d9836fb4SBjoern A. Zeeb * 422d9836fb4SBjoern A. Zeeb * @tp: timepoint whose dump has completed 423d9836fb4SBjoern A. Zeeb * @tp_data: timepoint data 424d9836fb4SBjoern A. Zeeb */ 425d9836fb4SBjoern A. Zeeb struct iwl_dbg_dump_complete_cmd { 426d9836fb4SBjoern A. Zeeb __le32 tp; 427d9836fb4SBjoern A. Zeeb __le32 tp_data; 428d9836fb4SBjoern A. Zeeb } __packed; /* FW_DUMP_COMPLETE_CMD_API_S_VER_1 */ 429d9836fb4SBjoern A. Zeeb 4309af1bba4SBjoern A. Zeeb #define TAS_LMAC_BAND_HB 0 4319af1bba4SBjoern A. Zeeb #define TAS_LMAC_BAND_LB 1 4329af1bba4SBjoern A. Zeeb #define TAS_LMAC_BAND_UHB 2 4339af1bba4SBjoern A. Zeeb #define TAS_LMAC_BAND_INVALID 3 4349af1bba4SBjoern A. Zeeb 4359af1bba4SBjoern A. Zeeb /** 4369af1bba4SBjoern A. Zeeb * struct iwl_mvm_tas_status_per_mac - tas status per lmac 4379af1bba4SBjoern A. Zeeb * @static_status: tas statically enabled or disabled per lmac - TRUE/FALSE 4389af1bba4SBjoern A. Zeeb * @static_dis_reason: TAS static disable reason, uses 4399af1bba4SBjoern A. Zeeb * &enum iwl_mvm_tas_statically_disabled_reason 4409af1bba4SBjoern A. Zeeb * @dynamic_status: Current TAS status. uses 4419af1bba4SBjoern A. Zeeb * &enum iwl_mvm_tas_dyna_status 4429af1bba4SBjoern A. Zeeb * @near_disconnection: is TAS currently near disconnection per lmac? - TRUE/FALSE 4439af1bba4SBjoern A. Zeeb * @max_reg_pwr_limit: Regulatory power limits in dBm 4449af1bba4SBjoern A. Zeeb * @sar_limit: SAR limits per lmac in dBm 4459af1bba4SBjoern A. Zeeb * @band: Band per lmac 4469af1bba4SBjoern A. Zeeb * @reserved: reserved 4479af1bba4SBjoern A. Zeeb */ 4489af1bba4SBjoern A. Zeeb struct iwl_mvm_tas_status_per_mac { 4499af1bba4SBjoern A. Zeeb u8 static_status; 4509af1bba4SBjoern A. Zeeb u8 static_dis_reason; 4519af1bba4SBjoern A. Zeeb u8 dynamic_status; 4529af1bba4SBjoern A. Zeeb u8 near_disconnection; 4539af1bba4SBjoern A. Zeeb __le16 max_reg_pwr_limit; 4549af1bba4SBjoern A. Zeeb __le16 sar_limit; 4559af1bba4SBjoern A. Zeeb u8 band; 4569af1bba4SBjoern A. Zeeb u8 reserved[3]; 4579af1bba4SBjoern A. Zeeb } __packed; /*DEBUG_GET_TAS_STATUS_PER_MAC_S_VER_1*/ 4589af1bba4SBjoern A. Zeeb 4599af1bba4SBjoern A. Zeeb /** 4609af1bba4SBjoern A. Zeeb * struct iwl_mvm_tas_status_resp - Response to GET_TAS_STATUS 4619af1bba4SBjoern A. Zeeb * @tas_fw_version: TAS FW version 4629af1bba4SBjoern A. Zeeb * @is_uhb_for_usa_enable: is UHB enabled in USA? - TRUE/FALSE 4639af1bba4SBjoern A. Zeeb * @curr_mcc: current mcc 4649af1bba4SBjoern A. Zeeb * @block_list: country block list 4659af1bba4SBjoern A. Zeeb * @tas_status_mac: TAS status per lmac, uses 4669af1bba4SBjoern A. Zeeb * &struct iwl_mvm_tas_status_per_mac 4679af1bba4SBjoern A. Zeeb * @in_dual_radio: is TAS in dual radio? - TRUE/FALSE 4689af1bba4SBjoern A. Zeeb * @reserved: reserved 4699af1bba4SBjoern A. Zeeb */ 4709af1bba4SBjoern A. Zeeb struct iwl_mvm_tas_status_resp { 4719af1bba4SBjoern A. Zeeb u8 tas_fw_version; 4729af1bba4SBjoern A. Zeeb u8 is_uhb_for_usa_enable; 4739af1bba4SBjoern A. Zeeb __le16 curr_mcc; 4749af1bba4SBjoern A. Zeeb __le16 block_list[16]; 4759af1bba4SBjoern A. Zeeb struct iwl_mvm_tas_status_per_mac tas_status_mac[2]; 4769af1bba4SBjoern A. Zeeb u8 in_dual_radio; 4779af1bba4SBjoern A. Zeeb u8 reserved[3]; 4789af1bba4SBjoern A. Zeeb } __packed; /*DEBUG_GET_TAS_STATUS_RSP_API_S_VER_3*/ 4799af1bba4SBjoern A. Zeeb 4809af1bba4SBjoern A. Zeeb /** 4819af1bba4SBjoern A. Zeeb * enum iwl_mvm_tas_dyna_status - TAS current running status 4829af1bba4SBjoern A. Zeeb * @TAS_DYNA_INACTIVE: TAS status is inactive 4839af1bba4SBjoern A. Zeeb * @TAS_DYNA_INACTIVE_MVM_MODE: TAS is disabled due because FW is in MVM mode 4849af1bba4SBjoern A. Zeeb * or is in softap mode. 4859af1bba4SBjoern A. Zeeb * @TAS_DYNA_INACTIVE_TRIGGER_MODE: TAS is disabled because FW is in 4869af1bba4SBjoern A. Zeeb * multi user trigger mode 4879af1bba4SBjoern A. Zeeb * @TAS_DYNA_INACTIVE_BLOCK_LISTED: TAS is disabled because current mcc 4889af1bba4SBjoern A. Zeeb * is blocklisted mcc 4899af1bba4SBjoern A. Zeeb * @TAS_DYNA_INACTIVE_UHB_NON_US: TAS is disabled because current band is UHB 4909af1bba4SBjoern A. Zeeb * and current mcc is USA 4919af1bba4SBjoern A. Zeeb * @TAS_DYNA_ACTIVE: TAS is currently active 4929af1bba4SBjoern A. Zeeb * @TAS_DYNA_STATUS_MAX: TAS status max value 4939af1bba4SBjoern A. Zeeb */ 4949af1bba4SBjoern A. Zeeb enum iwl_mvm_tas_dyna_status { 4959af1bba4SBjoern A. Zeeb TAS_DYNA_INACTIVE, 4969af1bba4SBjoern A. Zeeb TAS_DYNA_INACTIVE_MVM_MODE, 4979af1bba4SBjoern A. Zeeb TAS_DYNA_INACTIVE_TRIGGER_MODE, 4989af1bba4SBjoern A. Zeeb TAS_DYNA_INACTIVE_BLOCK_LISTED, 4999af1bba4SBjoern A. Zeeb TAS_DYNA_INACTIVE_UHB_NON_US, 5009af1bba4SBjoern A. Zeeb TAS_DYNA_ACTIVE, 5019af1bba4SBjoern A. Zeeb 5029af1bba4SBjoern A. Zeeb TAS_DYNA_STATUS_MAX, 5039af1bba4SBjoern A. Zeeb }; /*_TAS_DYNA_STATUS_E*/ 5049af1bba4SBjoern A. Zeeb 5059af1bba4SBjoern A. Zeeb /** 5069af1bba4SBjoern A. Zeeb * enum iwl_mvm_tas_statically_disabled_reason - TAS statically disabled reason 5079af1bba4SBjoern A. Zeeb * @TAS_DISABLED_DUE_TO_BIOS: TAS is disabled because TAS is disabled in BIOS 5089af1bba4SBjoern A. Zeeb * @TAS_DISABLED_DUE_TO_SAR_6DBM: TAS is disabled because SAR limit is less than 6 Dbm 5099af1bba4SBjoern A. Zeeb * @TAS_DISABLED_REASON_INVALID: TAS disable reason is invalid 5109af1bba4SBjoern A. Zeeb * @TAS_DISABLED_REASON_MAX: TAS disable reason max value 5119af1bba4SBjoern A. Zeeb */ 5129af1bba4SBjoern A. Zeeb enum iwl_mvm_tas_statically_disabled_reason { 5139af1bba4SBjoern A. Zeeb TAS_DISABLED_DUE_TO_BIOS, 5149af1bba4SBjoern A. Zeeb TAS_DISABLED_DUE_TO_SAR_6DBM, 5159af1bba4SBjoern A. Zeeb TAS_DISABLED_REASON_INVALID, 5169af1bba4SBjoern A. Zeeb 5179af1bba4SBjoern A. Zeeb TAS_DISABLED_REASON_MAX, 5189af1bba4SBjoern A. Zeeb }; /*_TAS_STATICALLY_DISABLED_REASON_E*/ 5199af1bba4SBjoern A. Zeeb 520bfcc09ddSBjoern A. Zeeb #endif /* __iwl_fw_api_debug_h__ */ 521