1bfcc09ddSBjoern A. Zeeb /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2bfcc09ddSBjoern A. Zeeb /* 39af1bba4SBjoern A. Zeeb * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4bfcc09ddSBjoern A. Zeeb * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5bfcc09ddSBjoern A. Zeeb * Copyright (C) 2016 Intel Deutschland GmbH 6bfcc09ddSBjoern A. Zeeb */ 7bfcc09ddSBjoern A. Zeeb #ifndef __iwl_prph_h__ 8bfcc09ddSBjoern A. Zeeb #define __iwl_prph_h__ 9bfcc09ddSBjoern A. Zeeb #include <linux/bitfield.h> 10bfcc09ddSBjoern A. Zeeb 11bfcc09ddSBjoern A. Zeeb /* 12bfcc09ddSBjoern A. Zeeb * Registers in this file are internal, not PCI bus memory mapped. 13bfcc09ddSBjoern A. Zeeb * Driver accesses these via HBUS_TARG_PRPH_* registers. 14bfcc09ddSBjoern A. Zeeb */ 15bfcc09ddSBjoern A. Zeeb #define PRPH_BASE (0x00000) 16bfcc09ddSBjoern A. Zeeb #define PRPH_END (0xFFFFF) 17bfcc09ddSBjoern A. Zeeb 18bfcc09ddSBjoern A. Zeeb /* APMG (power management) constants */ 19bfcc09ddSBjoern A. Zeeb #define APMG_BASE (PRPH_BASE + 0x3000) 20bfcc09ddSBjoern A. Zeeb #define APMG_CLK_CTRL_REG (APMG_BASE + 0x0000) 21bfcc09ddSBjoern A. Zeeb #define APMG_CLK_EN_REG (APMG_BASE + 0x0004) 22bfcc09ddSBjoern A. Zeeb #define APMG_CLK_DIS_REG (APMG_BASE + 0x0008) 23bfcc09ddSBjoern A. Zeeb #define APMG_PS_CTRL_REG (APMG_BASE + 0x000c) 24bfcc09ddSBjoern A. Zeeb #define APMG_PCIDEV_STT_REG (APMG_BASE + 0x0010) 25bfcc09ddSBjoern A. Zeeb #define APMG_RFKILL_REG (APMG_BASE + 0x0014) 26bfcc09ddSBjoern A. Zeeb #define APMG_RTC_INT_STT_REG (APMG_BASE + 0x001c) 27bfcc09ddSBjoern A. Zeeb #define APMG_RTC_INT_MSK_REG (APMG_BASE + 0x0020) 28bfcc09ddSBjoern A. Zeeb #define APMG_DIGITAL_SVR_REG (APMG_BASE + 0x0058) 29bfcc09ddSBjoern A. Zeeb #define APMG_ANALOG_SVR_REG (APMG_BASE + 0x006C) 30bfcc09ddSBjoern A. Zeeb 31bfcc09ddSBjoern A. Zeeb #define APMS_CLK_VAL_MRB_FUNC_MODE (0x00000001) 32bfcc09ddSBjoern A. Zeeb #define APMG_CLK_VAL_DMA_CLK_RQT (0x00000200) 33bfcc09ddSBjoern A. Zeeb #define APMG_CLK_VAL_BSM_CLK_RQT (0x00000800) 34bfcc09ddSBjoern A. Zeeb 35bfcc09ddSBjoern A. Zeeb #define APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS (0x00400000) 36bfcc09ddSBjoern A. Zeeb #define APMG_PS_CTRL_VAL_RESET_REQ (0x04000000) 37bfcc09ddSBjoern A. Zeeb #define APMG_PS_CTRL_MSK_PWR_SRC (0x03000000) 38bfcc09ddSBjoern A. Zeeb #define APMG_PS_CTRL_VAL_PWR_SRC_VMAIN (0x00000000) 39bfcc09ddSBjoern A. Zeeb #define APMG_PS_CTRL_VAL_PWR_SRC_VAUX (0x02000000) 40bfcc09ddSBjoern A. Zeeb #define APMG_SVR_VOLTAGE_CONFIG_BIT_MSK (0x000001E0) /* bit 8:5 */ 41bfcc09ddSBjoern A. Zeeb #define APMG_SVR_DIGITAL_VOLTAGE_1_32 (0x00000060) 42bfcc09ddSBjoern A. Zeeb 43bfcc09ddSBjoern A. Zeeb #define APMG_PCIDEV_STT_VAL_PERSIST_DIS (0x00000200) 44bfcc09ddSBjoern A. Zeeb #define APMG_PCIDEV_STT_VAL_L1_ACT_DIS (0x00000800) 45bfcc09ddSBjoern A. Zeeb #define APMG_PCIDEV_STT_VAL_WAKE_ME (0x00004000) 46bfcc09ddSBjoern A. Zeeb 47bfcc09ddSBjoern A. Zeeb #define APMG_RTC_INT_STT_RFKILL (0x10000000) 48bfcc09ddSBjoern A. Zeeb 49bfcc09ddSBjoern A. Zeeb /* Device system time */ 50bfcc09ddSBjoern A. Zeeb #define DEVICE_SYSTEM_TIME_REG 0xA0206C 51bfcc09ddSBjoern A. Zeeb 52bfcc09ddSBjoern A. Zeeb /* Device NMI register and value for 8000 family and lower hw's */ 53bfcc09ddSBjoern A. Zeeb #define DEVICE_SET_NMI_REG 0x00a01c30 54bfcc09ddSBjoern A. Zeeb #define DEVICE_SET_NMI_VAL_DRV BIT(7) 55bfcc09ddSBjoern A. Zeeb /* Device NMI register and value for 9000 family and above hw's */ 56bfcc09ddSBjoern A. Zeeb #define UREG_NIC_SET_NMI_DRIVER 0x00a05c10 57bfcc09ddSBjoern A. Zeeb #define UREG_NIC_SET_NMI_DRIVER_NMI_FROM_DRIVER BIT(24) 58bfcc09ddSBjoern A. Zeeb #define UREG_NIC_SET_NMI_DRIVER_RESET_HANDSHAKE (BIT(24) | BIT(25)) 59bfcc09ddSBjoern A. Zeeb 60bfcc09ddSBjoern A. Zeeb /* Shared registers (0x0..0x3ff, via target indirect or periphery */ 61bfcc09ddSBjoern A. Zeeb #define SHR_BASE 0x00a10000 62bfcc09ddSBjoern A. Zeeb 63bfcc09ddSBjoern A. Zeeb /* Shared GP1 register */ 64bfcc09ddSBjoern A. Zeeb #define SHR_APMG_GP1_REG 0x01dc 65bfcc09ddSBjoern A. Zeeb #define SHR_APMG_GP1_REG_PRPH (SHR_BASE + SHR_APMG_GP1_REG) 66bfcc09ddSBjoern A. Zeeb #define SHR_APMG_GP1_WF_XTAL_LP_EN 0x00000004 67bfcc09ddSBjoern A. Zeeb #define SHR_APMG_GP1_CHICKEN_BIT_SELECT 0x80000000 68bfcc09ddSBjoern A. Zeeb 69bfcc09ddSBjoern A. Zeeb /* Shared DL_CFG register */ 70bfcc09ddSBjoern A. Zeeb #define SHR_APMG_DL_CFG_REG 0x01c4 71bfcc09ddSBjoern A. Zeeb #define SHR_APMG_DL_CFG_REG_PRPH (SHR_BASE + SHR_APMG_DL_CFG_REG) 72bfcc09ddSBjoern A. Zeeb #define SHR_APMG_DL_CFG_RTCS_CLK_SELECTOR_MSK 0x000000c0 73bfcc09ddSBjoern A. Zeeb #define SHR_APMG_DL_CFG_RTCS_CLK_INTERNAL_XTAL 0x00000080 74bfcc09ddSBjoern A. Zeeb #define SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP 0x00000100 75bfcc09ddSBjoern A. Zeeb 76bfcc09ddSBjoern A. Zeeb /* Shared APMG_XTAL_CFG register */ 77bfcc09ddSBjoern A. Zeeb #define SHR_APMG_XTAL_CFG_REG 0x1c0 78bfcc09ddSBjoern A. Zeeb #define SHR_APMG_XTAL_CFG_XTAL_ON_REQ 0x80000000 79bfcc09ddSBjoern A. Zeeb 80bfcc09ddSBjoern A. Zeeb /* 81bfcc09ddSBjoern A. Zeeb * Device reset for family 8000 82bfcc09ddSBjoern A. Zeeb * write to bit 24 in order to reset the CPU 83bfcc09ddSBjoern A. Zeeb */ 84bfcc09ddSBjoern A. Zeeb #define RELEASE_CPU_RESET (0x300C) 85bfcc09ddSBjoern A. Zeeb #define RELEASE_CPU_RESET_BIT BIT(24) 86bfcc09ddSBjoern A. Zeeb 87bfcc09ddSBjoern A. Zeeb /***************************************************************************** 88bfcc09ddSBjoern A. Zeeb * 7000/3000 series SHR DTS addresses * 89bfcc09ddSBjoern A. Zeeb *****************************************************************************/ 90bfcc09ddSBjoern A. Zeeb 91bfcc09ddSBjoern A. Zeeb #define SHR_MISC_WFM_DTS_EN (0x00a10024) 92bfcc09ddSBjoern A. Zeeb #define DTSC_CFG_MODE (0x00a10604) 93bfcc09ddSBjoern A. Zeeb #define DTSC_VREF_AVG (0x00a10648) 94bfcc09ddSBjoern A. Zeeb #define DTSC_VREF5_AVG (0x00a1064c) 95bfcc09ddSBjoern A. Zeeb #define DTSC_CFG_MODE_PERIODIC (0x2) 96bfcc09ddSBjoern A. Zeeb #define DTSC_PTAT_AVG (0x00a10650) 97bfcc09ddSBjoern A. Zeeb 98bfcc09ddSBjoern A. Zeeb 99bfcc09ddSBjoern A. Zeeb /** 100bfcc09ddSBjoern A. Zeeb * Tx Scheduler 101bfcc09ddSBjoern A. Zeeb * 102bfcc09ddSBjoern A. Zeeb * The Tx Scheduler selects the next frame to be transmitted, choosing TFDs 103bfcc09ddSBjoern A. Zeeb * (Transmit Frame Descriptors) from up to 16 circular Tx queues resident in 104bfcc09ddSBjoern A. Zeeb * host DRAM. It steers each frame's Tx command (which contains the frame 105bfcc09ddSBjoern A. Zeeb * data) into one of up to 7 prioritized Tx DMA FIFO channels within the 106bfcc09ddSBjoern A. Zeeb * device. A queue maps to only one (selectable by driver) Tx DMA channel, 107bfcc09ddSBjoern A. Zeeb * but one DMA channel may take input from several queues. 108bfcc09ddSBjoern A. Zeeb * 109bfcc09ddSBjoern A. Zeeb * Tx DMA FIFOs have dedicated purposes. 110bfcc09ddSBjoern A. Zeeb * 111bfcc09ddSBjoern A. Zeeb * For 5000 series and up, they are used differently 112bfcc09ddSBjoern A. Zeeb * (cf. iwl5000_default_queue_to_tx_fifo in iwl-5000.c): 113bfcc09ddSBjoern A. Zeeb * 114bfcc09ddSBjoern A. Zeeb * 0 -- EDCA BK (background) frames, lowest priority 115bfcc09ddSBjoern A. Zeeb * 1 -- EDCA BE (best effort) frames, normal priority 116bfcc09ddSBjoern A. Zeeb * 2 -- EDCA VI (video) frames, higher priority 117bfcc09ddSBjoern A. Zeeb * 3 -- EDCA VO (voice) and management frames, highest priority 118bfcc09ddSBjoern A. Zeeb * 4 -- unused 119bfcc09ddSBjoern A. Zeeb * 5 -- unused 120bfcc09ddSBjoern A. Zeeb * 6 -- unused 121bfcc09ddSBjoern A. Zeeb * 7 -- Commands 122bfcc09ddSBjoern A. Zeeb * 123bfcc09ddSBjoern A. Zeeb * Driver should normally map queues 0-6 to Tx DMA/FIFO channels 0-6. 124bfcc09ddSBjoern A. Zeeb * In addition, driver can map the remaining queues to Tx DMA/FIFO 125bfcc09ddSBjoern A. Zeeb * channels 0-3 to support 11n aggregation via EDCA DMA channels. 126bfcc09ddSBjoern A. Zeeb * 127bfcc09ddSBjoern A. Zeeb * The driver sets up each queue to work in one of two modes: 128bfcc09ddSBjoern A. Zeeb * 129bfcc09ddSBjoern A. Zeeb * 1) Scheduler-Ack, in which the scheduler automatically supports a 130bfcc09ddSBjoern A. Zeeb * block-ack (BA) window of up to 64 TFDs. In this mode, each queue 131bfcc09ddSBjoern A. Zeeb * contains TFDs for a unique combination of Recipient Address (RA) 132bfcc09ddSBjoern A. Zeeb * and Traffic Identifier (TID), that is, traffic of a given 133bfcc09ddSBjoern A. Zeeb * Quality-Of-Service (QOS) priority, destined for a single station. 134bfcc09ddSBjoern A. Zeeb * 135bfcc09ddSBjoern A. Zeeb * In scheduler-ack mode, the scheduler keeps track of the Tx status of 136bfcc09ddSBjoern A. Zeeb * each frame within the BA window, including whether it's been transmitted, 137bfcc09ddSBjoern A. Zeeb * and whether it's been acknowledged by the receiving station. The device 138bfcc09ddSBjoern A. Zeeb * automatically processes block-acks received from the receiving STA, 139bfcc09ddSBjoern A. Zeeb * and reschedules un-acked frames to be retransmitted (successful 140bfcc09ddSBjoern A. Zeeb * Tx completion may end up being out-of-order). 141bfcc09ddSBjoern A. Zeeb * 142bfcc09ddSBjoern A. Zeeb * The driver must maintain the queue's Byte Count table in host DRAM 143bfcc09ddSBjoern A. Zeeb * for this mode. 144bfcc09ddSBjoern A. Zeeb * This mode does not support fragmentation. 145bfcc09ddSBjoern A. Zeeb * 146bfcc09ddSBjoern A. Zeeb * 2) FIFO (a.k.a. non-Scheduler-ACK), in which each TFD is processed in order. 147bfcc09ddSBjoern A. Zeeb * The device may automatically retry Tx, but will retry only one frame 148bfcc09ddSBjoern A. Zeeb * at a time, until receiving ACK from receiving station, or reaching 149bfcc09ddSBjoern A. Zeeb * retry limit and giving up. 150bfcc09ddSBjoern A. Zeeb * 151bfcc09ddSBjoern A. Zeeb * The command queue (#4/#9) must use this mode! 152bfcc09ddSBjoern A. Zeeb * This mode does not require use of the Byte Count table in host DRAM. 153bfcc09ddSBjoern A. Zeeb * 154bfcc09ddSBjoern A. Zeeb * Driver controls scheduler operation via 3 means: 155bfcc09ddSBjoern A. Zeeb * 1) Scheduler registers 156bfcc09ddSBjoern A. Zeeb * 2) Shared scheduler data base in internal SRAM 157bfcc09ddSBjoern A. Zeeb * 3) Shared data in host DRAM 158bfcc09ddSBjoern A. Zeeb * 159bfcc09ddSBjoern A. Zeeb * Initialization: 160bfcc09ddSBjoern A. Zeeb * 161bfcc09ddSBjoern A. Zeeb * When loading, driver should allocate memory for: 162bfcc09ddSBjoern A. Zeeb * 1) 16 TFD circular buffers, each with space for (typically) 256 TFDs. 163bfcc09ddSBjoern A. Zeeb * 2) 16 Byte Count circular buffers in 16 KBytes contiguous memory 164bfcc09ddSBjoern A. Zeeb * (1024 bytes for each queue). 165bfcc09ddSBjoern A. Zeeb * 166bfcc09ddSBjoern A. Zeeb * After receiving "Alive" response from uCode, driver must initialize 167bfcc09ddSBjoern A. Zeeb * the scheduler (especially for queue #4/#9, the command queue, otherwise 168bfcc09ddSBjoern A. Zeeb * the driver can't issue commands!): 169bfcc09ddSBjoern A. Zeeb */ 170bfcc09ddSBjoern A. Zeeb #define SCD_MEM_LOWER_BOUND (0x0000) 171bfcc09ddSBjoern A. Zeeb 172bfcc09ddSBjoern A. Zeeb /** 173bfcc09ddSBjoern A. Zeeb * Max Tx window size is the max number of contiguous TFDs that the scheduler 174bfcc09ddSBjoern A. Zeeb * can keep track of at one time when creating block-ack chains of frames. 175bfcc09ddSBjoern A. Zeeb * Note that "64" matches the number of ack bits in a block-ack packet. 176bfcc09ddSBjoern A. Zeeb */ 177bfcc09ddSBjoern A. Zeeb #define SCD_WIN_SIZE 64 178bfcc09ddSBjoern A. Zeeb #define SCD_FRAME_LIMIT 64 179bfcc09ddSBjoern A. Zeeb 180bfcc09ddSBjoern A. Zeeb #define SCD_TXFIFO_POS_TID (0) 181bfcc09ddSBjoern A. Zeeb #define SCD_TXFIFO_POS_RA (4) 182bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_RA_TID_MAP_RATID_MSK (0x01FF) 183bfcc09ddSBjoern A. Zeeb 184bfcc09ddSBjoern A. Zeeb /* agn SCD */ 185bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_STTS_REG_POS_TXF (0) 186bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_STTS_REG_POS_ACTIVE (3) 187bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_STTS_REG_POS_WSL (4) 188bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN (19) 189bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_STTS_REG_MSK (0x017F0000) 190bfcc09ddSBjoern A. Zeeb 191bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_CTX_REG1_CREDIT (0x00FFFF00) 192bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_CTX_REG1_SUPER_CREDIT (0xFF000000) 193bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_CTX_REG1_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG1_ ## _n, _v) 194bfcc09ddSBjoern A. Zeeb 195bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_CTX_REG2_WIN_SIZE (0x0000007F) 196bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_CTX_REG2_FRAME_LIMIT (0x007F0000) 197bfcc09ddSBjoern A. Zeeb #define SCD_QUEUE_CTX_REG2_VAL(_n, _v) FIELD_PREP(SCD_QUEUE_CTX_REG2_ ## _n, _v) 198bfcc09ddSBjoern A. Zeeb 199bfcc09ddSBjoern A. Zeeb #define SCD_GP_CTRL_ENABLE_31_QUEUES BIT(0) 200bfcc09ddSBjoern A. Zeeb #define SCD_GP_CTRL_AUTO_ACTIVE_MODE BIT(18) 201bfcc09ddSBjoern A. Zeeb 202bfcc09ddSBjoern A. Zeeb /* Context Data */ 203bfcc09ddSBjoern A. Zeeb #define SCD_CONTEXT_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x600) 204bfcc09ddSBjoern A. Zeeb #define SCD_CONTEXT_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) 205bfcc09ddSBjoern A. Zeeb 206bfcc09ddSBjoern A. Zeeb /* Tx status */ 207bfcc09ddSBjoern A. Zeeb #define SCD_TX_STTS_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x6A0) 208bfcc09ddSBjoern A. Zeeb #define SCD_TX_STTS_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) 209bfcc09ddSBjoern A. Zeeb 210bfcc09ddSBjoern A. Zeeb /* Translation Data */ 211bfcc09ddSBjoern A. Zeeb #define SCD_TRANS_TBL_MEM_LOWER_BOUND (SCD_MEM_LOWER_BOUND + 0x7E0) 212bfcc09ddSBjoern A. Zeeb #define SCD_TRANS_TBL_MEM_UPPER_BOUND (SCD_MEM_LOWER_BOUND + 0x808) 213bfcc09ddSBjoern A. Zeeb 214bfcc09ddSBjoern A. Zeeb #define SCD_CONTEXT_QUEUE_OFFSET(x)\ 215bfcc09ddSBjoern A. Zeeb (SCD_CONTEXT_MEM_LOWER_BOUND + ((x) * 8)) 216bfcc09ddSBjoern A. Zeeb 217bfcc09ddSBjoern A. Zeeb #define SCD_TX_STTS_QUEUE_OFFSET(x)\ 218bfcc09ddSBjoern A. Zeeb (SCD_TX_STTS_MEM_LOWER_BOUND + ((x) * 16)) 219bfcc09ddSBjoern A. Zeeb 220bfcc09ddSBjoern A. Zeeb #define SCD_TRANS_TBL_OFFSET_QUEUE(x) \ 221bfcc09ddSBjoern A. Zeeb ((SCD_TRANS_TBL_MEM_LOWER_BOUND + ((x) * 2)) & 0xfffc) 222bfcc09ddSBjoern A. Zeeb 223bfcc09ddSBjoern A. Zeeb #define SCD_BASE (PRPH_BASE + 0xa02c00) 224bfcc09ddSBjoern A. Zeeb 225bfcc09ddSBjoern A. Zeeb #define SCD_SRAM_BASE_ADDR (SCD_BASE + 0x0) 226bfcc09ddSBjoern A. Zeeb #define SCD_DRAM_BASE_ADDR (SCD_BASE + 0x8) 227bfcc09ddSBjoern A. Zeeb #define SCD_AIT (SCD_BASE + 0x0c) 228bfcc09ddSBjoern A. Zeeb #define SCD_TXFACT (SCD_BASE + 0x10) 229bfcc09ddSBjoern A. Zeeb #define SCD_ACTIVE (SCD_BASE + 0x14) 230bfcc09ddSBjoern A. Zeeb #define SCD_QUEUECHAIN_SEL (SCD_BASE + 0xe8) 231bfcc09ddSBjoern A. Zeeb #define SCD_CHAINEXT_EN (SCD_BASE + 0x244) 232bfcc09ddSBjoern A. Zeeb #define SCD_AGGR_SEL (SCD_BASE + 0x248) 233bfcc09ddSBjoern A. Zeeb #define SCD_INTERRUPT_MASK (SCD_BASE + 0x108) 234bfcc09ddSBjoern A. Zeeb #define SCD_GP_CTRL (SCD_BASE + 0x1a8) 235bfcc09ddSBjoern A. Zeeb #define SCD_EN_CTRL (SCD_BASE + 0x254) 236bfcc09ddSBjoern A. Zeeb 237bfcc09ddSBjoern A. Zeeb /*********************** END TX SCHEDULER *************************************/ 238bfcc09ddSBjoern A. Zeeb 239bfcc09ddSBjoern A. Zeeb /* Oscillator clock */ 240bfcc09ddSBjoern A. Zeeb #define OSC_CLK (0xa04068) 241bfcc09ddSBjoern A. Zeeb #define OSC_CLK_FORCE_CONTROL (0x8) 242bfcc09ddSBjoern A. Zeeb 243bfcc09ddSBjoern A. Zeeb #define FH_UCODE_LOAD_STATUS (0x1AF0) 244bfcc09ddSBjoern A. Zeeb 245bfcc09ddSBjoern A. Zeeb /* 246bfcc09ddSBjoern A. Zeeb * Replacing FH_UCODE_LOAD_STATUS 247bfcc09ddSBjoern A. Zeeb * This register is writen by driver and is read by uCode during boot flow. 248bfcc09ddSBjoern A. Zeeb * Note this address is cleared after MAC reset. 249bfcc09ddSBjoern A. Zeeb */ 250bfcc09ddSBjoern A. Zeeb #define UREG_UCODE_LOAD_STATUS (0xa05c40) 251bfcc09ddSBjoern A. Zeeb #define UREG_CPU_INIT_RUN (0xa05c44) 252bfcc09ddSBjoern A. Zeeb 253bfcc09ddSBjoern A. Zeeb #define LMPM_SECURE_UCODE_LOAD_CPU1_HDR_ADDR (0x1E78) 254bfcc09ddSBjoern A. Zeeb #define LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR (0x1E7C) 255bfcc09ddSBjoern A. Zeeb 256bfcc09ddSBjoern A. Zeeb #define LMPM_SECURE_CPU1_HDR_MEM_SPACE (0x420000) 257bfcc09ddSBjoern A. Zeeb #define LMPM_SECURE_CPU2_HDR_MEM_SPACE (0x420400) 258bfcc09ddSBjoern A. Zeeb 259bfcc09ddSBjoern A. Zeeb #define LMAC2_PRPH_OFFSET (0x100000) 260bfcc09ddSBjoern A. Zeeb 261bfcc09ddSBjoern A. Zeeb /* Rx FIFO */ 262bfcc09ddSBjoern A. Zeeb #define RXF_SIZE_ADDR (0xa00c88) 263bfcc09ddSBjoern A. Zeeb #define RXF_RD_D_SPACE (0xa00c40) 264bfcc09ddSBjoern A. Zeeb #define RXF_RD_WR_PTR (0xa00c50) 265bfcc09ddSBjoern A. Zeeb #define RXF_RD_RD_PTR (0xa00c54) 266bfcc09ddSBjoern A. Zeeb #define RXF_RD_FENCE_PTR (0xa00c4c) 267bfcc09ddSBjoern A. Zeeb #define RXF_SET_FENCE_MODE (0xa00c14) 268bfcc09ddSBjoern A. Zeeb #define RXF_LD_WR2FENCE (0xa00c1c) 269bfcc09ddSBjoern A. Zeeb #define RXF_FIFO_RD_FENCE_INC (0xa00c68) 270bfcc09ddSBjoern A. Zeeb #define RXF_SIZE_BYTE_CND_POS (7) 271bfcc09ddSBjoern A. Zeeb #define RXF_SIZE_BYTE_CNT_MSK (0x3ff << RXF_SIZE_BYTE_CND_POS) 272bfcc09ddSBjoern A. Zeeb #define RXF_DIFF_FROM_PREV (0x200) 273bfcc09ddSBjoern A. Zeeb #define RXF2C_DIFF_FROM_PREV (0x4e00) 274bfcc09ddSBjoern A. Zeeb 275bfcc09ddSBjoern A. Zeeb #define RXF_LD_FENCE_OFFSET_ADDR (0xa00c10) 276bfcc09ddSBjoern A. Zeeb #define RXF_FIFO_RD_FENCE_ADDR (0xa00c0c) 277bfcc09ddSBjoern A. Zeeb 278bfcc09ddSBjoern A. Zeeb /* Tx FIFO */ 279bfcc09ddSBjoern A. Zeeb #define TXF_FIFO_ITEM_CNT (0xa00438) 280bfcc09ddSBjoern A. Zeeb #define TXF_WR_PTR (0xa00414) 281bfcc09ddSBjoern A. Zeeb #define TXF_RD_PTR (0xa00410) 282bfcc09ddSBjoern A. Zeeb #define TXF_FENCE_PTR (0xa00418) 283bfcc09ddSBjoern A. Zeeb #define TXF_LOCK_FENCE (0xa00424) 284bfcc09ddSBjoern A. Zeeb #define TXF_LARC_NUM (0xa0043c) 285bfcc09ddSBjoern A. Zeeb #define TXF_READ_MODIFY_DATA (0xa00448) 286bfcc09ddSBjoern A. Zeeb #define TXF_READ_MODIFY_ADDR (0xa0044c) 287bfcc09ddSBjoern A. Zeeb 288bfcc09ddSBjoern A. Zeeb /* UMAC Internal Tx Fifo */ 289bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_FIFO_ITEM_CNT (0xA00538) 290bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_WR_PTR (0xA00514) 291bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_RD_PTR (0xA00510) 292bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_FENCE_PTR (0xA00518) 293bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_LOCK_FENCE (0xA00524) 294bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_NUM (0xA0053C) 295bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_READ_MODIFY_DATA (0xA00548) 296bfcc09ddSBjoern A. Zeeb #define TXF_CPU2_READ_MODIFY_ADDR (0xA0054C) 297bfcc09ddSBjoern A. Zeeb 298bfcc09ddSBjoern A. Zeeb /* Radio registers access */ 299bfcc09ddSBjoern A. Zeeb #define RSP_RADIO_CMD (0xa02804) 300bfcc09ddSBjoern A. Zeeb #define RSP_RADIO_RDDAT (0xa02814) 301bfcc09ddSBjoern A. Zeeb #define RADIO_RSP_ADDR_POS (6) 302bfcc09ddSBjoern A. Zeeb #define RADIO_RSP_RD_CMD (3) 303bfcc09ddSBjoern A. Zeeb 304bfcc09ddSBjoern A. Zeeb /* LTR control (Qu only) */ 305bfcc09ddSBjoern A. Zeeb #define HPM_MAC_LTR_CSR 0xa0348c 306bfcc09ddSBjoern A. Zeeb #define HPM_MAC_LRT_ENABLE_ALL 0xf 307bfcc09ddSBjoern A. Zeeb /* also uses CSR_LTR_* for values */ 308bfcc09ddSBjoern A. Zeeb #define HPM_UMAC_LTR 0xa03480 309bfcc09ddSBjoern A. Zeeb 310bfcc09ddSBjoern A. Zeeb /* FW monitor */ 311bfcc09ddSBjoern A. Zeeb #define MON_BUFF_SAMPLE_CTL (0xa03c00) 312bfcc09ddSBjoern A. Zeeb #define MON_BUFF_BASE_ADDR (0xa03c1c) 313bfcc09ddSBjoern A. Zeeb #define MON_BUFF_END_ADDR (0xa03c40) 314bfcc09ddSBjoern A. Zeeb #define MON_BUFF_WRPTR (0xa03c44) 315bfcc09ddSBjoern A. Zeeb #define MON_BUFF_CYCLE_CNT (0xa03c48) 316bfcc09ddSBjoern A. Zeeb /* FW monitor family 8000 and on */ 317bfcc09ddSBjoern A. Zeeb #define MON_BUFF_BASE_ADDR_VER2 (0xa03c1c) 318bfcc09ddSBjoern A. Zeeb #define MON_BUFF_END_ADDR_VER2 (0xa03c20) 319bfcc09ddSBjoern A. Zeeb #define MON_BUFF_WRPTR_VER2 (0xa03c24) 320bfcc09ddSBjoern A. Zeeb #define MON_BUFF_CYCLE_CNT_VER2 (0xa03c28) 321bfcc09ddSBjoern A. Zeeb #define MON_BUFF_SHIFT_VER2 (0x8) 322bfcc09ddSBjoern A. Zeeb /* FW monitor familiy AX210 and on */ 323bfcc09ddSBjoern A. Zeeb #define DBGC_CUR_DBGBUF_BASE_ADDR_LSB (0xd03c20) 324bfcc09ddSBjoern A. Zeeb #define DBGC_CUR_DBGBUF_BASE_ADDR_MSB (0xd03c24) 325bfcc09ddSBjoern A. Zeeb #define DBGC_CUR_DBGBUF_STATUS (0xd03c1c) 326bfcc09ddSBjoern A. Zeeb #define DBGC_DBGBUF_WRAP_AROUND (0xd03c2c) 327bfcc09ddSBjoern A. Zeeb #define DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK (0x00ffffff) 328bfcc09ddSBjoern A. Zeeb #define DBGC_CUR_DBGBUF_STATUS_IDX_MSK (0x0f000000) 329bfcc09ddSBjoern A. Zeeb 330bfcc09ddSBjoern A. Zeeb #define MON_DMARB_RD_CTL_ADDR (0xa03c60) 331bfcc09ddSBjoern A. Zeeb #define MON_DMARB_RD_DATA_ADDR (0xa03c5c) 332bfcc09ddSBjoern A. Zeeb 333bfcc09ddSBjoern A. Zeeb #define DBGC_IN_SAMPLE (0xa03c00) 334bfcc09ddSBjoern A. Zeeb #define DBGC_OUT_CTRL (0xa03c0c) 335bfcc09ddSBjoern A. Zeeb 336bfcc09ddSBjoern A. Zeeb /* M2S registers */ 337bfcc09ddSBjoern A. Zeeb #define LDBG_M2S_BUF_WPTR (0xa0476c) 338bfcc09ddSBjoern A. Zeeb #define LDBG_M2S_BUF_WRAP_CNT (0xa04774) 339bfcc09ddSBjoern A. Zeeb #define LDBG_M2S_BUF_WPTR_VAL_MSK (0x000fffff) 340bfcc09ddSBjoern A. Zeeb #define LDBG_M2S_BUF_WRAP_CNT_VAL_MSK (0x000fffff) 341bfcc09ddSBjoern A. Zeeb 342bfcc09ddSBjoern A. Zeeb /* enable the ID buf for read */ 343bfcc09ddSBjoern A. Zeeb #define WFPM_PS_CTL_CLR 0xA0300C 344bfcc09ddSBjoern A. Zeeb #define WFMP_MAC_ADDR_0 0xA03080 345bfcc09ddSBjoern A. Zeeb #define WFMP_MAC_ADDR_1 0xA03084 346bfcc09ddSBjoern A. Zeeb #define LMPM_PMG_EN 0xA01CEC 347bfcc09ddSBjoern A. Zeeb #define RADIO_REG_SYS_MANUAL_DFT_0 0xAD4078 348bfcc09ddSBjoern A. Zeeb #define RFIC_REG_RD 0xAD0470 349bfcc09ddSBjoern A. Zeeb #define WFPM_CTRL_REG 0xA03030 350bfcc09ddSBjoern A. Zeeb #define WFPM_OTP_CFG1_ADDR 0x00a03098 351bfcc09ddSBjoern A. Zeeb #define WFPM_OTP_CFG1_IS_JACKET_BIT BIT(4) 352bfcc09ddSBjoern A. Zeeb #define WFPM_OTP_CFG1_IS_CDB_BIT BIT(5) 3539af1bba4SBjoern A. Zeeb #define WFPM_OTP_BZ_BNJ_JACKET_BIT 5 3549af1bba4SBjoern A. Zeeb #define WFPM_OTP_BZ_BNJ_CDB_BIT 4 3559af1bba4SBjoern A. Zeeb #define WFPM_OTP_CFG1_IS_JACKET(_val) (((_val) & 0x00000020) >> WFPM_OTP_BZ_BNJ_JACKET_BIT) 3569af1bba4SBjoern A. Zeeb #define WFPM_OTP_CFG1_IS_CDB(_val) (((_val) & 0x00000010) >> WFPM_OTP_BZ_BNJ_CDB_BIT) 3579af1bba4SBjoern A. Zeeb 358bfcc09ddSBjoern A. Zeeb 359bfcc09ddSBjoern A. Zeeb #define WFPM_GP2 0xA030B4 360bfcc09ddSBjoern A. Zeeb 361bfcc09ddSBjoern A. Zeeb /* DBGI SRAM Register details */ 362bfcc09ddSBjoern A. Zeeb #define DBGI_SRAM_TARGET_ACCESS_RDATA_LSB 0x00A2E154 363bfcc09ddSBjoern A. Zeeb #define DBGI_SRAM_TARGET_ACCESS_RDATA_MSB 0x00A2E158 364d9836fb4SBjoern A. Zeeb #define DBGI_SRAM_FIFO_POINTERS 0x00A2E148 365d9836fb4SBjoern A. Zeeb #define DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK 0x00000FFF 366bfcc09ddSBjoern A. Zeeb 367bfcc09ddSBjoern A. Zeeb enum { 368bfcc09ddSBjoern A. Zeeb ENABLE_WFPM = BIT(31), 369bfcc09ddSBjoern A. Zeeb WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK = 0x80000000, 370bfcc09ddSBjoern A. Zeeb }; 371bfcc09ddSBjoern A. Zeeb 372bfcc09ddSBjoern A. Zeeb #define CNVI_AUX_MISC_CHIP 0xA200B0 373bfcc09ddSBjoern A. Zeeb #define CNVR_AUX_MISC_CHIP 0xA2B800 374bfcc09ddSBjoern A. Zeeb #define CNVR_SCU_SD_REGS_SD_REG_DIG_DCDC_VTRIM 0xA29890 375bfcc09ddSBjoern A. Zeeb #define CNVR_SCU_SD_REGS_SD_REG_ACTIVE_VDIG_MIRROR 0xA29938 3769af1bba4SBjoern A. Zeeb #define CNVI_SCU_SEQ_DATA_DW9 0xA27488 377bfcc09ddSBjoern A. Zeeb 378bfcc09ddSBjoern A. Zeeb #define PREG_AUX_BUS_WPROT_0 0xA04CC0 379bfcc09ddSBjoern A. Zeeb 380bfcc09ddSBjoern A. Zeeb /* device family 9000 WPROT register */ 381bfcc09ddSBjoern A. Zeeb #define PREG_PRPH_WPROT_9000 0xA04CE0 382bfcc09ddSBjoern A. Zeeb /* device family 22000 WPROT register */ 383bfcc09ddSBjoern A. Zeeb #define PREG_PRPH_WPROT_22000 0xA04D00 384bfcc09ddSBjoern A. Zeeb 385bfcc09ddSBjoern A. Zeeb #define SB_MODIFY_CFG_FLAG 0xA03088 3869af1bba4SBjoern A. Zeeb #define SB_CFG_RESIDES_IN_OTP_MASK 0x10 387bfcc09ddSBjoern A. Zeeb #define SB_CPU_1_STATUS 0xA01E30 388bfcc09ddSBjoern A. Zeeb #define SB_CPU_2_STATUS 0xA01E34 389bfcc09ddSBjoern A. Zeeb #define UMAG_SB_CPU_1_STATUS 0xA038C0 390bfcc09ddSBjoern A. Zeeb #define UMAG_SB_CPU_2_STATUS 0xA038C4 391bfcc09ddSBjoern A. Zeeb #define UMAG_GEN_HW_STATUS 0xA038C8 392bfcc09ddSBjoern A. Zeeb #define UREG_UMAC_CURRENT_PC 0xa05c18 393bfcc09ddSBjoern A. Zeeb #define UREG_LMAC1_CURRENT_PC 0xa05c1c 394bfcc09ddSBjoern A. Zeeb #define UREG_LMAC2_CURRENT_PC 0xa05c20 395bfcc09ddSBjoern A. Zeeb 396d9836fb4SBjoern A. Zeeb #define WFPM_LMAC1_PD_NOTIFICATION 0xa0338c 397d9836fb4SBjoern A. Zeeb #define WFPM_ARC1_PD_NOTIFICATION 0xa03044 398d9836fb4SBjoern A. Zeeb #define HPM_SECONDARY_DEVICE_STATE 0xa03404 3999af1bba4SBjoern A. Zeeb #define WFPM_MAC_OTP_CFG7_ADDR 0xa03338 4009af1bba4SBjoern A. Zeeb #define WFPM_MAC_OTP_CFG7_DATA 0xa0333c 401d9836fb4SBjoern A. Zeeb 402d9836fb4SBjoern A. Zeeb 403bfcc09ddSBjoern A. Zeeb /* For UMAG_GEN_HW_STATUS reg check */ 404bfcc09ddSBjoern A. Zeeb enum { 405bfcc09ddSBjoern A. Zeeb UMAG_GEN_HW_IS_FPGA = BIT(1), 406bfcc09ddSBjoern A. Zeeb }; 407bfcc09ddSBjoern A. Zeeb 408bfcc09ddSBjoern A. Zeeb /* FW chicken bits */ 409bfcc09ddSBjoern A. Zeeb #define LMPM_CHICK 0xA01FF8 410bfcc09ddSBjoern A. Zeeb enum { 411bfcc09ddSBjoern A. Zeeb LMPM_CHICK_EXTENDED_ADDR_SPACE = BIT(0), 412bfcc09ddSBjoern A. Zeeb }; 413bfcc09ddSBjoern A. Zeeb 414bfcc09ddSBjoern A. Zeeb /* FW chicken bits */ 415bfcc09ddSBjoern A. Zeeb #define LMPM_PAGE_PASS_NOTIF 0xA03824 416bfcc09ddSBjoern A. Zeeb enum { 417bfcc09ddSBjoern A. Zeeb LMPM_PAGE_PASS_NOTIF_POS = BIT(20), 418bfcc09ddSBjoern A. Zeeb }; 419bfcc09ddSBjoern A. Zeeb 420bfcc09ddSBjoern A. Zeeb /* 421bfcc09ddSBjoern A. Zeeb * CRF ID register 422bfcc09ddSBjoern A. Zeeb * 423bfcc09ddSBjoern A. Zeeb * type: bits 0-11 424bfcc09ddSBjoern A. Zeeb * reserved: bits 12-18 425bfcc09ddSBjoern A. Zeeb * slave_exist: bit 19 426bfcc09ddSBjoern A. Zeeb * dash: bits 20-23 427bfcc09ddSBjoern A. Zeeb * step: bits 24-26 428bfcc09ddSBjoern A. Zeeb * flavor: bits 27-31 429bfcc09ddSBjoern A. Zeeb */ 430bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE(val) (((val) & 0x00000FFF) >> 0) 431bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_SLAVE(val) (((val) & 0x00080000) >> 19) 432bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_DASH(val) (((val) & 0x00F00000) >> 20) 433bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_STEP(val) (((val) & 0x07000000) >> 24) 434bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_FLAVOR(val) (((val) & 0xF8000000) >> 27) 435bfcc09ddSBjoern A. Zeeb 436bfcc09ddSBjoern A. Zeeb #define UREG_CHICK (0xA05C00) 437bfcc09ddSBjoern A. Zeeb #define UREG_CHICK_MSI_ENABLE BIT(24) 438bfcc09ddSBjoern A. Zeeb #define UREG_CHICK_MSIX_ENABLE BIT(25) 439bfcc09ddSBjoern A. Zeeb 440bfcc09ddSBjoern A. Zeeb #define SD_REG_VER 0xa29600 441bfcc09ddSBjoern A. Zeeb #define SD_REG_VER_GEN2 0x00a2b800 442bfcc09ddSBjoern A. Zeeb 443bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_JF_1 0x201 444bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_JF_2 0x202 445bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_HR_CDB 0x503 446bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_HR_NONE_CDB 0x504 447bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_HR_NONE_CDB_1X1 0x501 448bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_HR_NONE_CDB_CCP 0x532 449bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_GF 0x410 450bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_GF_TC 0xF08 451bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_MR 0x810 452bfcc09ddSBjoern A. Zeeb #define REG_CRF_ID_TYPE_FM 0x910 4539af1bba4SBjoern A. Zeeb #define REG_CRF_ID_TYPE_FMI 0x930 4549af1bba4SBjoern A. Zeeb #define REG_CRF_ID_TYPE_FMR 0x900 455bfcc09ddSBjoern A. Zeeb 456bfcc09ddSBjoern A. Zeeb #define HPM_DEBUG 0xA03440 457bfcc09ddSBjoern A. Zeeb #define PERSISTENCE_BIT BIT(12) 458bfcc09ddSBjoern A. Zeeb #define PREG_WFPM_ACCESS BIT(12) 459bfcc09ddSBjoern A. Zeeb 460bfcc09ddSBjoern A. Zeeb #define HPM_HIPM_GEN_CFG 0xA03458 461bfcc09ddSBjoern A. Zeeb #define HPM_HIPM_GEN_CFG_CR_PG_EN BIT(0) 462bfcc09ddSBjoern A. Zeeb #define HPM_HIPM_GEN_CFG_CR_SLP_EN BIT(1) 463bfcc09ddSBjoern A. Zeeb #define HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE BIT(10) 464bfcc09ddSBjoern A. Zeeb 465bfcc09ddSBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6 0xA05C04 466bfcc09ddSBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6_NMI_BIT BIT(0) 467bfcc09ddSBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6_RESET_HANDSHAKE (BIT(0) | BIT(1)) 468bfcc09ddSBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6_SUSPEND BIT(18) 469bfcc09ddSBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6_RESUME BIT(19) 470bfcc09ddSBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6_PNVM BIT(20) 471bfcc09ddSBjoern A. Zeeb 472d9836fb4SBjoern A. Zeeb /* 473d9836fb4SBjoern A. Zeeb * From BZ family driver triggers this bit for suspend and resume 474d9836fb4SBjoern A. Zeeb * The driver should update CSR_IPC_SLEEP_CONTROL before triggering 475d9836fb4SBjoern A. Zeeb * this interrupt with suspend/resume value 476d9836fb4SBjoern A. Zeeb */ 477d9836fb4SBjoern A. Zeeb #define UREG_DOORBELL_TO_ISR6_SLEEP_CTRL BIT(31) 478d9836fb4SBjoern A. Zeeb 479bfcc09ddSBjoern A. Zeeb #define CNVI_MBOX_C 0xA3400C 480bfcc09ddSBjoern A. Zeeb 481bfcc09ddSBjoern A. Zeeb #define FSEQ_ERROR_CODE 0xA340C8 482bfcc09ddSBjoern A. Zeeb #define FSEQ_TOP_INIT_VERSION 0xA34038 483bfcc09ddSBjoern A. Zeeb #define FSEQ_CNVIO_INIT_VERSION 0xA3403C 484bfcc09ddSBjoern A. Zeeb #define FSEQ_OTP_VERSION 0xA340FC 485bfcc09ddSBjoern A. Zeeb #define FSEQ_TOP_CONTENT_VERSION 0xA340F4 486bfcc09ddSBjoern A. Zeeb #define FSEQ_ALIVE_TOKEN 0xA340F0 487bfcc09ddSBjoern A. Zeeb #define FSEQ_CNVI_ID 0xA3408C 488bfcc09ddSBjoern A. Zeeb #define FSEQ_CNVR_ID 0xA34090 4899af1bba4SBjoern A. Zeeb #define FSEQ_PREV_CNVIO_INIT_VERSION 0xA34084 4909af1bba4SBjoern A. Zeeb #define FSEQ_WIFI_FSEQ_VERSION 0xA34040 4919af1bba4SBjoern A. Zeeb #define FSEQ_BT_FSEQ_VERSION 0xA34044 4929af1bba4SBjoern A. Zeeb #define FSEQ_CLASS_TP_VERSION 0xA34078 493bfcc09ddSBjoern A. Zeeb 494bfcc09ddSBjoern A. Zeeb #define IWL_D3_SLEEP_STATUS_SUSPEND 0xD3 495bfcc09ddSBjoern A. Zeeb #define IWL_D3_SLEEP_STATUS_RESUME 0xD0 496bfcc09ddSBjoern A. Zeeb 497bfcc09ddSBjoern A. Zeeb #define WMAL_INDRCT_RD_CMD1_OPMOD_POS 28 498bfcc09ddSBjoern A. Zeeb #define WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK 0xFFFFF 499bfcc09ddSBjoern A. Zeeb #define WMAL_CMD_READ_BURST_ACCESS 2 500bfcc09ddSBjoern A. Zeeb #define WMAL_MRSPF_1 0xADFC20 501bfcc09ddSBjoern A. Zeeb #define WMAL_INDRCT_RD_CMD1 0xADFD44 502bfcc09ddSBjoern A. Zeeb #define WMAL_INDRCT_CMD1 0xADFC14 503bfcc09ddSBjoern A. Zeeb #define WMAL_INDRCT_CMD(addr) \ 504bfcc09ddSBjoern A. Zeeb ((WMAL_CMD_READ_BURST_ACCESS << WMAL_INDRCT_RD_CMD1_OPMOD_POS) | \ 505bfcc09ddSBjoern A. Zeeb ((addr) & WMAL_INDRCT_RD_CMD1_BYTE_ADDRESS_MSK)) 506bfcc09ddSBjoern A. Zeeb 507bfcc09ddSBjoern A. Zeeb #define WFPM_LMAC1_PS_CTL_RW 0xA03380 508bfcc09ddSBjoern A. Zeeb #define WFPM_LMAC2_PS_CTL_RW 0xA033C0 509bfcc09ddSBjoern A. Zeeb #define WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK 0x0000000F 510bfcc09ddSBjoern A. Zeeb #define WFPM_PHYRF_STATE_ON 5 511bfcc09ddSBjoern A. Zeeb #define HBUS_TIMEOUT 0xA5A5A5A1 512bfcc09ddSBjoern A. Zeeb #define WFPM_DPHY_OFF 0xDF10FF 513bfcc09ddSBjoern A. Zeeb 514d9836fb4SBjoern A. Zeeb #define REG_OTP_MINOR 0xA0333C 515d9836fb4SBjoern A. Zeeb 5169af1bba4SBjoern A. Zeeb #define WFPM_LMAC2_PD_NOTIFICATION 0xA033CC 5179af1bba4SBjoern A. Zeeb #define WFPM_LMAC2_PD_RE_READ BIT(31) 5189af1bba4SBjoern A. Zeeb 519bfcc09ddSBjoern A. Zeeb #endif /* __iwl_prph_h__ */ 520