16c92544dSBjoern A. Zeeb // SPDX-License-Identifier: ISC
26c92544dSBjoern A. Zeeb /*
36c92544dSBjoern A. Zeeb * Copyright (C) 2016 Felix Fietkau <nbd@nbd.name>
46c92544dSBjoern A. Zeeb * Copyright (C) 2018 Lorenzo Bianconi <lorenzo.bianconi83@gmail.com>
56c92544dSBjoern A. Zeeb */
66c92544dSBjoern A. Zeeb
76c92544dSBjoern A. Zeeb #include "mt76x2.h"
86c92544dSBjoern A. Zeeb #include "eeprom.h"
96c92544dSBjoern A. Zeeb #include "../mt76x02_phy.h"
106c92544dSBjoern A. Zeeb
mt76x2_set_sar_specs(struct ieee80211_hw * hw,const struct cfg80211_sar_specs * sar)116c92544dSBjoern A. Zeeb int mt76x2_set_sar_specs(struct ieee80211_hw *hw,
126c92544dSBjoern A. Zeeb const struct cfg80211_sar_specs *sar)
136c92544dSBjoern A. Zeeb {
146c92544dSBjoern A. Zeeb int err = -EINVAL, power = hw->conf.power_level * 2;
156c92544dSBjoern A. Zeeb struct mt76x02_dev *dev = hw->priv;
166c92544dSBjoern A. Zeeb struct mt76_phy *mphy = &dev->mphy;
176c92544dSBjoern A. Zeeb
186c92544dSBjoern A. Zeeb mutex_lock(&dev->mt76.mutex);
196c92544dSBjoern A. Zeeb if (!cfg80211_chandef_valid(&mphy->chandef))
206c92544dSBjoern A. Zeeb goto out;
216c92544dSBjoern A. Zeeb
226c92544dSBjoern A. Zeeb err = mt76_init_sar_power(hw, sar);
236c92544dSBjoern A. Zeeb if (err)
246c92544dSBjoern A. Zeeb goto out;
256c92544dSBjoern A. Zeeb
266c92544dSBjoern A. Zeeb dev->txpower_conf = mt76_get_sar_power(mphy, mphy->chandef.chan,
276c92544dSBjoern A. Zeeb power);
286c92544dSBjoern A. Zeeb /* convert to per-chain power for 2x2 devices */
296c92544dSBjoern A. Zeeb dev->txpower_conf -= 6;
306c92544dSBjoern A. Zeeb
316c92544dSBjoern A. Zeeb if (test_bit(MT76_STATE_RUNNING, &mphy->state))
326c92544dSBjoern A. Zeeb mt76x2_phy_set_txpower(dev);
336c92544dSBjoern A. Zeeb out:
346c92544dSBjoern A. Zeeb mutex_unlock(&dev->mt76.mutex);
356c92544dSBjoern A. Zeeb
366c92544dSBjoern A. Zeeb return err;
376c92544dSBjoern A. Zeeb }
386c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x2_set_sar_specs);
396c92544dSBjoern A. Zeeb
406c92544dSBjoern A. Zeeb static void
mt76x2_set_wlan_state(struct mt76x02_dev * dev,bool enable)416c92544dSBjoern A. Zeeb mt76x2_set_wlan_state(struct mt76x02_dev *dev, bool enable)
426c92544dSBjoern A. Zeeb {
436c92544dSBjoern A. Zeeb u32 val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
446c92544dSBjoern A. Zeeb
456c92544dSBjoern A. Zeeb if (enable)
466c92544dSBjoern A. Zeeb val |= (MT_WLAN_FUN_CTRL_WLAN_EN |
476c92544dSBjoern A. Zeeb MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
486c92544dSBjoern A. Zeeb else
496c92544dSBjoern A. Zeeb val &= ~(MT_WLAN_FUN_CTRL_WLAN_EN |
506c92544dSBjoern A. Zeeb MT_WLAN_FUN_CTRL_WLAN_CLK_EN);
516c92544dSBjoern A. Zeeb
526c92544dSBjoern A. Zeeb mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
536c92544dSBjoern A. Zeeb udelay(20);
546c92544dSBjoern A. Zeeb }
556c92544dSBjoern A. Zeeb
mt76x2_reset_wlan(struct mt76x02_dev * dev,bool enable)566c92544dSBjoern A. Zeeb void mt76x2_reset_wlan(struct mt76x02_dev *dev, bool enable)
576c92544dSBjoern A. Zeeb {
586c92544dSBjoern A. Zeeb u32 val;
596c92544dSBjoern A. Zeeb
606c92544dSBjoern A. Zeeb if (!enable)
616c92544dSBjoern A. Zeeb goto out;
626c92544dSBjoern A. Zeeb
636c92544dSBjoern A. Zeeb val = mt76_rr(dev, MT_WLAN_FUN_CTRL);
646c92544dSBjoern A. Zeeb
656c92544dSBjoern A. Zeeb val &= ~MT_WLAN_FUN_CTRL_FRC_WL_ANT_SEL;
666c92544dSBjoern A. Zeeb
676c92544dSBjoern A. Zeeb if (val & MT_WLAN_FUN_CTRL_WLAN_EN) {
686c92544dSBjoern A. Zeeb val |= MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
696c92544dSBjoern A. Zeeb mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
706c92544dSBjoern A. Zeeb udelay(20);
716c92544dSBjoern A. Zeeb
726c92544dSBjoern A. Zeeb val &= ~MT_WLAN_FUN_CTRL_WLAN_RESET_RF;
736c92544dSBjoern A. Zeeb }
746c92544dSBjoern A. Zeeb
756c92544dSBjoern A. Zeeb mt76_wr(dev, MT_WLAN_FUN_CTRL, val);
766c92544dSBjoern A. Zeeb udelay(20);
776c92544dSBjoern A. Zeeb
786c92544dSBjoern A. Zeeb out:
796c92544dSBjoern A. Zeeb mt76x2_set_wlan_state(dev, enable);
806c92544dSBjoern A. Zeeb }
816c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x2_reset_wlan);
826c92544dSBjoern A. Zeeb
mt76_write_mac_initvals(struct mt76x02_dev * dev)836c92544dSBjoern A. Zeeb void mt76_write_mac_initvals(struct mt76x02_dev *dev)
846c92544dSBjoern A. Zeeb {
856c92544dSBjoern A. Zeeb #define DEFAULT_PROT_CFG_CCK \
866c92544dSBjoern A. Zeeb (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \
876c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
886c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
896c92544dSBjoern A. Zeeb MT_PROT_CFG_RTS_THRESH)
906c92544dSBjoern A. Zeeb
916c92544dSBjoern A. Zeeb #define DEFAULT_PROT_CFG_OFDM \
926c92544dSBjoern A. Zeeb (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
936c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
946c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \
956c92544dSBjoern A. Zeeb MT_PROT_CFG_RTS_THRESH)
966c92544dSBjoern A. Zeeb
976c92544dSBjoern A. Zeeb #define DEFAULT_PROT_CFG_20 \
986c92544dSBjoern A. Zeeb (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \
996c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
1006c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
1016c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17))
1026c92544dSBjoern A. Zeeb
1036c92544dSBjoern A. Zeeb #define DEFAULT_PROT_CFG_40 \
1046c92544dSBjoern A. Zeeb (FIELD_PREP(MT_PROT_CFG_RATE, 0x2084) | \
1056c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \
1066c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_NAV, 1) | \
1076c92544dSBjoern A. Zeeb FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f))
1086c92544dSBjoern A. Zeeb
1096c92544dSBjoern A. Zeeb static const struct mt76_reg_pair vals[] = {
1106c92544dSBjoern A. Zeeb /* Copied from MediaTek reference source */
1116c92544dSBjoern A. Zeeb { MT_PBF_SYS_CTRL, 0x00080c00 },
1126c92544dSBjoern A. Zeeb { MT_PBF_CFG, 0x1efebcff },
1136c92544dSBjoern A. Zeeb { MT_FCE_PSE_CTRL, 0x00000001 },
1146c92544dSBjoern A. Zeeb { MT_MAC_SYS_CTRL, 0x00000000 },
1156c92544dSBjoern A. Zeeb { MT_MAX_LEN_CFG, 0x003e3f00 },
1166c92544dSBjoern A. Zeeb { MT_AMPDU_MAX_LEN_20M1S, 0xaaa99887 },
1176c92544dSBjoern A. Zeeb { MT_AMPDU_MAX_LEN_20M2S, 0x000000aa },
1186c92544dSBjoern A. Zeeb { MT_XIFS_TIME_CFG, 0x33a40d0a },
1196c92544dSBjoern A. Zeeb { MT_BKOFF_SLOT_CFG, 0x00000209 },
1206c92544dSBjoern A. Zeeb { MT_TBTT_SYNC_CFG, 0x00422010 },
1216c92544dSBjoern A. Zeeb { MT_PWR_PIN_CFG, 0x00000000 },
1226c92544dSBjoern A. Zeeb { 0x1238, 0x001700c8 },
1236c92544dSBjoern A. Zeeb { MT_TX_SW_CFG0, 0x00101001 },
1246c92544dSBjoern A. Zeeb { MT_TX_SW_CFG1, 0x00010000 },
1256c92544dSBjoern A. Zeeb { MT_TX_SW_CFG2, 0x00000000 },
1266c92544dSBjoern A. Zeeb { MT_TXOP_CTRL_CFG, 0x0400583f },
1276c92544dSBjoern A. Zeeb { MT_TX_RTS_CFG, 0x00ffff20 },
1286c92544dSBjoern A. Zeeb { MT_TX_TIMEOUT_CFG, 0x000a2290 },
1296c92544dSBjoern A. Zeeb { MT_TX_RETRY_CFG, 0x47f01f0f },
1306c92544dSBjoern A. Zeeb { MT_EXP_ACK_TIME, 0x002c00dc },
1316c92544dSBjoern A. Zeeb { MT_TX_PROT_CFG6, 0xe3f42004 },
1326c92544dSBjoern A. Zeeb { MT_TX_PROT_CFG7, 0xe3f42084 },
1336c92544dSBjoern A. Zeeb { MT_TX_PROT_CFG8, 0xe3f42104 },
1346c92544dSBjoern A. Zeeb { MT_PIFS_TX_CFG, 0x00060fff },
1356c92544dSBjoern A. Zeeb { MT_RX_FILTR_CFG, 0x00015f97 },
1366c92544dSBjoern A. Zeeb { MT_LEGACY_BASIC_RATE, 0x0000017f },
1376c92544dSBjoern A. Zeeb { MT_HT_BASIC_RATE, 0x00004003 },
1386c92544dSBjoern A. Zeeb { MT_PN_PAD_MODE, 0x00000003 },
1396c92544dSBjoern A. Zeeb { MT_TXOP_HLDR_ET, 0x00000002 },
1406c92544dSBjoern A. Zeeb { 0xa44, 0x00000000 },
1416c92544dSBjoern A. Zeeb { MT_HEADER_TRANS_CTRL_REG, 0x00000000 },
1426c92544dSBjoern A. Zeeb { MT_TSO_CTRL, 0x00000000 },
1436c92544dSBjoern A. Zeeb { MT_AUX_CLK_CFG, 0x00000000 },
1446c92544dSBjoern A. Zeeb { MT_DACCLK_EN_DLY_CFG, 0x00000000 },
1456c92544dSBjoern A. Zeeb { MT_TX_ALC_CFG_4, 0x00000000 },
1466c92544dSBjoern A. Zeeb { MT_TX_ALC_VGA3, 0x00000000 },
1476c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_0, 0x3a3a3a3a },
1486c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_1, 0x3a3a3a3a },
1496c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_2, 0x3a3a3a3a },
1506c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_3, 0x3a3a3a3a },
1516c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_4, 0x3a3a3a3a },
1526c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_7, 0x3a3a3a3a },
1536c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_8, 0x0000003a },
1546c92544dSBjoern A. Zeeb { MT_TX_PWR_CFG_9, 0x0000003a },
1556c92544dSBjoern A. Zeeb { MT_EFUSE_CTRL, 0x0000d000 },
1566c92544dSBjoern A. Zeeb { MT_PAUSE_ENABLE_CONTROL1, 0x0000000a },
1576c92544dSBjoern A. Zeeb { MT_FCE_WLAN_FLOW_CONTROL1, 0x60401c18 },
1586c92544dSBjoern A. Zeeb { MT_WPDMA_DELAY_INT_CFG, 0x94ff0000 },
1596c92544dSBjoern A. Zeeb { MT_TX_SW_CFG3, 0x00000004 },
1606c92544dSBjoern A. Zeeb { MT_HT_FBK_TO_LEGACY, 0x00001818 },
1616c92544dSBjoern A. Zeeb { MT_VHT_HT_FBK_CFG1, 0xedcba980 },
1626c92544dSBjoern A. Zeeb { MT_PROT_AUTO_TX_CFG, 0x00830083 },
1636c92544dSBjoern A. Zeeb { MT_HT_CTRL_CFG, 0x000001ff },
1646c92544dSBjoern A. Zeeb { MT_TX_LINK_CFG, 0x00001020 },
1656c92544dSBjoern A. Zeeb };
1666c92544dSBjoern A. Zeeb struct mt76_reg_pair prot_vals[] = {
1676c92544dSBjoern A. Zeeb { MT_CCK_PROT_CFG, DEFAULT_PROT_CFG_CCK },
1686c92544dSBjoern A. Zeeb { MT_OFDM_PROT_CFG, DEFAULT_PROT_CFG_OFDM },
1696c92544dSBjoern A. Zeeb { MT_MM20_PROT_CFG, DEFAULT_PROT_CFG_20 },
1706c92544dSBjoern A. Zeeb { MT_MM40_PROT_CFG, DEFAULT_PROT_CFG_40 },
1716c92544dSBjoern A. Zeeb { MT_GF20_PROT_CFG, DEFAULT_PROT_CFG_20 },
1726c92544dSBjoern A. Zeeb { MT_GF40_PROT_CFG, DEFAULT_PROT_CFG_40 },
1736c92544dSBjoern A. Zeeb };
1746c92544dSBjoern A. Zeeb
1756c92544dSBjoern A. Zeeb mt76_wr_rp(dev, 0, vals, ARRAY_SIZE(vals));
1766c92544dSBjoern A. Zeeb mt76_wr_rp(dev, 0, prot_vals, ARRAY_SIZE(prot_vals));
1776c92544dSBjoern A. Zeeb }
1786c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76_write_mac_initvals);
1796c92544dSBjoern A. Zeeb
mt76x2_init_txpower(struct mt76x02_dev * dev,struct ieee80211_supported_band * sband)1806c92544dSBjoern A. Zeeb void mt76x2_init_txpower(struct mt76x02_dev *dev,
1816c92544dSBjoern A. Zeeb struct ieee80211_supported_band *sband)
1826c92544dSBjoern A. Zeeb {
1836c92544dSBjoern A. Zeeb struct ieee80211_channel *chan;
1846c92544dSBjoern A. Zeeb struct mt76x2_tx_power_info txp;
185cbb3ec25SBjoern A. Zeeb struct mt76x02_rate_power t = {};
1866c92544dSBjoern A. Zeeb int i;
1876c92544dSBjoern A. Zeeb
1886c92544dSBjoern A. Zeeb for (i = 0; i < sband->n_channels; i++) {
1896c92544dSBjoern A. Zeeb chan = &sband->channels[i];
1906c92544dSBjoern A. Zeeb
1916c92544dSBjoern A. Zeeb mt76x2_get_power_info(dev, &txp, chan);
1926c92544dSBjoern A. Zeeb mt76x2_get_rate_power(dev, &t, chan);
1936c92544dSBjoern A. Zeeb
1946c92544dSBjoern A. Zeeb chan->orig_mpwr = mt76x02_get_max_rate_power(&t) +
1956c92544dSBjoern A. Zeeb txp.target_power;
1966c92544dSBjoern A. Zeeb chan->orig_mpwr = DIV_ROUND_UP(chan->orig_mpwr, 2);
1976c92544dSBjoern A. Zeeb
1986c92544dSBjoern A. Zeeb /* convert to combined output power on 2x2 devices */
1996c92544dSBjoern A. Zeeb chan->orig_mpwr += 3;
2006c92544dSBjoern A. Zeeb chan->max_power = min_t(int, chan->max_reg_power,
2016c92544dSBjoern A. Zeeb chan->orig_mpwr);
2026c92544dSBjoern A. Zeeb }
2036c92544dSBjoern A. Zeeb }
2046c92544dSBjoern A. Zeeb EXPORT_SYMBOL_GPL(mt76x2_init_txpower);
205