1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2 /* Copyright(c) 2018-2019 Realtek Corporation 3 */ 4 5 #ifndef __RTW8822B_H__ 6 #define __RTW8822B_H__ 7 8 #include <asm/byteorder.h> 9 10 #define RCR_VHT_ACK BIT(26) 11 12 struct rtw8822bu_efuse { 13 u8 res4[4]; /* 0xd0 */ 14 u8 usb_optional_function; 15 u8 res5[0x1e]; 16 u8 res6[2]; 17 u8 serial[0x0b]; /* 0xf5 */ 18 u8 vid; /* 0x100 */ 19 u8 res7; 20 u8 pid; 21 u8 res8[4]; 22 u8 mac_addr[ETH_ALEN]; /* 0x107 */ 23 u8 res9[2]; 24 u8 vendor_name[0x07]; 25 u8 res10[2]; 26 u8 device_name[0x14]; 27 u8 res11[0xcf]; 28 u8 package_type; /* 0x1fb */ 29 u8 res12[0x4]; 30 }; 31 32 struct rtw8822be_efuse { 33 u8 mac_addr[ETH_ALEN]; /* 0xd0 */ 34 u8 vender_id[2]; 35 u8 device_id[2]; 36 u8 sub_vender_id[2]; 37 u8 sub_device_id[2]; 38 u8 pmc[2]; 39 u8 exp_device_cap[2]; 40 u8 msi_cap; 41 u8 ltr_cap; /* 0xe3 */ 42 u8 exp_link_control[2]; 43 u8 link_cap[4]; 44 u8 link_control[2]; 45 u8 serial_number[8]; 46 u8 res0:2; /* 0xf4 */ 47 u8 ltr_en:1; 48 u8 res1:2; 49 u8 obff:2; 50 u8 res2:3; 51 u8 obff_cap:2; 52 u8 res3:4; 53 u8 res4[3]; 54 u8 class_code[3]; 55 u8 pci_pm_L1_2_supp:1; 56 u8 pci_pm_L1_1_supp:1; 57 u8 aspm_pm_L1_2_supp:1; 58 u8 aspm_pm_L1_1_supp:1; 59 u8 L1_pm_substates_supp:1; 60 u8 res5:3; 61 u8 port_common_mode_restore_time; 62 u8 port_t_power_on_scale:2; 63 u8 res6:1; 64 u8 port_t_power_on_value:5; 65 u8 res7; 66 }; 67 68 struct rtw8822b_efuse { 69 __le16 rtl_id; 70 u8 res0[0x0e]; 71 72 /* power index for four RF paths */ 73 struct rtw_txpwr_idx txpwr_idx_table[4]; 74 75 u8 channel_plan; /* 0xb8 */ 76 u8 xtal_k; 77 u8 thermal_meter; 78 u8 iqk_lck; 79 u8 pa_type; /* 0xbc */ 80 u8 lna_type_2g[2]; /* 0xbd */ 81 u8 lna_type_5g[2]; 82 u8 rf_board_option; 83 u8 rf_feature_option; 84 u8 rf_bt_setting; 85 u8 eeprom_version; 86 u8 eeprom_customer_id; 87 u8 tx_bb_swing_setting_2g; 88 u8 tx_bb_swing_setting_5g; 89 u8 tx_pwr_calibrate_rate; 90 u8 rf_antenna_option; /* 0xc9 */ 91 u8 rfe_option; 92 u8 country_code[2]; 93 u8 res[3]; 94 union { 95 struct rtw8822bu_efuse u; 96 struct rtw8822be_efuse e; 97 }; 98 }; 99 100 static inline void 101 _rtw_write32s_mask(struct rtw_dev *rtwdev, u32 addr, u32 mask, u32 data) 102 { 103 /* 0xC00-0xCFF and 0xE00-0xEFF have the same layout */ 104 rtw_write32_mask(rtwdev, addr, mask, data); 105 rtw_write32_mask(rtwdev, addr + 0x200, mask, data); 106 } 107 108 #define rtw_write32s_mask(rtwdev, addr, mask, data) \ 109 do { \ 110 BUILD_BUG_ON((addr) < 0xC00 || (addr) >= 0xD00); \ 111 \ 112 _rtw_write32s_mask(rtwdev, addr, mask, data); \ 113 } while (0) 114 115 /* phy status page0 */ 116 #define GET_PHY_STAT_P0_PWDB(phy_stat) \ 117 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 118 119 /* phy status page1 */ 120 #define GET_PHY_STAT_P1_PWDB_A(phy_stat) \ 121 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(15, 8)) 122 #define GET_PHY_STAT_P1_PWDB_B(phy_stat) \ 123 le32_get_bits(*((__le32 *)(phy_stat) + 0x00), GENMASK(23, 16)) 124 #define GET_PHY_STAT_P1_RF_MODE(phy_stat) \ 125 le32_get_bits(*((__le32 *)(phy_stat) + 0x03), GENMASK(29, 28)) 126 #define GET_PHY_STAT_P1_L_RXSC(phy_stat) \ 127 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(11, 8)) 128 #define GET_PHY_STAT_P1_HT_RXSC(phy_stat) \ 129 le32_get_bits(*((__le32 *)(phy_stat) + 0x01), GENMASK(15, 12)) 130 #define GET_PHY_STAT_P1_RXEVM_A(phy_stat) \ 131 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(7, 0)) 132 #define GET_PHY_STAT_P1_RXEVM_B(phy_stat) \ 133 le32_get_bits(*((__le32 *)(phy_stat) + 0x04), GENMASK(15, 8)) 134 #define GET_PHY_STAT_P1_CFO_TAIL_A(phy_stat) \ 135 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(7, 0)) 136 #define GET_PHY_STAT_P1_CFO_TAIL_B(phy_stat) \ 137 le32_get_bits(*((__le32 *)(phy_stat) + 0x05), GENMASK(15, 8)) 138 #define GET_PHY_STAT_P1_RXSNR_A(phy_stat) \ 139 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(7, 0)) 140 #define GET_PHY_STAT_P1_RXSNR_B(phy_stat) \ 141 le32_get_bits(*((__le32 *)(phy_stat) + 0x06), GENMASK(15, 8)) 142 143 #define RTW8822B_EDCCA_MAX 0x7f 144 #define RTW8822B_EDCCA_SRC_DEF 1 145 #define REG_HTSTFWT 0x800 146 #define REG_RXPSEL 0x808 147 #define BIT_RX_PSEL_RST (BIT(28) | BIT(29)) 148 #define REG_TXPSEL 0x80c 149 #define REG_RXCCAMSK 0x814 150 #define REG_CCASEL 0x82c 151 #define REG_PDMFTH 0x830 152 #define REG_CCA2ND 0x838 153 #define REG_L1WT 0x83c 154 #define REG_L1PKWT 0x840 155 #define REG_MRC 0x850 156 #define REG_CLKTRK 0x860 157 #define REG_EDCCA_POW_MA 0x8a0 158 #define BIT_MA_LEVEL GENMASK(1, 0) 159 #define REG_ADCCLK 0x8ac 160 #define REG_ADC160 0x8c4 161 #define REG_ADC40 0x8c8 162 #define REG_EDCCA_DECISION 0x8dc 163 #define BIT_EDCCA_OPTION BIT(5) 164 #define REG_CDDTXP 0x93c 165 #define REG_TXPSEL1 0x940 166 #define REG_EDCCA_SOURCE 0x944 167 #define BIT_SOURCE_OPTION GENMASK(29, 28) 168 #define REG_ACBB0 0x948 169 #define REG_ACBBRXFIR 0x94c 170 #define REG_ACGG2TBL 0x958 171 #define REG_RXSB 0xa00 172 #define REG_ADCINI 0xa04 173 #define REG_TXSF2 0xa24 174 #define REG_TXSF6 0xa28 175 #define REG_RXDESC 0xa2c 176 #define REG_ENTXCCK 0xa80 177 #define REG_AGCTR_A 0xc08 178 #define REG_TXDFIR 0xc20 179 #define REG_RXIGI_A 0xc50 180 #define REG_TRSW 0xca0 181 #define REG_RFESEL0 0xcb0 182 #define REG_RFESEL8 0xcb4 183 #define REG_RFECTL 0xcb8 184 #define REG_RFEINV 0xcbc 185 #define REG_AGCTR_B 0xe08 186 #define REG_RXIGI_B 0xe50 187 #define REG_ANTWT 0x1904 188 #define REG_IQKFAILMSK 0x1bf0 189 190 #endif 191