1Device State Configuration Registers
2------------------------------------
3
4TI C6X SoCs contain a region of miscellaneous registers which provide various
5function for SoC control or status. Details vary considerably among from SoC
6to SoC with no two being alike.
7
8In general, the Device State Configuration Registers (DSCR) will provide one or
9more configuration registers often protected by a lock register where one or
10more key values must be written to a lock register in order to unlock the
11configuration register for writes. These configuration register may be used to
12enable (and disable in some cases) SoC pin drivers, select peripheral clock
13sources (internal or pin), etc. In some cases, a configuration register is
14write once or the individual bits are write once. In addition to device config,
15the DSCR block may provide registers which are used to reset peripherals,
16provide device ID information, provide ethernet MAC addresses, as well as other
17miscellaneous functions.
18
19For device state control (enable/disable), each device control is assigned an
20id which is used by individual device drivers to control the state as needed.
21
22Required properties:
23
24- compatible: must be "ti,c64x+dscr"
25- reg: register area base and size
26
27Optional properties:
28
29  NOTE: These are optional in that not all SoCs will have all properties. For
30        SoCs which do support a given property, leaving the property out of the
31        device tree will result in reduced functionality or possibly driver
32        failure.
33
34- ti,dscr-devstat
35    offset of the devstat register
36
37- ti,dscr-silicon-rev
38    offset, start bit, and bitsize of silicon revision field
39
40- ti,dscr-rmii-resets
41    offset and bitmask of RMII reset field. May have multiple tuples if more
42    than one ethernet port is available.
43
44- ti,dscr-locked-regs
45    possibly multiple tuples describing registers which are write protected by
46    a lock register. Each tuple consists of the register offset, lock register
47    offsset, and the key value used to unlock the register.
48
49- ti,dscr-kick-regs
50    offset and key values of two "kick" registers used to write protect other
51    registers in DSCR. On SoCs using kick registers, the first key must be
52    written to the first kick register and the second key must be written to
53    the second register before other registers in the area are write-enabled.
54
55- ti,dscr-mac-fuse-regs
56    MAC addresses are contained in two registers. Each element of a MAC address
57    is contained in a single byte. This property has two tuples. Each tuple has
58    a register offset and four cells representing bytes in the register from
59    most significant to least. The value of these four cells is the MAC byte
60    index (1-6) of the byte within the register. A value of 0 means the byte
61    is unused in the MAC address.
62
63- ti,dscr-devstate-ctl-regs
64    This property describes the bitfields used to control the state of devices.
65    Each tuple describes a range of identical bitfields used to control one or
66    more devices (one bitfield per device). The layout of each tuple is:
67
68        start_id num_ids reg enable disable start_bit nbits
69
70    Where:
71        start_id is device id for the first device control in the range
72        num_ids is the number of device controls in the range
73        reg is the offset of the register holding the control bits
74        enable is the value to enable a device
75        disable is the value to disable a device (0xffffffff if cannot disable)
76        start_bit is the bit number of the first bit in the range
77        nbits is the number of bits per device control
78
79- ti,dscr-devstate-stat-regs
80    This property describes the bitfields used to provide device state status
81    for device states controlled by the DSCR. Each tuple describes a range of
82    identical bitfields used to provide status for one or more devices (one
83    bitfield per device). The layout of each tuple is:
84
85        start_id num_ids reg enable disable start_bit nbits
86
87    Where:
88        start_id is device id for the first device status in the range
89        num_ids is the number of devices covered by the range
90        reg is the offset of the register holding the status bits
91        enable is the value indicating device is enabled
92        disable is the value indicating device is disabled
93        start_bit is the bit number of the first bit in the range
94        nbits is the number of bits per device status
95
96- ti,dscr-privperm
97    Offset and default value for register used to set access privilege for
98    some SoC devices.
99
100
101Example:
102
103	device-state-config-regs@2a80000 {
104		compatible = "ti,c64x+dscr";
105		reg = <0x02a80000 0x41000>;
106
107		ti,dscr-devstat = <0>;
108		ti,dscr-silicon-rev = <8 28 0xf>;
109		ti,dscr-rmii-resets = <0x40020 0x00040000>;
110
111		ti,dscr-locked-regs = <0x40008 0x40004 0x0f0a0b00>;
112		ti,dscr-devstate-ctl-regs =
113			 <0 12 0x40008 1 0  0  2
114			  12 1 0x40008 3 0 30  2
115			  13 2 0x4002c 1 0xffffffff 0 1>;
116		ti,dscr-devstate-stat-regs =
117			<0 10 0x40014 1 0  0  3
118			 10 2 0x40018 1 0  0  3>;
119
120		ti,dscr-mac-fuse-regs = <0x700 1 2 3 4
121					 0x704 5 6 0 0>;
122
123		ti,dscr-privperm = <0x41c 0xaaaaaaaa>;
124
125		ti,dscr-kick-regs = <0x38 0x83E70B13
126				     0x3c 0x95A4F1E0>;
127	};
128