1--------------------------------------------------------------------------
2Device Tree Clock bindings for the Zynq Ultrascale+ MPSoC controlled using
3Zynq MPSoC firmware interface
4--------------------------------------------------------------------------
5The clock controller is a h/w block of Zynq Ultrascale+ MPSoC clock
6tree. It reads required input clock frequencies from the devicetree and acts
7as clock provider for all clock consumers of PS clocks.
8
9See clock_bindings.txt for more information on the generic clock bindings.
10
11Required properties:
12 - #clock-cells:	Must be 1
13 - compatible:		Must contain:	"xlnx,zynqmp-clk"
14 - clocks:		List of clock specifiers which are external input
15			clocks to the given clock controller. Please refer
16			the next section to find the input clocks for a
17			given controller.
18 - clock-names:		List of clock names which are exteral input clocks
19			to the given clock controller. Please refer to the
20			clock bindings for more details.
21
22Input clocks for zynqmp Ultrascale+ clock controller:
23
24The Zynq UltraScale+ MPSoC has one primary and four alternative reference clock
25inputs. These required clock inputs are:
26 - pss_ref_clk (PS reference clock)
27 - video_clk (reference clock for video system )
28 - pss_alt_ref_clk (alternative PS reference clock)
29 - aux_ref_clk
30 - gt_crx_ref_clk (transceiver reference clock)
31
32The following strings are optional parameters to the 'clock-names' property in
33order to provide an optional (E)MIO clock source:
34 - swdt0_ext_clk
35 - swdt1_ext_clk
36 - gem0_emio_clk
37 - gem1_emio_clk
38 - gem2_emio_clk
39 - gem3_emio_clk
40 - mio_clk_XX		# with XX = 00..77
41 - mio_clk_50_or_51	#for the mux clock to gem tsu from 50 or 51
42
43
44Output clocks are registered based on clock information received
45from firmware. Output clocks indexes are mentioned in
46include/dt-bindings/clock/xlnx-zynqmp-clk.h.
47
48-------
49Example
50-------
51
52firmware {
53	zynqmp_firmware: zynqmp-firmware {
54		compatible = "xlnx,zynqmp-firmware";
55		method = "smc";
56		zynqmp_clk: clock-controller {
57			#clock-cells = <1>;
58			compatible = "xlnx,zynqmp-clk";
59			clocks = <&pss_ref_clk>, <&video_clk>, <&pss_alt_ref_clk>, <&aux_ref_clk>, <&gt_crx_ref_clk>;
60			clock-names = "pss_ref_clk", "video_clk", "pss_alt_ref_clk","aux_ref_clk", "gt_crx_ref_clk";
61		};
62	};
63};
64