1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP i.MX System Controller Firmware (SCFW)
8
9maintainers:
10  - Dong Aisheng <aisheng.dong@nxp.com>
11
12description:
13  The System Controller Firmware (SCFW) is a low-level system function
14  which runs on a dedicated Cortex-M core to provide power, clock, and
15  resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
16  (QM, QP), and i.MX8QX (QXP, DX).
17  The AP communicates with the SC using a multi-ported MU module found
18  in the LSIO subsystem. The current definition of this MU module provides
19  5 remote AP connections to the SC to support up to 5 execution environments
20  (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
21  with the LSIO DSC IP bus. The SC firmware will communicate with this MU
22  using the MSI bus.
23
24properties:
25  compatible:
26    const: fsl,imx-scu
27
28  clock-controller:
29    description:
30      Clock controller node that provides the clocks controlled by the SCU
31    $ref: /schemas/clock/fsl,scu-clk.yaml
32
33  ocotp:
34    description:
35      OCOTP controller node provided by the SCU
36    $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
37
38  keys:
39    description:
40      Keys provided by the SCU
41    $ref: /schemas/input/fsl,scu-key.yaml
42
43  mboxes:
44    description:
45      A list of phandles of TX MU channels followed by a list of phandles of
46      RX MU channels. The list may include at the end one more optional MU
47      channel for general interrupt. The number of expected tx and rx
48      channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
49      compatible, 4 TX and 4 RX channels otherwise. All MU channels must be
50      within the same MU instance. Cross instances are not allowed. The MU
51      instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users
52      need to ensure that one is used that does not conflict with other
53      execution environments such as ATF.
54    oneOf:
55      - items:
56          - description: TX0 MU channel
57          - description: RX0 MU channel
58      - items:
59          - description: TX0 MU channel
60          - description: RX0 MU channel
61          - description: optional MU channel for general interrupt
62      - items:
63          - description: TX0 MU channel
64          - description: TX1 MU channel
65          - description: TX2 MU channel
66          - description: TX3 MU channel
67          - description: RX0 MU channel
68          - description: RX1 MU channel
69          - description: RX2 MU channel
70          - description: RX3 MU channel
71      - items:
72          - description: TX0 MU channel
73          - description: TX1 MU channel
74          - description: TX2 MU channel
75          - description: TX3 MU channel
76          - description: RX0 MU channel
77          - description: RX1 MU channel
78          - description: RX2 MU channel
79          - description: RX3 MU channel
80          - description: optional MU channel for general interrupt
81
82  mbox-names:
83    oneOf:
84      - items:
85          - const: tx0
86          - const: rx0
87      - items:
88          - const: tx0
89          - const: rx0
90          - const: gip3
91      - items:
92          - const: tx0
93          - const: tx1
94          - const: tx2
95          - const: tx3
96          - const: rx0
97          - const: rx1
98          - const: rx2
99          - const: rx3
100      - items:
101          - const: tx0
102          - const: tx1
103          - const: tx2
104          - const: tx3
105          - const: rx0
106          - const: rx1
107          - const: rx2
108          - const: rx3
109          - const: gip3
110
111  pinctrl:
112    description:
113      Pin controller provided by the SCU
114    $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
115
116  power-controller:
117    description:
118      Power domains controller node that provides the power domains
119      controlled by the SCU
120    $ref: /schemas/power/fsl,scu-pd.yaml
121
122  rtc:
123    description:
124      RTC controller provided by the SCU
125    $ref: /schemas/rtc/fsl,scu-rtc.yaml
126
127  thermal-sensor:
128    description:
129      Thermal sensor provided by the SCU
130    $ref: /schemas/thermal/fsl,scu-thermal.yaml
131
132  watchdog:
133    description:
134      Watchdog controller provided by the SCU
135    $ref: /schemas/watchdog/fsl,scu-wdt.yaml
136
137required:
138  - compatible
139  - mbox-names
140  - mboxes
141
142additionalProperties: false
143
144examples:
145  - |
146    #include <dt-bindings/firmware/imx/rsrc.h>
147    #include <dt-bindings/input/input.h>
148    #include <dt-bindings/pinctrl/pads-imx8qxp.h>
149
150    firmware {
151        system-controller {
152            compatible = "fsl,imx-scu";
153            mbox-names = "tx0", "tx1", "tx2", "tx3",
154                         "rx0", "rx1", "rx2", "rx3",
155                         "gip3";
156            mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
157                      &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
158                      &lsio_mu1 3 3>;
159
160            clock-controller {
161                compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
162                #clock-cells = <2>;
163            };
164
165            pinctrl {
166                compatible = "fsl,imx8qxp-iomuxc";
167
168                pinctrl_lpuart0: lpuart0grp {
169                    fsl,pins = <
170                        IMX8QXP_UART0_RX_ADMA_UART0_RX   0x06000020
171                        IMX8QXP_UART0_TX_ADMA_UART0_TX   0x06000020
172                    >;
173                };
174            };
175
176            ocotp {
177                compatible = "fsl,imx8qxp-scu-ocotp";
178                #address-cells = <1>;
179                #size-cells = <1>;
180
181                fec_mac0: mac@2c4 {
182                    reg = <0x2c4 6>;
183                };
184            };
185
186            power-controller {
187                compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
188                #power-domain-cells = <1>;
189            };
190
191            rtc {
192                compatible = "fsl,imx8qxp-sc-rtc";
193            };
194
195            keys {
196                compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
197                linux,keycodes = <KEY_POWER>;
198            };
199
200            watchdog {
201                compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
202                timeout-sec = <60>;
203            };
204
205            thermal-sensor {
206                compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
207                #thermal-sensor-cells = <1>;
208            };
209        };
210    };
211