1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/iio/adc/fsl,vf610-adc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ADC found on Freescale vf610 and similar SoCs
8
9maintainers:
10  - Haibo Chen <haibo.chen@nxp.com>
11
12description:
13  ADCs found on vf610/i.MX6slx and upward SoCs from Freescale.
14
15properties:
16  compatible:
17    const: fsl,vf610-adc
18
19  reg:
20    maxItems: 1
21
22  interrupts:
23    maxItems: 1
24
25  clocks:
26    description: ADC source clock (ipg clock)
27    maxItems: 1
28
29  clock-names:
30    const: adc
31
32  vref-supply:
33    description: ADC reference voltage supply.
34
35  fsl,adck-max-frequency:
36    $ref: /schemas/types.yaml#/definitions/uint32-array
37    minItems: 3
38    maxItems: 3
39    description: |
40      Maximum frequencies from datasheet operating requirements.
41      Three values necessary to cover the 3 conversion modes.
42      * Frequency in normal mode (ADLPC=0, ADHSC=0)
43      * Frequency in high-speed mode (ADLPC=0, ADHSC=1)
44      * Frequency in low-power mode (ADLPC=1, ADHSC=0)
45
46  min-sample-time:
47    $ref: /schemas/types.yaml#/definitions/uint32
48    description:
49      Minimum sampling time in nanoseconds. This value has
50      to be chosen according to the conversion mode and the connected analog
51      source resistance (R_as) and capacitance (C_as). Refer the datasheet's
52      operating requirements. A safe default across a wide range of R_as and
53      C_as as well as conversion modes is 1000ns.
54
55  "#io-channel-cells":
56    const: 1
57
58required:
59  - compatible
60  - reg
61  - interrupts
62  - clocks
63  - clock-names
64  - vref-supply
65
66additionalProperties: false
67
68examples:
69  - |
70    #include <dt-bindings/clock/vf610-clock.h>
71    adc@4003b000 {
72        compatible = "fsl,vf610-adc";
73        reg = <0x4003b000 0x1000>;
74        interrupts = <0 53 0x04>;
75        clocks = <&clks VF610_CLK_ADC0>;
76        clock-names = "adc";
77        fsl,adck-max-frequency = <30000000>, <40000000>, <20000000>;
78        vref-supply = <&reg_vcc_3v3_mcu>;
79        min-sample-time = <10000>;
80    };
81...
82