1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings
8
9description:
10  The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
11  least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
12  cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
13  depends on the SPI bus master driver.
14
15allOf:
16  - $ref: "dsa.yaml#"
17  - $ref: /schemas/spi/spi-peripheral-props.yaml#
18
19maintainers:
20  - Vladimir Oltean <vladimir.oltean@nxp.com>
21
22properties:
23  compatible:
24    enum:
25      - nxp,sja1105e
26      - nxp,sja1105t
27      - nxp,sja1105p
28      - nxp,sja1105q
29      - nxp,sja1105r
30      - nxp,sja1105s
31      - nxp,sja1110a
32      - nxp,sja1110b
33      - nxp,sja1110c
34      - nxp,sja1110d
35
36  reg:
37    maxItems: 1
38
39  # Optional container node for the 2 internal MDIO buses of the SJA1110
40  # (one for the internal 100base-T1 PHYs and the other for the single
41  # 100base-TX PHY). The "reg" property does not have physical significance.
42  # The PHY addresses to port correspondence is as follows: for 100base-T1,
43  # port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
44  # PHY 1.
45  mdios:
46    type: object
47
48    properties:
49      '#address-cells':
50        const: 1
51      '#size-cells':
52        const: 0
53
54    patternProperties:
55      "^mdio@[0-1]$":
56        $ref: /schemas/net/mdio.yaml#
57        unevaluatedProperties: false
58
59        properties:
60          compatible:
61            oneOf:
62              - enum:
63                  - nxp,sja1110-base-t1-mdio
64                  - nxp,sja1110-base-tx-mdio
65
66          reg:
67            oneOf:
68              - enum:
69                  - 0
70                  - 1
71
72        required:
73          - compatible
74          - reg
75
76patternProperties:
77  "^(ethernet-)?ports$":
78    patternProperties:
79      "^(ethernet-)?port@[0-9]+$":
80        allOf:
81          - if:
82              properties:
83                phy-mode:
84                  contains:
85                    enum:
86                      - rgmii
87                      - rgmii-rxid
88                      - rgmii-txid
89                      - rgmii-id
90            then:
91              properties:
92                rx-internal-delay-ps:
93                  $ref: "#/$defs/internal-delay-ps"
94                tx-internal-delay-ps:
95                  $ref: "#/$defs/internal-delay-ps"
96
97required:
98  - compatible
99  - reg
100
101$defs:
102  internal-delay-ps:
103    description:
104      Disable tunable delay lines using 0 ps, or enable them and select
105      the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
106      (101.7 degree shift) in increments of 0.9 degrees (20 ps).
107    enum:
108      [0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
109       1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
110       2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
111
112unevaluatedProperties: false
113
114examples:
115  - |
116    spi {
117            #address-cells = <1>;
118            #size-cells = <0>;
119
120            ethernet-switch@1 {
121                    reg = <0x1>;
122                    compatible = "nxp,sja1105t";
123
124                    ethernet-ports {
125                            #address-cells = <1>;
126                            #size-cells = <0>;
127
128                            port@0 {
129                                    phy-handle = <&rgmii_phy6>;
130                                    phy-mode = "rgmii-id";
131                                    rx-internal-delay-ps = <0>;
132                                    tx-internal-delay-ps = <0>;
133                                    reg = <0>;
134                            };
135
136                            port@1 {
137                                    phy-handle = <&rgmii_phy3>;
138                                    phy-mode = "rgmii-id";
139                                    rx-internal-delay-ps = <0>;
140                                    tx-internal-delay-ps = <0>;
141                                    reg = <1>;
142                            };
143
144                            port@2 {
145                                    phy-handle = <&rgmii_phy4>;
146                                    phy-mode = "rgmii-id";
147                                    rx-internal-delay-ps = <0>;
148                                    tx-internal-delay-ps = <0>;
149                                    reg = <2>;
150                            };
151
152                            port@3 {
153                                    phy-handle = <&rgmii_phy4>;
154                                    phy-mode = "rgmii-id";
155                                    rx-internal-delay-ps = <0>;
156                                    tx-internal-delay-ps = <0>;
157                                    reg = <3>;
158                            };
159
160                            port@4 {
161                                    ethernet = <&enet2>;
162                                    phy-mode = "rgmii";
163                                    rx-internal-delay-ps = <0>;
164                                    tx-internal-delay-ps = <0>;
165                                    reg = <4>;
166
167                                    fixed-link {
168                                            speed = <1000>;
169                                            full-duplex;
170                                    };
171                            };
172                    };
173            };
174    };
175