1*c66ec88fSEmmanuel VadotMediaTek XS-PHY binding 2*c66ec88fSEmmanuel Vadot-------------------------- 3*c66ec88fSEmmanuel Vadot 4*c66ec88fSEmmanuel VadotThe XS-PHY controller supports physical layer functionality for USB3.1 5*c66ec88fSEmmanuel VadotGEN2 controller on MediaTek SoCs. 6*c66ec88fSEmmanuel Vadot 7*c66ec88fSEmmanuel VadotRequired properties (controller (parent) node): 8*c66ec88fSEmmanuel Vadot - compatible : should be "mediatek,<soc-model>-xsphy", "mediatek,xsphy", 9*c66ec88fSEmmanuel Vadot soc-model is the name of SoC, such as mt3611 etc; 10*c66ec88fSEmmanuel Vadot when using "mediatek,xsphy" compatible string, you need SoC specific 11*c66ec88fSEmmanuel Vadot ones in addition, one of: 12*c66ec88fSEmmanuel Vadot - "mediatek,mt3611-xsphy" 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadot - #address-cells, #size-cells : should use the same values as the root node 15*c66ec88fSEmmanuel Vadot - ranges: must be present 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel VadotOptional properties (controller (parent) node): 18*c66ec88fSEmmanuel Vadot - reg : offset and length of register shared by multiple U3 ports, 19*c66ec88fSEmmanuel Vadot exclude port's private register, if only U2 ports provided, 20*c66ec88fSEmmanuel Vadot shouldn't use the property. 21*c66ec88fSEmmanuel Vadot - mediatek,src-ref-clk-mhz : u32, frequency of reference clock for slew rate 22*c66ec88fSEmmanuel Vadot calibrate 23*c66ec88fSEmmanuel Vadot - mediatek,src-coef : u32, coefficient for slew rate calibrate, depends on 24*c66ec88fSEmmanuel Vadot SoC process 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel VadotRequired nodes : a sub-node is required for each port the controller 27*c66ec88fSEmmanuel Vadot provides. Address range information including the usual 28*c66ec88fSEmmanuel Vadot 'reg' property is used inside these nodes to describe 29*c66ec88fSEmmanuel Vadot the controller's topology. 30*c66ec88fSEmmanuel Vadot 31*c66ec88fSEmmanuel VadotRequired properties (port (child) node): 32*c66ec88fSEmmanuel Vadot- reg : address and length of the register set for the port. 33*c66ec88fSEmmanuel Vadot- clocks : a list of phandle + clock-specifier pairs, one for each 34*c66ec88fSEmmanuel Vadot entry in clock-names 35*c66ec88fSEmmanuel Vadot- clock-names : must contain 36*c66ec88fSEmmanuel Vadot "ref": 48M reference clock for HighSpeed analog phy; and 26M 37*c66ec88fSEmmanuel Vadot reference clock for SuperSpeedPlus analog phy, sometimes is 38*c66ec88fSEmmanuel Vadot 24M, 25M or 27M, depended on platform. 39*c66ec88fSEmmanuel Vadot- #phy-cells : should be 1 40*c66ec88fSEmmanuel Vadot cell after port phandle is phy type from: 41*c66ec88fSEmmanuel Vadot - PHY_TYPE_USB2 42*c66ec88fSEmmanuel Vadot - PHY_TYPE_USB3 43*c66ec88fSEmmanuel Vadot 44*c66ec88fSEmmanuel VadotThe following optional properties are only for debug or HQA test 45*c66ec88fSEmmanuel VadotOptional properties (PHY_TYPE_USB2 port (child) node): 46*c66ec88fSEmmanuel Vadot- mediatek,eye-src : u32, the value of slew rate calibrate 47*c66ec88fSEmmanuel Vadot- mediatek,eye-vrt : u32, the selection of VRT reference voltage 48*c66ec88fSEmmanuel Vadot- mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage 49*c66ec88fSEmmanuel Vadot- mediatek,efuse-intr : u32, the selection of Internal Resistor 50*c66ec88fSEmmanuel Vadot 51*c66ec88fSEmmanuel VadotOptional properties (PHY_TYPE_USB3 port (child) node): 52*c66ec88fSEmmanuel Vadot- mediatek,efuse-intr : u32, the selection of Internal Resistor 53*c66ec88fSEmmanuel Vadot- mediatek,efuse-tx-imp : u32, the selection of TX Impedance 54*c66ec88fSEmmanuel Vadot- mediatek,efuse-rx-imp : u32, the selection of RX Impedance 55*c66ec88fSEmmanuel Vadot 56*c66ec88fSEmmanuel VadotBanks layout of xsphy 57*c66ec88fSEmmanuel Vadot------------------------------------------------------------- 58*c66ec88fSEmmanuel Vadotport offset bank 59*c66ec88fSEmmanuel Vadotu2 port0 0x0000 MISC 60*c66ec88fSEmmanuel Vadot 0x0100 FMREG 61*c66ec88fSEmmanuel Vadot 0x0300 U2PHY_COM 62*c66ec88fSEmmanuel Vadotu2 port1 0x1000 MISC 63*c66ec88fSEmmanuel Vadot 0x1100 FMREG 64*c66ec88fSEmmanuel Vadot 0x1300 U2PHY_COM 65*c66ec88fSEmmanuel Vadotu2 port2 0x2000 MISC 66*c66ec88fSEmmanuel Vadot ... 67*c66ec88fSEmmanuel Vadotu31 common 0x3000 DIG_GLB 68*c66ec88fSEmmanuel Vadot 0x3100 PHYA_GLB 69*c66ec88fSEmmanuel Vadotu31 port0 0x3400 DIG_LN_TOP 70*c66ec88fSEmmanuel Vadot 0x3500 DIG_LN_TX0 71*c66ec88fSEmmanuel Vadot 0x3600 DIG_LN_RX0 72*c66ec88fSEmmanuel Vadot 0x3700 DIG_LN_DAIF 73*c66ec88fSEmmanuel Vadot 0x3800 PHYA_LN 74*c66ec88fSEmmanuel Vadotu31 port1 0x3a00 DIG_LN_TOP 75*c66ec88fSEmmanuel Vadot 0x3b00 DIG_LN_TX0 76*c66ec88fSEmmanuel Vadot 0x3c00 DIG_LN_RX0 77*c66ec88fSEmmanuel Vadot 0x3d00 DIG_LN_DAIF 78*c66ec88fSEmmanuel Vadot 0x3e00 PHYA_LN 79*c66ec88fSEmmanuel Vadot ... 80*c66ec88fSEmmanuel Vadot 81*c66ec88fSEmmanuel VadotDIG_GLB & PHYA_GLB are shared by U31 ports. 82*c66ec88fSEmmanuel Vadot 83*c66ec88fSEmmanuel VadotExample: 84*c66ec88fSEmmanuel Vadot 85*c66ec88fSEmmanuel Vadotu3phy: usb-phy@11c40000 { 86*c66ec88fSEmmanuel Vadot compatible = "mediatek,mt3611-xsphy", "mediatek,xsphy"; 87*c66ec88fSEmmanuel Vadot reg = <0 0x11c43000 0 0x0200>; 88*c66ec88fSEmmanuel Vadot mediatek,src-ref-clk-mhz = <26>; 89*c66ec88fSEmmanuel Vadot mediatek,src-coef = <17>; 90*c66ec88fSEmmanuel Vadot #address-cells = <2>; 91*c66ec88fSEmmanuel Vadot #size-cells = <2>; 92*c66ec88fSEmmanuel Vadot ranges; 93*c66ec88fSEmmanuel Vadot 94*c66ec88fSEmmanuel Vadot u2port0: usb-phy@11c40000 { 95*c66ec88fSEmmanuel Vadot reg = <0 0x11c40000 0 0x0400>; 96*c66ec88fSEmmanuel Vadot clocks = <&clk48m>; 97*c66ec88fSEmmanuel Vadot clock-names = "ref"; 98*c66ec88fSEmmanuel Vadot mediatek,eye-src = <4>; 99*c66ec88fSEmmanuel Vadot #phy-cells = <1>; 100*c66ec88fSEmmanuel Vadot }; 101*c66ec88fSEmmanuel Vadot 102*c66ec88fSEmmanuel Vadot u3port0: usb-phy@11c43000 { 103*c66ec88fSEmmanuel Vadot reg = <0 0x11c43400 0 0x0500>; 104*c66ec88fSEmmanuel Vadot clocks = <&clk26m>; 105*c66ec88fSEmmanuel Vadot clock-names = "ref"; 106*c66ec88fSEmmanuel Vadot mediatek,efuse-intr = <28>; 107*c66ec88fSEmmanuel Vadot #phy-cells = <1>; 108*c66ec88fSEmmanuel Vadot }; 109*c66ec88fSEmmanuel Vadot}; 110