1NVIDIA Tegra194 pinmux controller
2
3Required properties:
4- compatible: "nvidia,tegra194-pinmux"
5- reg: Should contain a list of base address and size pairs for:
6  - first entry: The APB_MISC_GP_*_PADCTRL registers (pad control)
7  - second entry: The PINMUX_AUX_* registers (pinmux)
8
9Please refer to pinctrl-bindings.txt in this directory for details of the
10common pinctrl bindings used by client devices, including the meaning of the
11phrase "pin configuration node".
12
13Tegra's pin configuration nodes act as a container for an arbitrary number of
14subnodes. Each of these subnodes represents some desired configuration for a
15pin, a group, or a list of pins or groups. This configuration can include the
16mux function to select on those pin(s)/group(s), and various pin configuration
17parameters, such as pull-up, tristate, drive strength, etc.
18
19See the TRM to determine which properties and values apply to each pin/group.
20Macro values for property values are defined in
21include/dt-binding/pinctrl/pinctrl-tegra.h.
22
23Required subnode-properties:
24- nvidia,pins : An array of strings. Each string contains the name of a pin or
25    group. Valid values for these names are listed below.
26
27Optional subnode-properties:
28- nvidia,function: A string containing the name of the function to mux to the
29    pin or group.
30- nvidia,pull: Integer, representing the pull-down/up to apply to the pin.
31    0: none, 1: down, 2: up.
32- nvidia,tristate: Integer.
33    0: drive, 1: tristate.
34- nvidia,enable-input: Integer. Enable the pin's input path.
35    enable :TEGRA_PIN_ENABLE and
36    disable or output only: TEGRA_PIN_DISABLE.
37- nvidia,open-drain: Integer.
38    enable: TEGRA_PIN_ENABLE.
39    disable: TEGRA_PIN_DISABLE.
40- nvidia,lock: Integer. Lock the pin configuration against further changes
41    until reset.
42    enable: TEGRA_PIN_ENABLE.
43    disable: TEGRA_PIN_DISABLE.
44- nvidia,io-hv: Integer. Select high-voltage receivers.
45    normal: TEGRA_PIN_DISABLE
46    high: TEGRA_PIN_ENABLE
47- nvidia,schmitt: Integer. Enables Schmitt Trigger on the input.
48    normal: TEGRA_PIN_DISABLE
49    high: TEGRA_PIN_ENABLE
50- nvidia,drive-type: Integer. Valid range 0...3.
51- nvidia,pull-down-strength: Integer. Controls drive strength. 0 is weakest.
52    The range of valid values depends on the pingroup. See "CAL_DRVDN" in the
53    Tegra TRM.
54- nvidia,pull-up-strength: Integer. Controls drive strength. 0 is weakest.
55    The range of valid values depends on the pingroup. See "CAL_DRVUP" in the
56    Tegra TRM.
57
58Valid values for pin and group names (nvidia,pin) are:
59
60    These correspond to Tegra PADCTL_* (pinmux) registers.
61
62  Mux groups:
63
64    These correspond to Tegra PADCTL_* (pinmux) registers. Any property
65    that exists in those registers may be set for the following pin names.
66
67    pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
68
69  Drive groups:
70
71    These registers controls a single pin for which a mux group exists.
72    See the list above for the pin name to use when configuring the pinmux.
73
74    pex_l5_clkreq_n_pgg0, pex_l5_rst_n_pgg1
75
76Valid values for nvidia,functions are:
77
78    pe5
79
80Power Domain:
81    pex_l5_clkreq_n_pgg0 and pex_l5_rst_n_pgg1 are part of PCIE C5 power
82    partition. Client devices must enable this partition before accessing
83    these pins here.
84
85
86Example:
87
88		tegra_pinctrl: pinmux: pinmux@2430000 {
89			compatible = "nvidia,tegra194-pinmux";
90			reg = <0x2430000 0x17000
91			       0xc300000 0x4000>;
92
93			pinctrl-names = "pex_rst";
94			pinctrl-0 = <&pex_rst_c5_out_state>;
95
96			pex_rst_c5_out_state: pex_rst_c5_out {
97				pex_rst {
98					nvidia,pins = "pex_l5_rst_n_pgg1";
99					nvidia,schmitt = <TEGRA_PIN_DISABLE>;
100					nvidia,lpdr = <TEGRA_PIN_ENABLE>;
101					nvidia,enable-input = <TEGRA_PIN_DISABLE>;
102					nvidia,io-hv = <TEGRA_PIN_ENABLE>;
103					nvidia,tristate = <TEGRA_PIN_DISABLE>;
104					nvidia,pull = <TEGRA_PIN_PULL_NONE>;
105				};
106			};
107		};
108