1Qualcomm MSM8994 TLMM block
2
3This binding describes the Top Level Mode Multiplexer block found in the
4MSM8994 platform.
5
6- compatible:
7	Usage: required
8	Value type: <string>
9	Definition: Should contain one of:
10		    "qcom,msm8992-pinctrl",
11		    "qcom,msm8994-pinctrl".
12
13- reg:
14	Usage: required
15	Value type: <prop-encoded-array>
16	Definition: the base address and size of the TLMM register space.
17
18- interrupts:
19	Usage: required
20	Value type: <prop-encoded-array>
21	Definition: should specify the TLMM summary IRQ.
22
23- interrupt-controller:
24	Usage: required
25	Value type: <none>
26	Definition: identifies this node as an interrupt controller
27
28- #interrupt-cells:
29	Usage: required
30	Value type: <u32>
31	Definition: must be 2. Specifying the pin number and flags, as defined
32		    in <dt-bindings/interrupt-controller/irq.h>
33
34- gpio-controller:
35	Usage: required
36	Value type: <none>
37	Definition: identifies this node as a gpio controller
38
39- #gpio-cells:
40	Usage: required
41	Value type: <u32>
42	Definition: must be 2. Specifying the pin number and flags, as defined
43		    in <dt-bindings/gpio/gpio.h>
44
45- gpio-ranges:
46	Usage: required
47	Definition:  see ../gpio/gpio.txt
48
49- gpio-reserved-ranges:
50	Usage: optional
51	Definition: see ../gpio/gpio.txt
52
53Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
54a general description of GPIO and interrupt bindings.
55
56Please refer to pinctrl-bindings.txt in this directory for details of the
57common pinctrl bindings used by client devices, including the meaning of the
58phrase "pin configuration node".
59
60The pin configuration nodes act as a container for an arbitrary number of
61subnodes. Each of these subnodes represents some desired configuration for a
62pin, a group, or a list of pins or groups. This configuration can include the
63mux function to select on those pin(s)/group(s), and various pin configuration
64parameters, such as pull-up, drive strength, etc.
65
66
67PIN CONFIGURATION NODES:
68
69The name of each subnode is not important; all subnodes should be enumerated
70and processed purely based on their content.
71
72Each subnode only affects those parameters that are explicitly listed. In
73other words, a subnode that lists a mux function but no pin configuration
74parameters implies no information about any pin configuration parameters.
75Similarly, a pin subnode that describes a pullup parameter implies no
76information about e.g. the mux function.
77
78
79The following generic properties as defined in pinctrl-bindings.txt are valid
80to specify in a pin configuration subnode:
81
82- pins:
83	Usage: required
84	Value type: <string-array>
85	Definition: List of gpio pins affected by the properties specified in
86		    this subnode.
87
88		    Valid pins are:
89		      gpio0-gpio145
90		        Supports mux, bias and drive-strength
91
92		      sdc1_clk, sdc1_cmd, sdc1_data sdc1_rclk, sdc2_clk,
93		      sdc2_cmd, sdc2_data
94		        Supports bias and drive-strength
95
96- function:
97	Usage: required
98	Value type: <string>
99	Definition: Specify the alternative function to be configured for the
100		    specified pins. Functions are only valid for gpio pins.
101		    Valid values are:
102
103		    audio_ref_clk,  blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5,
104		    blsp_i2c6, blsp_i2c7, blsp_i2c8, blsp_i2c9, blsp_i2c10, blsp_i2c11,
105		    blsp_i2c12, blsp_spi1, blsp_spi1_cs1, blsp_spi1_cs2, blsp_spi1_cs3,
106		    blsp_spi2, blsp_spi2_cs1, blsp_spi2_cs2, blsp_spi2_cs3, blsp_spi3,
107		    blsp_spi4, blsp_spi5, blsp_spi6, blsp_spi7, blsp_spi8, blsp_spi9,
108		    blsp_spi10, blsp_spi10_cs1, blsp_spi10_cs2, blsp_spi10_cs3, blsp_spi11,
109		    blsp_spi12, blsp_uart1, blsp_uart2, blsp_uart3, blsp_uart4, blsp_uart5,
110		    blsp_uart6, blsp_uart7, blsp_uart8, blsp_uart9, blsp_uart10, blsp_uart11,
111		    blsp_uart12, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim4, blsp_uim5,
112		    blsp_uim6, blsp_uim7, blsp_uim8, blsp_uim9, blsp_uim10, blsp_uim11,
113		    blsp_uim12, blsp11_i2c_scl_b, blsp11_i2c_sda_b, blsp11_uart_rx_b,
114		    blsp11_uart_tx_b, cam_mclk0, cam_mclk1, cam_mclk2, cam_mclk3,
115		    cci_async_in0, cci_async_in1, cci_async_in2, cci_i2c0, cci_i2c1,
116		    cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
117		    gcc_gp1_clk_a, gcc_gp1_clk_b, gcc_gp2_clk_a, gcc_gp2_clk_b, gcc_gp3_clk_a,
118		    gcc_gp3_clk_b, gp_mn, gp_pdm0, gp_pdm1, gp_pdm2, gp0_clk,
119		    gp1_clk, gps_tx, gsm_tx, hdmi_cec, hdmi_ddc, hdmi_hpd, hdmi_rcv,
120		    mdp_vsync, mss_lte, nav_pps, nav_tsync, qdss_cti_trig_in_a,
121		    qdss_cti_trig_in_b, qdss_cti_trig_in_c, qdss_cti_trig_in_d,
122		    qdss_cti_trig_out_a, qdss_cti_trig_out_b, qdss_cti_trig_out_c,
123		    qdss_cti_trig_out_d, qdss_traceclk_a, qdss_traceclk_b, qdss_tracectl_a,
124		    qdss_tracectl_b, qdss_tracedata_a, qdss_tracedata_b, qua_mi2s, pci_e0,
125		    pci_e1, pri_mi2s, sdc4, sec_mi2s, slimbus, spkr_i2s, ter_mi2s, tsif1,
126		    tsif2, uim_batt_alarm, uim1, uim2, uim3, uim4, gpio
127
128- bias-disable:
129	Usage: optional
130	Value type: <none>
131	Definition: The specified pins should be configured as no pull.
132
133- bias-pull-down:
134	Usage: optional
135	Value type: <none>
136	Definition: The specified pins should be configured as pull down.
137
138- bias-pull-up:
139	Usage: optional
140	Value type: <none>
141	Definition: The specified pins should be configured as pull up.
142
143- output-high:
144	Usage: optional
145	Value type: <none>
146	Definition: The specified pins are configured in output mode, driven
147		    high.
148		    Not valid for sdc pins.
149
150- output-low:
151	Usage: optional
152	Value type: <none>
153	Definition: The specified pins are configured in output mode, driven
154		    low.
155		    Not valid for sdc pins.
156
157- drive-strength:
158	Usage: optional
159	Value type: <u32>
160	Definition: Selects the drive strength for the specified pins, in mA.
161		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
162
163Example:
164
165	msmgpio: pinctrl@fd510000 {
166		compatible = "qcom,msm8994-pinctrl";
167		reg = <0xfd510000 0x4000>;
168		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
169		gpio-controller;
170		#gpio-cells = <2>;
171		gpio-ranges = <&msmgpio 0 0 146>;
172		interrupt-controller;
173		#interrupt-cells = <2>;
174
175		blsp1_uart2_default: blsp1_uart2_default {
176			pinmux {
177				pins = "gpio4", "gpio5";
178				function = "blsp_uart2";
179			};
180			pinconf {
181				pins = "gpio4", "gpio5";
182				drive-strength = <16>;
183				bias-disable;
184			};
185		};
186	};
187