1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-pinctrl.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Technologies, Inc. SDX65 TLMM block
8
9maintainers:
10  - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
11
12description:
13  This binding describes the Top Level Mode Multiplexer block found in the
14  SDX65 platform.
15
16properties:
17  compatible:
18    const: qcom,sdx65-tlmm
19
20  reg:
21    maxItems: 1
22
23  interrupts:
24    maxItems: 1
25
26  interrupt-controller: true
27
28  '#interrupt-cells':
29    description: Specifies the PIN numbers and Flags, as defined in
30      include/dt-bindings/interrupt-controller/irq.h
31    const: 2
32
33  gpio-controller: true
34
35  '#gpio-cells':
36    description: Specifying the pin number and flags, as defined in
37      include/dt-bindings/gpio/gpio.h
38    const: 2
39
40  gpio-ranges:
41    maxItems: 1
42
43  gpio-reserved-ranges:
44    maxItems: 1
45
46#PIN CONFIGURATION NODES
47patternProperties:
48  '-state$':
49    oneOf:
50      - $ref: "#/$defs/qcom-sdx65-tlmm-state"
51      - patternProperties:
52          ".*":
53            $ref: "#/$defs/qcom-sdx65-tlmm-state"
54'$defs':
55  qcom-sdx65-tlmm-state:
56    type: object
57    description:
58      Pinctrl node's client devices use subnodes for desired pin configuration.
59      Client device subnodes use below standard properties.
60    $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
61
62    properties:
63      pins:
64        description:
65          List of gpio pins affected by the properties specified in this subnode.
66        items:
67          oneOf:
68            - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-7])$"
69            - enum: [ ufs_reset, sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data, sdc1_rclk ]
70        minItems: 1
71        maxItems: 150
72
73      function:
74        description:
75          Specify the alternative function to be configured for the specified
76          pins. Functions are only valid for gpio pins.
77        enum: [ blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens,
78                bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8,
79                qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b,
80                dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10,
81                blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12,
82                mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11,
83                atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char,
84                cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b,
85                pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c,
86                qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4,
87                qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5,
88                atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6,
89                atest_usb20, atest_char0, dac_calib10, qdss_stm10,
90                qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6,
91                blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11,
92                qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1,
93                qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11,
94                dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6,
95                qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14,
96                dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem,
97                dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto,
98                dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0,
99                dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25,
100                sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2,
101                qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3,
102                uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9,
103                blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7,
104                qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11,
105                blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0,
106                cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4,
107                blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4,
108                qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus,
109                isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s,
110                qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b,
111                sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b,
112                gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12,
113                qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29,
114                tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27,
115                qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk,
116                sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b,
117                sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b,
118                ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b,
119                blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt,
120                pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11,
121                qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx,
122                qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3,
123                gpio ]
124
125      drive-strength:
126        enum: [2, 4, 6, 8, 10, 12, 14, 16]
127        default: 2
128        description:
129          Selects the drive strength for the specified pins, in mA.
130
131      bias-pull-down: true
132
133      bias-pull-up: true
134
135      bias-disable: true
136
137      output-high: true
138
139      output-low: true
140
141    required:
142      - pins
143      - function
144
145    additionalProperties: false
146
147required:
148  - compatible
149  - reg
150  - interrupts
151  - interrupt-controller
152  - '#interrupt-cells'
153  - gpio-controller
154  - '#gpio-cells'
155  - gpio-ranges
156
157additionalProperties: false
158
159examples:
160  - |
161    #include <dt-bindings/interrupt-controller/arm-gic.h>
162    tlmm: pinctrl@f100000 {
163        compatible = "qcom,sdx65-tlmm";
164        reg = <0x03000000 0xdc2000>;
165        gpio-controller;
166        #gpio-cells = <2>;
167        gpio-ranges = <&tlmm 0 0 109>;
168        interrupt-controller;
169        #interrupt-cells = <2>;
170        interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
171
172        gpio-wo-subnode-state {
173            pins = "gpio1";
174            function = "gpio";
175        };
176
177        uart-w-subnodes-state {
178            rx {
179                pins = "gpio4";
180                function = "blsp_uart1";
181                bias-pull-up;
182            };
183
184            tx {
185                pins = "gpio5";
186                function = "blsp_uart1";
187                bias-disable;
188            };
189        };
190    };
191...
192