1# SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/remoteproc/ti,k3-r5f-rproc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI K3 R5F processor subsystems
8
9maintainers:
10  - Suman Anna <s-anna@ti.com>
11
12description: |
13  The TI K3 family of SoCs usually have one or more dual-core Arm Cortex R5F
14  processor subsystems/clusters (R5FSS). The dual core cluster can be used
15  either in a LockStep mode providing safety/fault tolerance features or in a
16  Split mode providing two individual compute cores for doubling the compute
17  capacity. These are used together with other processors present on the SoC
18  to achieve various system level goals.
19
20  Each Dual-Core R5F sub-system is represented as a single DTS node
21  representing the cluster, with a pair of child DT nodes representing
22  the individual R5F cores. Each node has a number of required or optional
23  properties that enable the OS running on the host processor to perform
24  the device management of the remote processor and to communicate with the
25  remote processor.
26
27properties:
28  $nodename:
29    pattern: "^r5fss(@.*)?"
30
31  compatible:
32    enum:
33      - ti,am654-r5fss
34      - ti,j721e-r5fss
35      - ti,j7200-r5fss
36
37  power-domains:
38    description: |
39      Should contain a phandle to a PM domain provider node and an args
40      specifier containing the R5FSS device id value.
41    maxItems: 1
42
43  "#address-cells":
44    const: 1
45
46  "#size-cells":
47    const: 1
48
49  ranges:
50    description: |
51      Standard ranges definition providing address translations for
52      local R5F TCM address spaces to bus addresses.
53
54# Optional properties:
55# --------------------
56
57  ti,cluster-mode:
58    $ref: /schemas/types.yaml#/definitions/uint32
59    enum: [0, 1]
60    description: |
61      Configuration Mode for the Dual R5F cores within the R5F cluster.
62      Should be either a value of 1 (LockStep mode) or 0 (Split mode),
63      default is LockStep mode if omitted.
64
65# R5F Processor Child Nodes:
66# ==========================
67
68patternProperties:
69  "^r5f@[a-f0-9]+$":
70    type: object
71    description: |
72      The R5F Sub-System device node should define two R5F child nodes, each
73      node representing a TI instantiation of the Arm Cortex R5F core. There
74      are some specific integration differences for the IP like the usage of
75      a Region Address Translator (RAT) for translating the larger SoC bus
76      addresses into a 32-bit address space for the processor.
77
78      Each R5F core has an associated 64 KB of Tightly-Coupled Memory (TCM)
79      internal memories split between two banks - TCMA and TCMB (further
80      interleaved into two banks TCMB0 and TCMB1). These memories (also called
81      ATCM and BTCM) provide read/write performance on par with the core's L1
82      caches. Each of the TCMs can be enabled or disabled independently and
83      either of them can be configured to appear at that R5F's address 0x0.
84
85      The cores do not use an MMU, but has a Region Address Translater
86      (RAT) module that is accessible only from the R5Fs for providing
87      translations between 32-bit CPU addresses into larger system bus
88      addresses. Cache and memory access settings are provided through a
89      Memory Protection Unit (MPU), programmable only from the R5Fs.
90
91    allOf:
92      - $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
93
94    properties:
95      compatible:
96        enum:
97          - ti,am654-r5f
98          - ti,j721e-r5f
99          - ti,j7200-r5f
100
101      reg:
102        items:
103          - description: Address and Size of the ATCM internal memory region
104          - description: Address and Size of the BTCM internal memory region
105
106      reg-names:
107        items:
108          - const: atcm
109          - const: btcm
110
111      resets:
112        description: |
113          Should contain the phandle to the reset controller node managing the
114          local resets for this device, and a reset specifier.
115        maxItems: 1
116
117      firmware-name:
118        description: |
119          Should contain the name of the default firmware image
120          file located on the firmware search path
121
122# The following properties are mandatory for R5F Core0 in both LockStep and Split
123# modes, and are mandatory for R5F Core1 _only_ in Split mode. They are unused for
124# R5F Core1 in LockStep mode:
125
126      mboxes:
127        description: |
128          OMAP Mailbox specifier denoting the sub-mailbox, to be used for
129          communication with the remote processor. This property should match
130          with the sub-mailbox node used in the firmware image.
131        maxItems: 1
132
133      memory-region:
134        description: |
135          phandle to the reserved memory nodes to be associated with the
136          remoteproc device. There should be at least two reserved memory nodes
137          defined. The reserved memory nodes should be carveout nodes, and
138          should be defined with a "no-map" property as per the bindings in
139          Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
140        minItems: 2
141        maxItems: 8
142        items:
143          - description: region used for dynamic DMA allocations like vrings and
144                         vring buffers
145          - description: region reserved for firmware image sections
146        additionalItems: true
147
148
149# Optional properties:
150# --------------------
151# The following properties are optional properties for each of the R5F cores:
152
153      ti,atcm-enable:
154        $ref: /schemas/types.yaml#/definitions/uint32
155        enum: [0, 1]
156        description: |
157          R5F core configuration mode dictating if ATCM should be enabled. The
158          R5F address of ATCM is dictated by ti,loczrama property. Should be
159          either a value of 1 (enabled) or 0 (disabled), default is disabled
160          if omitted. Recommended to enable it for maximizing TCMs.
161
162      ti,btcm-enable:
163        $ref: /schemas/types.yaml#/definitions/uint32
164        enum: [0, 1]
165        description: |
166          R5F core configuration mode dictating if BTCM should be enabled. The
167          R5F address of BTCM is dictated by ti,loczrama property. Should be
168          either a value of 1 (enabled) or 0 (disabled), default is enabled if
169          omitted.
170
171      ti,loczrama:
172        $ref: /schemas/types.yaml#/definitions/uint32
173        enum: [0, 1]
174        description: |
175          R5F core configuration mode dictating which TCM should appear at
176          address 0 (from core's view). Should be either a value of 1 (ATCM
177          at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted.
178
179      sram:
180        $ref: /schemas/types.yaml#/definitions/phandle-array
181        minItems: 1
182        maxItems: 4
183        description: |
184          phandles to one or more reserved on-chip SRAM regions. The regions
185          should be defined as child nodes of the respective SRAM node, and
186          should be defined as per the generic bindings in,
187          Documentation/devicetree/bindings/sram/sram.yaml
188
189    required:
190      - compatible
191      - reg
192      - reg-names
193      - ti,sci
194      - ti,sci-dev-id
195      - ti,sci-proc-ids
196      - resets
197      - firmware-name
198
199    unevaluatedProperties: false
200
201required:
202  - compatible
203  - power-domains
204  - "#address-cells"
205  - "#size-cells"
206  - ranges
207
208additionalProperties: false
209
210examples:
211  - |
212    / {
213        model = "Texas Instruments K3 AM654 SoC";
214        compatible = "ti,am654-evm", "ti,am654";
215        #address-cells = <2>;
216        #size-cells = <2>;
217
218        bus@100000 {
219            compatible = "simple-bus";
220            #address-cells = <2>;
221            #size-cells = <2>;
222            ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
223                     <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>,
224                     <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>,
225                     <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>;
226
227            bus@28380000 {
228                compatible = "simple-bus";
229                #address-cells = <2>;
230                #size-cells = <2>;
231                ranges = <0x00 0x28380000 0x00 0x28380000 0x00 0x03880000>, /* MCU NAVSS */
232                         <0x00 0x41000000 0x00 0x41000000 0x00 0x00020000>, /* MCU R5F Core0 */
233                         <0x00 0x41400000 0x00 0x41400000 0x00 0x00020000>, /* MCU R5F Core1 */
234                         <0x00 0x41c00000 0x00 0x41c00000 0x00 0x00080000>; /* MCU SRAM */
235
236                /* AM65x MCU R5FSS node */
237                mcu_r5fss0: r5fss@41000000 {
238                    compatible = "ti,am654-r5fss";
239                    power-domains = <&k3_pds 129>;
240                    ti,cluster-mode = <1>;
241                    #address-cells = <1>;
242                    #size-cells = <1>;
243                    ranges = <0x41000000 0x00 0x41000000 0x20000>,
244                             <0x41400000 0x00 0x41400000 0x20000>;
245
246                    mcu_r5f0: r5f@41000000 {
247                        compatible = "ti,am654-r5f";
248                        reg = <0x41000000 0x00008000>,
249                              <0x41010000 0x00008000>;
250                        reg-names = "atcm", "btcm";
251                        ti,sci = <&dmsc>;
252                        ti,sci-dev-id = <159>;
253                        ti,sci-proc-ids = <0x01 0xFF>;
254                        resets = <&k3_reset 159 1>;
255                        firmware-name = "am65x-mcu-r5f0_0-fw";
256                        ti,atcm-enable = <1>;
257                        ti,btcm-enable = <1>;
258                        ti,loczrama = <1>;
259                        mboxes = <&mailbox0 &mbox_mcu_r5fss0_core0>;
260                        memory-region = <&mcu_r5fss0_core0_dma_memory_region>,
261                                        <&mcu_r5fss0_core0_memory_region>;
262                        sram = <&mcu_r5fss0_core0_sram>;
263                    };
264
265                    mcu_r5f1: r5f@41400000 {
266                        compatible = "ti,am654-r5f";
267                        reg = <0x41400000 0x00008000>,
268                              <0x41410000 0x00008000>;
269                        reg-names = "atcm", "btcm";
270                        ti,sci = <&dmsc>;
271                        ti,sci-dev-id = <245>;
272                        ti,sci-proc-ids = <0x02 0xFF>;
273                        resets = <&k3_reset 245 1>;
274                        firmware-name = "am65x-mcu-r5f0_1-fw";
275                        ti,atcm-enable = <1>;
276                        ti,btcm-enable = <1>;
277                        ti,loczrama = <1>;
278                        mboxes = <&mailbox1 &mbox_mcu_r5fss0_core1>;
279                    };
280                };
281            };
282        };
283    };
284