1*c66ec88fSEmmanuel VadotSiFive L2 Cache Controller 2*c66ec88fSEmmanuel Vadot-------------------------- 3*c66ec88fSEmmanuel VadotThe SiFive Level 2 Cache Controller is used to provide access to fast copies 4*c66ec88fSEmmanuel Vadotof memory for masters in a Core Complex. The Level 2 Cache Controller also 5*c66ec88fSEmmanuel Vadotacts as directory-based coherency manager. 6*c66ec88fSEmmanuel VadotAll the properties in ePAPR/DeviceTree specification applies for this platform 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel VadotRequired Properties: 9*c66ec88fSEmmanuel Vadot-------------------- 10*c66ec88fSEmmanuel Vadot- compatible: Should be "sifive,fu540-c000-ccache" and "cache" 11*c66ec88fSEmmanuel Vadot 12*c66ec88fSEmmanuel Vadot- cache-block-size: Specifies the block size in bytes of the cache. 13*c66ec88fSEmmanuel Vadot Should be 64 14*c66ec88fSEmmanuel Vadot 15*c66ec88fSEmmanuel Vadot- cache-level: Should be set to 2 for a level 2 cache 16*c66ec88fSEmmanuel Vadot 17*c66ec88fSEmmanuel Vadot- cache-sets: Specifies the number of associativity sets of the cache. 18*c66ec88fSEmmanuel Vadot Should be 1024 19*c66ec88fSEmmanuel Vadot 20*c66ec88fSEmmanuel Vadot- cache-size: Specifies the size in bytes of the cache. Should be 2097152 21*c66ec88fSEmmanuel Vadot 22*c66ec88fSEmmanuel Vadot- cache-unified: Specifies the cache is a unified cache 23*c66ec88fSEmmanuel Vadot 24*c66ec88fSEmmanuel Vadot- interrupts: Must contain 3 entries (DirError, DataError and DataFail signals) 25*c66ec88fSEmmanuel Vadot 26*c66ec88fSEmmanuel Vadot- reg: Physical base address and size of L2 cache controller registers map 27*c66ec88fSEmmanuel Vadot 28*c66ec88fSEmmanuel VadotOptional Properties: 29*c66ec88fSEmmanuel Vadot-------------------- 30*c66ec88fSEmmanuel Vadot- next-level-cache: phandle to the next level cache if present. 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel Vadot- memory-region: reference to the reserved-memory for the L2 Loosely Integrated 33*c66ec88fSEmmanuel Vadot Memory region. The reserved memory node should be defined as per the bindings 34*c66ec88fSEmmanuel Vadot in reserved-memory.txt 35*c66ec88fSEmmanuel Vadot 36*c66ec88fSEmmanuel Vadot 37*c66ec88fSEmmanuel VadotExample: 38*c66ec88fSEmmanuel Vadot 39*c66ec88fSEmmanuel Vadot cache-controller@2010000 { 40*c66ec88fSEmmanuel Vadot compatible = "sifive,fu540-c000-ccache", "cache"; 41*c66ec88fSEmmanuel Vadot cache-block-size = <64>; 42*c66ec88fSEmmanuel Vadot cache-level = <2>; 43*c66ec88fSEmmanuel Vadot cache-sets = <1024>; 44*c66ec88fSEmmanuel Vadot cache-size = <2097152>; 45*c66ec88fSEmmanuel Vadot cache-unified; 46*c66ec88fSEmmanuel Vadot interrupt-parent = <&plic0>; 47*c66ec88fSEmmanuel Vadot interrupts = <1 2 3>; 48*c66ec88fSEmmanuel Vadot reg = <0x0 0x2010000 0x0 0x1000>; 49*c66ec88fSEmmanuel Vadot next-level-cache = <&L25 &L40 &L36>; 50*c66ec88fSEmmanuel Vadot memory-region = <&l2_lim>; 51*c66ec88fSEmmanuel Vadot }; 52