1c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0 */ 2c66ec88fSEmmanuel Vadot /* 3c66ec88fSEmmanuel Vadot * Copyright (c) 2013 Samsung Electronics Co., Ltd. 4c66ec88fSEmmanuel Vadot * Author: Andrzej Hajda <a.hajda@samsung.com> 5c66ec88fSEmmanuel Vadot * 6c66ec88fSEmmanuel Vadot * Device Tree binding constants for Exynos4 clock controller. 7c66ec88fSEmmanuel Vadot */ 8c66ec88fSEmmanuel Vadot 9c66ec88fSEmmanuel Vadot #ifndef _DT_BINDINGS_CLOCK_EXYNOS_4_H 10c66ec88fSEmmanuel Vadot #define _DT_BINDINGS_CLOCK_EXYNOS_4_H 11c66ec88fSEmmanuel Vadot 12c66ec88fSEmmanuel Vadot /* core clocks */ 13c66ec88fSEmmanuel Vadot #define CLK_XXTI 1 14c66ec88fSEmmanuel Vadot #define CLK_XUSBXTI 2 15c66ec88fSEmmanuel Vadot #define CLK_FIN_PLL 3 16c66ec88fSEmmanuel Vadot #define CLK_FOUT_APLL 4 17c66ec88fSEmmanuel Vadot #define CLK_FOUT_MPLL 5 18c66ec88fSEmmanuel Vadot #define CLK_FOUT_EPLL 6 19c66ec88fSEmmanuel Vadot #define CLK_FOUT_VPLL 7 20c66ec88fSEmmanuel Vadot #define CLK_SCLK_APLL 8 21c66ec88fSEmmanuel Vadot #define CLK_SCLK_MPLL 9 22c66ec88fSEmmanuel Vadot #define CLK_SCLK_EPLL 10 23c66ec88fSEmmanuel Vadot #define CLK_SCLK_VPLL 11 24c66ec88fSEmmanuel Vadot #define CLK_ARM_CLK 12 25c66ec88fSEmmanuel Vadot #define CLK_ACLK200 13 26c66ec88fSEmmanuel Vadot #define CLK_ACLK100 14 27c66ec88fSEmmanuel Vadot #define CLK_ACLK160 15 28c66ec88fSEmmanuel Vadot #define CLK_ACLK133 16 29c66ec88fSEmmanuel Vadot #define CLK_MOUT_MPLL_USER_T 17 /* Exynos4x12 only */ 30c66ec88fSEmmanuel Vadot #define CLK_MOUT_MPLL_USER_C 18 /* Exynos4x12 only */ 31c66ec88fSEmmanuel Vadot #define CLK_MOUT_CORE 19 32c66ec88fSEmmanuel Vadot #define CLK_MOUT_APLL 20 33c66ec88fSEmmanuel Vadot #define CLK_SCLK_HDMIPHY 22 34c66ec88fSEmmanuel Vadot #define CLK_OUT_DMC 23 35c66ec88fSEmmanuel Vadot #define CLK_OUT_TOP 24 36c66ec88fSEmmanuel Vadot #define CLK_OUT_LEFTBUS 25 37c66ec88fSEmmanuel Vadot #define CLK_OUT_RIGHTBUS 26 38c66ec88fSEmmanuel Vadot #define CLK_OUT_CPU 27 39c66ec88fSEmmanuel Vadot 40c66ec88fSEmmanuel Vadot /* gate for special clocks (sclk) */ 41c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMC0 128 42c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMC1 129 43c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMC2 130 44c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMC3 131 45c66ec88fSEmmanuel Vadot #define CLK_SCLK_CAM0 132 46c66ec88fSEmmanuel Vadot #define CLK_SCLK_CAM1 133 47c66ec88fSEmmanuel Vadot #define CLK_SCLK_CSIS0 134 48c66ec88fSEmmanuel Vadot #define CLK_SCLK_CSIS1 135 49c66ec88fSEmmanuel Vadot #define CLK_SCLK_HDMI 136 50c66ec88fSEmmanuel Vadot #define CLK_SCLK_MIXER 137 51c66ec88fSEmmanuel Vadot #define CLK_SCLK_DAC 138 52c66ec88fSEmmanuel Vadot #define CLK_SCLK_PIXEL 139 53c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMD0 140 54c66ec88fSEmmanuel Vadot #define CLK_SCLK_MDNIE0 141 /* Exynos4412 only */ 55c66ec88fSEmmanuel Vadot #define CLK_SCLK_MDNIE_PWM0 142 56c66ec88fSEmmanuel Vadot #define CLK_SCLK_MIPI0 143 57c66ec88fSEmmanuel Vadot #define CLK_SCLK_AUDIO0 144 58c66ec88fSEmmanuel Vadot #define CLK_SCLK_MMC0 145 59c66ec88fSEmmanuel Vadot #define CLK_SCLK_MMC1 146 60c66ec88fSEmmanuel Vadot #define CLK_SCLK_MMC2 147 61c66ec88fSEmmanuel Vadot #define CLK_SCLK_MMC3 148 62c66ec88fSEmmanuel Vadot #define CLK_SCLK_MMC4 149 63c66ec88fSEmmanuel Vadot #define CLK_SCLK_SATA 150 /* Exynos4210 only */ 64c66ec88fSEmmanuel Vadot #define CLK_SCLK_UART0 151 65c66ec88fSEmmanuel Vadot #define CLK_SCLK_UART1 152 66c66ec88fSEmmanuel Vadot #define CLK_SCLK_UART2 153 67c66ec88fSEmmanuel Vadot #define CLK_SCLK_UART3 154 68c66ec88fSEmmanuel Vadot #define CLK_SCLK_UART4 155 69c66ec88fSEmmanuel Vadot #define CLK_SCLK_AUDIO1 156 70c66ec88fSEmmanuel Vadot #define CLK_SCLK_AUDIO2 157 71c66ec88fSEmmanuel Vadot #define CLK_SCLK_SPDIF 158 72c66ec88fSEmmanuel Vadot #define CLK_SCLK_SPI0 159 73c66ec88fSEmmanuel Vadot #define CLK_SCLK_SPI1 160 74c66ec88fSEmmanuel Vadot #define CLK_SCLK_SPI2 161 75c66ec88fSEmmanuel Vadot #define CLK_SCLK_SLIMBUS 162 76c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMD1 163 /* Exynos4210 only */ 77c66ec88fSEmmanuel Vadot #define CLK_SCLK_MIPI1 164 /* Exynos4210 only */ 78c66ec88fSEmmanuel Vadot #define CLK_SCLK_PCM1 165 79c66ec88fSEmmanuel Vadot #define CLK_SCLK_PCM2 166 80c66ec88fSEmmanuel Vadot #define CLK_SCLK_I2S1 167 81c66ec88fSEmmanuel Vadot #define CLK_SCLK_I2S2 168 82c66ec88fSEmmanuel Vadot #define CLK_SCLK_MIPIHSI 169 /* Exynos4412 only */ 83c66ec88fSEmmanuel Vadot #define CLK_SCLK_MFC 170 84c66ec88fSEmmanuel Vadot #define CLK_SCLK_PCM0 171 85c66ec88fSEmmanuel Vadot #define CLK_SCLK_G3D 172 86c66ec88fSEmmanuel Vadot #define CLK_SCLK_PWM_ISP 173 /* Exynos4x12 only */ 87c66ec88fSEmmanuel Vadot #define CLK_SCLK_SPI0_ISP 174 /* Exynos4x12 only */ 88c66ec88fSEmmanuel Vadot #define CLK_SCLK_SPI1_ISP 175 /* Exynos4x12 only */ 89c66ec88fSEmmanuel Vadot #define CLK_SCLK_UART_ISP 176 /* Exynos4x12 only */ 90c66ec88fSEmmanuel Vadot #define CLK_SCLK_FIMG2D 177 91c66ec88fSEmmanuel Vadot 92c66ec88fSEmmanuel Vadot /* gate clocks */ 93c66ec88fSEmmanuel Vadot #define CLK_SSS 255 94c66ec88fSEmmanuel Vadot #define CLK_FIMC0 256 95c66ec88fSEmmanuel Vadot #define CLK_FIMC1 257 96c66ec88fSEmmanuel Vadot #define CLK_FIMC2 258 97c66ec88fSEmmanuel Vadot #define CLK_FIMC3 259 98c66ec88fSEmmanuel Vadot #define CLK_CSIS0 260 99c66ec88fSEmmanuel Vadot #define CLK_CSIS1 261 100c66ec88fSEmmanuel Vadot #define CLK_JPEG 262 101c66ec88fSEmmanuel Vadot #define CLK_SMMU_FIMC0 263 102c66ec88fSEmmanuel Vadot #define CLK_SMMU_FIMC1 264 103c66ec88fSEmmanuel Vadot #define CLK_SMMU_FIMC2 265 104c66ec88fSEmmanuel Vadot #define CLK_SMMU_FIMC3 266 105c66ec88fSEmmanuel Vadot #define CLK_SMMU_JPEG 267 106c66ec88fSEmmanuel Vadot #define CLK_VP 268 107c66ec88fSEmmanuel Vadot #define CLK_MIXER 269 108c66ec88fSEmmanuel Vadot #define CLK_TVENC 270 /* Exynos4210 only */ 109c66ec88fSEmmanuel Vadot #define CLK_HDMI 271 110c66ec88fSEmmanuel Vadot #define CLK_SMMU_TV 272 111c66ec88fSEmmanuel Vadot #define CLK_MFC 273 112c66ec88fSEmmanuel Vadot #define CLK_SMMU_MFCL 274 113c66ec88fSEmmanuel Vadot #define CLK_SMMU_MFCR 275 114c66ec88fSEmmanuel Vadot #define CLK_G3D 276 115c66ec88fSEmmanuel Vadot #define CLK_G2D 277 116c66ec88fSEmmanuel Vadot #define CLK_ROTATOR 278 117c66ec88fSEmmanuel Vadot #define CLK_MDMA 279 118c66ec88fSEmmanuel Vadot #define CLK_SMMU_G2D 280 119c66ec88fSEmmanuel Vadot #define CLK_SMMU_ROTATOR 281 120c66ec88fSEmmanuel Vadot #define CLK_SMMU_MDMA 282 121c66ec88fSEmmanuel Vadot #define CLK_FIMD0 283 122c66ec88fSEmmanuel Vadot #define CLK_MIE0 284 123c66ec88fSEmmanuel Vadot #define CLK_MDNIE0 285 /* Exynos4412 only */ 124c66ec88fSEmmanuel Vadot #define CLK_DSIM0 286 125c66ec88fSEmmanuel Vadot #define CLK_SMMU_FIMD0 287 126c66ec88fSEmmanuel Vadot #define CLK_FIMD1 288 /* Exynos4210 only */ 127c66ec88fSEmmanuel Vadot #define CLK_MIE1 289 /* Exynos4210 only */ 128c66ec88fSEmmanuel Vadot #define CLK_DSIM1 290 /* Exynos4210 only */ 129c66ec88fSEmmanuel Vadot #define CLK_SMMU_FIMD1 291 /* Exynos4210 only */ 130c66ec88fSEmmanuel Vadot #define CLK_PDMA0 292 131c66ec88fSEmmanuel Vadot #define CLK_PDMA1 293 132c66ec88fSEmmanuel Vadot #define CLK_PCIE_PHY 294 133c66ec88fSEmmanuel Vadot #define CLK_SATA_PHY 295 /* Exynos4210 only */ 134c66ec88fSEmmanuel Vadot #define CLK_TSI 296 135c66ec88fSEmmanuel Vadot #define CLK_SDMMC0 297 136c66ec88fSEmmanuel Vadot #define CLK_SDMMC1 298 137c66ec88fSEmmanuel Vadot #define CLK_SDMMC2 299 138c66ec88fSEmmanuel Vadot #define CLK_SDMMC3 300 139c66ec88fSEmmanuel Vadot #define CLK_SDMMC4 301 140c66ec88fSEmmanuel Vadot #define CLK_SATA 302 /* Exynos4210 only */ 141c66ec88fSEmmanuel Vadot #define CLK_SROMC 303 142c66ec88fSEmmanuel Vadot #define CLK_USB_HOST 304 143c66ec88fSEmmanuel Vadot #define CLK_USB_DEVICE 305 144c66ec88fSEmmanuel Vadot #define CLK_PCIE 306 145c66ec88fSEmmanuel Vadot #define CLK_ONENAND 307 146c66ec88fSEmmanuel Vadot #define CLK_NFCON 308 147c66ec88fSEmmanuel Vadot #define CLK_SMMU_PCIE 309 148c66ec88fSEmmanuel Vadot #define CLK_GPS 310 149c66ec88fSEmmanuel Vadot #define CLK_SMMU_GPS 311 150c66ec88fSEmmanuel Vadot #define CLK_UART0 312 151c66ec88fSEmmanuel Vadot #define CLK_UART1 313 152c66ec88fSEmmanuel Vadot #define CLK_UART2 314 153c66ec88fSEmmanuel Vadot #define CLK_UART3 315 154c66ec88fSEmmanuel Vadot #define CLK_UART4 316 155c66ec88fSEmmanuel Vadot #define CLK_I2C0 317 156c66ec88fSEmmanuel Vadot #define CLK_I2C1 318 157c66ec88fSEmmanuel Vadot #define CLK_I2C2 319 158c66ec88fSEmmanuel Vadot #define CLK_I2C3 320 159c66ec88fSEmmanuel Vadot #define CLK_I2C4 321 160c66ec88fSEmmanuel Vadot #define CLK_I2C5 322 161c66ec88fSEmmanuel Vadot #define CLK_I2C6 323 162c66ec88fSEmmanuel Vadot #define CLK_I2C7 324 163c66ec88fSEmmanuel Vadot #define CLK_I2C_HDMI 325 164c66ec88fSEmmanuel Vadot #define CLK_TSADC 326 165c66ec88fSEmmanuel Vadot #define CLK_SPI0 327 166c66ec88fSEmmanuel Vadot #define CLK_SPI1 328 167c66ec88fSEmmanuel Vadot #define CLK_SPI2 329 168c66ec88fSEmmanuel Vadot #define CLK_I2S1 330 169c66ec88fSEmmanuel Vadot #define CLK_I2S2 331 170c66ec88fSEmmanuel Vadot #define CLK_PCM0 332 171c66ec88fSEmmanuel Vadot #define CLK_I2S0 333 172c66ec88fSEmmanuel Vadot #define CLK_PCM1 334 173c66ec88fSEmmanuel Vadot #define CLK_PCM2 335 174c66ec88fSEmmanuel Vadot #define CLK_PWM 336 175c66ec88fSEmmanuel Vadot #define CLK_SLIMBUS 337 176c66ec88fSEmmanuel Vadot #define CLK_SPDIF 338 177c66ec88fSEmmanuel Vadot #define CLK_AC97 339 178c66ec88fSEmmanuel Vadot #define CLK_MODEMIF 340 179c66ec88fSEmmanuel Vadot #define CLK_CHIPID 341 180c66ec88fSEmmanuel Vadot #define CLK_SYSREG 342 181c66ec88fSEmmanuel Vadot #define CLK_HDMI_CEC 343 182c66ec88fSEmmanuel Vadot #define CLK_MCT 344 183c66ec88fSEmmanuel Vadot #define CLK_WDT 345 184c66ec88fSEmmanuel Vadot #define CLK_RTC 346 185c66ec88fSEmmanuel Vadot #define CLK_KEYIF 347 186c66ec88fSEmmanuel Vadot #define CLK_AUDSS 348 187c66ec88fSEmmanuel Vadot #define CLK_MIPI_HSI 349 /* Exynos4210 only */ 188c66ec88fSEmmanuel Vadot #define CLK_PIXELASYNCM0 351 189c66ec88fSEmmanuel Vadot #define CLK_PIXELASYNCM1 352 190c66ec88fSEmmanuel Vadot #define CLK_ASYNC_G3D 353 /* Exynos4x12 only */ 191c66ec88fSEmmanuel Vadot #define CLK_PWM_ISP_SCLK 379 /* Exynos4x12 only */ 192c66ec88fSEmmanuel Vadot #define CLK_SPI0_ISP_SCLK 380 /* Exynos4x12 only */ 193c66ec88fSEmmanuel Vadot #define CLK_SPI1_ISP_SCLK 381 /* Exynos4x12 only */ 194c66ec88fSEmmanuel Vadot #define CLK_UART_ISP_SCLK 382 /* Exynos4x12 only */ 195c66ec88fSEmmanuel Vadot #define CLK_TMU_APBIF 383 196c66ec88fSEmmanuel Vadot 197c66ec88fSEmmanuel Vadot /* mux clocks */ 198c66ec88fSEmmanuel Vadot #define CLK_MOUT_FIMC0 384 199c66ec88fSEmmanuel Vadot #define CLK_MOUT_FIMC1 385 200c66ec88fSEmmanuel Vadot #define CLK_MOUT_FIMC2 386 201c66ec88fSEmmanuel Vadot #define CLK_MOUT_FIMC3 387 202c66ec88fSEmmanuel Vadot #define CLK_MOUT_CAM0 388 203c66ec88fSEmmanuel Vadot #define CLK_MOUT_CAM1 389 204c66ec88fSEmmanuel Vadot #define CLK_MOUT_CSIS0 390 205c66ec88fSEmmanuel Vadot #define CLK_MOUT_CSIS1 391 206c66ec88fSEmmanuel Vadot #define CLK_MOUT_G3D0 392 207c66ec88fSEmmanuel Vadot #define CLK_MOUT_G3D1 393 208c66ec88fSEmmanuel Vadot #define CLK_MOUT_G3D 394 209c66ec88fSEmmanuel Vadot #define CLK_ACLK400_MCUISP 395 /* Exynos4x12 only */ 210c66ec88fSEmmanuel Vadot #define CLK_MOUT_HDMI 396 211c66ec88fSEmmanuel Vadot #define CLK_MOUT_MIXER 397 212*e67e8565SEmmanuel Vadot #define CLK_MOUT_VPLLSRC 398 213c66ec88fSEmmanuel Vadot 214c66ec88fSEmmanuel Vadot /* gate clocks - ppmu */ 215c66ec88fSEmmanuel Vadot #define CLK_PPMULEFT 400 216c66ec88fSEmmanuel Vadot #define CLK_PPMURIGHT 401 217c66ec88fSEmmanuel Vadot #define CLK_PPMUCAMIF 402 218c66ec88fSEmmanuel Vadot #define CLK_PPMUTV 403 219c66ec88fSEmmanuel Vadot #define CLK_PPMUMFC_L 404 220c66ec88fSEmmanuel Vadot #define CLK_PPMUMFC_R 405 221c66ec88fSEmmanuel Vadot #define CLK_PPMUG3D 406 222c66ec88fSEmmanuel Vadot #define CLK_PPMUIMAGE 407 223c66ec88fSEmmanuel Vadot #define CLK_PPMULCD0 408 224c66ec88fSEmmanuel Vadot #define CLK_PPMULCD1 409 /* Exynos4210 only */ 225c66ec88fSEmmanuel Vadot #define CLK_PPMUFILE 410 226c66ec88fSEmmanuel Vadot #define CLK_PPMUGPS 411 227c66ec88fSEmmanuel Vadot #define CLK_PPMUDMC0 412 228c66ec88fSEmmanuel Vadot #define CLK_PPMUDMC1 413 229c66ec88fSEmmanuel Vadot #define CLK_PPMUCPU 414 230c66ec88fSEmmanuel Vadot #define CLK_PPMUACP 415 231c66ec88fSEmmanuel Vadot 232c66ec88fSEmmanuel Vadot /* div clocks */ 233c66ec88fSEmmanuel Vadot #define CLK_DIV_ACLK200 454 /* Exynos4x12 only */ 234c66ec88fSEmmanuel Vadot #define CLK_DIV_ACLK400_MCUISP 455 /* Exynos4x12 only */ 235c66ec88fSEmmanuel Vadot #define CLK_DIV_ACP 456 236c66ec88fSEmmanuel Vadot #define CLK_DIV_DMC 457 237c66ec88fSEmmanuel Vadot #define CLK_DIV_C2C 458 /* Exynos4x12 only */ 238c66ec88fSEmmanuel Vadot #define CLK_DIV_GDL 459 239c66ec88fSEmmanuel Vadot #define CLK_DIV_GDR 460 240*e67e8565SEmmanuel Vadot #define CLK_DIV_CORE2 461 241c66ec88fSEmmanuel Vadot 242c66ec88fSEmmanuel Vadot /* Exynos4x12 ISP clocks */ 243c66ec88fSEmmanuel Vadot #define CLK_ISP_FIMC_ISP 1 244c66ec88fSEmmanuel Vadot #define CLK_ISP_FIMC_DRC 2 245c66ec88fSEmmanuel Vadot #define CLK_ISP_FIMC_FD 3 246c66ec88fSEmmanuel Vadot #define CLK_ISP_FIMC_LITE0 4 247c66ec88fSEmmanuel Vadot #define CLK_ISP_FIMC_LITE1 5 248c66ec88fSEmmanuel Vadot #define CLK_ISP_MCUISP 6 249c66ec88fSEmmanuel Vadot #define CLK_ISP_GICISP 7 250c66ec88fSEmmanuel Vadot #define CLK_ISP_SMMU_ISP 8 251c66ec88fSEmmanuel Vadot #define CLK_ISP_SMMU_DRC 9 252c66ec88fSEmmanuel Vadot #define CLK_ISP_SMMU_FD 10 253c66ec88fSEmmanuel Vadot #define CLK_ISP_SMMU_LITE0 11 254c66ec88fSEmmanuel Vadot #define CLK_ISP_SMMU_LITE1 12 255c66ec88fSEmmanuel Vadot #define CLK_ISP_PPMUISPMX 13 256c66ec88fSEmmanuel Vadot #define CLK_ISP_PPMUISPX 14 257c66ec88fSEmmanuel Vadot #define CLK_ISP_MCUCTL_ISP 15 258c66ec88fSEmmanuel Vadot #define CLK_ISP_MPWM_ISP 16 259c66ec88fSEmmanuel Vadot #define CLK_ISP_I2C0_ISP 17 260c66ec88fSEmmanuel Vadot #define CLK_ISP_I2C1_ISP 18 261c66ec88fSEmmanuel Vadot #define CLK_ISP_MTCADC_ISP 19 262c66ec88fSEmmanuel Vadot #define CLK_ISP_PWM_ISP 20 263c66ec88fSEmmanuel Vadot #define CLK_ISP_WDT_ISP 21 264c66ec88fSEmmanuel Vadot #define CLK_ISP_UART_ISP 22 265c66ec88fSEmmanuel Vadot #define CLK_ISP_ASYNCAXIM 23 266c66ec88fSEmmanuel Vadot #define CLK_ISP_SMMU_ISPCX 24 267c66ec88fSEmmanuel Vadot #define CLK_ISP_SPI0_ISP 25 268c66ec88fSEmmanuel Vadot #define CLK_ISP_SPI1_ISP 26 269c66ec88fSEmmanuel Vadot 270c66ec88fSEmmanuel Vadot #define CLK_ISP_DIV_ISP0 27 271c66ec88fSEmmanuel Vadot #define CLK_ISP_DIV_ISP1 28 272c66ec88fSEmmanuel Vadot #define CLK_ISP_DIV_MCUISP0 29 273c66ec88fSEmmanuel Vadot #define CLK_ISP_DIV_MCUISP1 30 274c66ec88fSEmmanuel Vadot 275c66ec88fSEmmanuel Vadot #endif /* _DT_BINDINGS_CLOCK_EXYNOS_4_H */ 276