1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright 2016 Freescale Semiconductor, Inc.
4  * Copyright 2017 NXP
5  */
6 
7 #ifndef __DT_BINDINGS_CLOCK_IMX8MQ_H
8 #define __DT_BINDINGS_CLOCK_IMX8MQ_H
9 
10 #define IMX8MQ_CLK_DUMMY		0
11 #define IMX8MQ_CLK_32K			1
12 #define IMX8MQ_CLK_25M			2
13 #define IMX8MQ_CLK_27M			3
14 #define IMX8MQ_CLK_EXT1			4
15 #define IMX8MQ_CLK_EXT2			5
16 #define IMX8MQ_CLK_EXT3			6
17 #define IMX8MQ_CLK_EXT4			7
18 
19 /* ANAMIX PLL clocks */
20 /* FRAC PLLs */
21 /* ARM PLL */
22 #define IMX8MQ_ARM_PLL_REF_SEL		8
23 #define IMX8MQ_ARM_PLL_REF_DIV		9
24 #define IMX8MQ_ARM_PLL			10
25 #define IMX8MQ_ARM_PLL_BYPASS		11
26 #define IMX8MQ_ARM_PLL_OUT		12
27 
28 /* GPU PLL */
29 #define IMX8MQ_GPU_PLL_REF_SEL		13
30 #define IMX8MQ_GPU_PLL_REF_DIV		14
31 #define IMX8MQ_GPU_PLL			15
32 #define IMX8MQ_GPU_PLL_BYPASS		16
33 #define IMX8MQ_GPU_PLL_OUT		17
34 
35 /* VPU PLL */
36 #define IMX8MQ_VPU_PLL_REF_SEL		18
37 #define IMX8MQ_VPU_PLL_REF_DIV		19
38 #define IMX8MQ_VPU_PLL			20
39 #define IMX8MQ_VPU_PLL_BYPASS		21
40 #define IMX8MQ_VPU_PLL_OUT		22
41 
42 /* AUDIO PLL1 */
43 #define IMX8MQ_AUDIO_PLL1_REF_SEL	23
44 #define IMX8MQ_AUDIO_PLL1_REF_DIV	24
45 #define IMX8MQ_AUDIO_PLL1		25
46 #define IMX8MQ_AUDIO_PLL1_BYPASS	26
47 #define IMX8MQ_AUDIO_PLL1_OUT		27
48 
49 /* AUDIO PLL2 */
50 #define IMX8MQ_AUDIO_PLL2_REF_SEL	28
51 #define IMX8MQ_AUDIO_PLL2_REF_DIV	29
52 #define IMX8MQ_AUDIO_PLL2		30
53 #define IMX8MQ_AUDIO_PLL2_BYPASS	31
54 #define IMX8MQ_AUDIO_PLL2_OUT		32
55 
56 /* VIDEO PLL1 */
57 #define IMX8MQ_VIDEO_PLL1_REF_SEL	33
58 #define IMX8MQ_VIDEO_PLL1_REF_DIV	34
59 #define IMX8MQ_VIDEO_PLL1		35
60 #define IMX8MQ_VIDEO_PLL1_BYPASS	36
61 #define IMX8MQ_VIDEO_PLL1_OUT		37
62 
63 /* SYS1 PLL */
64 #define IMX8MQ_SYS1_PLL1_REF_SEL	38
65 #define IMX8MQ_SYS1_PLL1_REF_DIV	39
66 #define IMX8MQ_SYS1_PLL1		40
67 #define IMX8MQ_SYS1_PLL1_OUT		41
68 #define IMX8MQ_SYS1_PLL1_OUT_DIV	42
69 #define IMX8MQ_SYS1_PLL2		43
70 #define IMX8MQ_SYS1_PLL2_DIV		44
71 #define IMX8MQ_SYS1_PLL2_OUT		45
72 
73 /* SYS2 PLL */
74 #define IMX8MQ_SYS2_PLL1_REF_SEL	46
75 #define IMX8MQ_SYS2_PLL1_REF_DIV	47
76 #define IMX8MQ_SYS2_PLL1		48
77 #define IMX8MQ_SYS2_PLL1_OUT		49
78 #define IMX8MQ_SYS2_PLL1_OUT_DIV	50
79 #define IMX8MQ_SYS2_PLL2		51
80 #define IMX8MQ_SYS2_PLL2_DIV		52
81 #define IMX8MQ_SYS2_PLL2_OUT		53
82 
83 /* SYS3 PLL */
84 #define IMX8MQ_SYS3_PLL1_REF_SEL	54
85 #define IMX8MQ_SYS3_PLL1_REF_DIV	55
86 #define IMX8MQ_SYS3_PLL1		56
87 #define IMX8MQ_SYS3_PLL1_OUT		57
88 #define IMX8MQ_SYS3_PLL1_OUT_DIV	58
89 #define IMX8MQ_SYS3_PLL2		59
90 #define IMX8MQ_SYS3_PLL2_DIV		60
91 #define IMX8MQ_SYS3_PLL2_OUT		61
92 
93 /* DRAM PLL */
94 #define IMX8MQ_DRAM_PLL1_REF_SEL	62
95 #define IMX8MQ_DRAM_PLL1_REF_DIV	63
96 #define IMX8MQ_DRAM_PLL1		64
97 #define IMX8MQ_DRAM_PLL1_OUT		65
98 #define IMX8MQ_DRAM_PLL1_OUT_DIV	66
99 #define IMX8MQ_DRAM_PLL2		67
100 #define IMX8MQ_DRAM_PLL2_DIV		68
101 #define IMX8MQ_DRAM_PLL2_OUT		69
102 
103 /* SYS PLL DIV */
104 #define IMX8MQ_SYS1_PLL_40M		70
105 #define IMX8MQ_SYS1_PLL_80M		71
106 #define IMX8MQ_SYS1_PLL_100M		72
107 #define IMX8MQ_SYS1_PLL_133M		73
108 #define IMX8MQ_SYS1_PLL_160M		74
109 #define IMX8MQ_SYS1_PLL_200M		75
110 #define IMX8MQ_SYS1_PLL_266M		76
111 #define IMX8MQ_SYS1_PLL_400M		77
112 #define IMX8MQ_SYS1_PLL_800M		78
113 
114 #define IMX8MQ_SYS2_PLL_50M		79
115 #define IMX8MQ_SYS2_PLL_100M		80
116 #define IMX8MQ_SYS2_PLL_125M		81
117 #define IMX8MQ_SYS2_PLL_166M		82
118 #define IMX8MQ_SYS2_PLL_200M		83
119 #define IMX8MQ_SYS2_PLL_250M		84
120 #define IMX8MQ_SYS2_PLL_333M		85
121 #define IMX8MQ_SYS2_PLL_500M		86
122 #define IMX8MQ_SYS2_PLL_1000M		87
123 
124 /* CCM ROOT clocks */
125 /* A53 */
126 #define IMX8MQ_CLK_A53_SRC		88
127 #define IMX8MQ_CLK_A53_CG		89
128 #define IMX8MQ_CLK_A53_DIV		90
129 /* M4 */
130 #define IMX8MQ_CLK_M4_SRC		91
131 #define IMX8MQ_CLK_M4_CG		92
132 #define IMX8MQ_CLK_M4_DIV		93
133 /* VPU */
134 #define IMX8MQ_CLK_VPU_SRC		94
135 #define IMX8MQ_CLK_VPU_CG		95
136 #define IMX8MQ_CLK_VPU_DIV		96
137 /* GPU CORE */
138 #define IMX8MQ_CLK_GPU_CORE_SRC		97
139 #define IMX8MQ_CLK_GPU_CORE_CG		98
140 #define IMX8MQ_CLK_GPU_CORE_DIV		99
141 /* GPU SHADER */
142 #define IMX8MQ_CLK_GPU_SHADER_SRC	100
143 #define IMX8MQ_CLK_GPU_SHADER_CG	101
144 #define IMX8MQ_CLK_GPU_SHADER_DIV	102
145 
146 /* BUS TYPE */
147 /* MAIN AXI */
148 #define IMX8MQ_CLK_MAIN_AXI		103
149 /* ENET AXI */
150 #define IMX8MQ_CLK_ENET_AXI		104
151 /* NAND_USDHC_BUS */
152 #define IMX8MQ_CLK_NAND_USDHC_BUS	105
153 /* VPU BUS */
154 #define IMX8MQ_CLK_VPU_BUS		106
155 /* DISP_AXI */
156 #define IMX8MQ_CLK_DISP_AXI		107
157 /* DISP APB */
158 #define IMX8MQ_CLK_DISP_APB		108
159 /* DISP RTRM */
160 #define IMX8MQ_CLK_DISP_RTRM		109
161 /* USB_BUS */
162 #define IMX8MQ_CLK_USB_BUS		110
163 /* GPU_AXI */
164 #define IMX8MQ_CLK_GPU_AXI		111
165 /* GPU_AHB */
166 #define IMX8MQ_CLK_GPU_AHB		112
167 /* NOC */
168 #define IMX8MQ_CLK_NOC			113
169 /* NOC_APB */
170 #define IMX8MQ_CLK_NOC_APB		115
171 
172 /* AHB */
173 #define IMX8MQ_CLK_AHB			116
174 /* AUDIO AHB */
175 #define IMX8MQ_CLK_AUDIO_AHB		117
176 
177 /* DRAM_ALT */
178 #define IMX8MQ_CLK_DRAM_ALT		118
179 /* DRAM APB */
180 #define IMX8MQ_CLK_DRAM_APB		119
181 /* VPU_G1 */
182 #define IMX8MQ_CLK_VPU_G1		120
183 /* VPU_G2 */
184 #define IMX8MQ_CLK_VPU_G2		121
185 /* DISP_DTRC */
186 #define IMX8MQ_CLK_DISP_DTRC		122
187 /* DISP_DC8000 */
188 #define IMX8MQ_CLK_DISP_DC8000		123
189 /* PCIE_CTRL */
190 #define IMX8MQ_CLK_PCIE1_CTRL		124
191 /* PCIE_PHY */
192 #define IMX8MQ_CLK_PCIE1_PHY		125
193 /* PCIE_AUX */
194 #define IMX8MQ_CLK_PCIE1_AUX		126
195 /* DC_PIXEL */
196 #define IMX8MQ_CLK_DC_PIXEL		127
197 /* LCDIF_PIXEL */
198 #define IMX8MQ_CLK_LCDIF_PIXEL		128
199 /* SAI1~6 */
200 #define IMX8MQ_CLK_SAI1			129
201 
202 #define IMX8MQ_CLK_SAI2			130
203 
204 #define IMX8MQ_CLK_SAI3			131
205 
206 #define IMX8MQ_CLK_SAI4			132
207 
208 #define IMX8MQ_CLK_SAI5			133
209 
210 #define IMX8MQ_CLK_SAI6			134
211 /* SPDIF1 */
212 #define IMX8MQ_CLK_SPDIF1		135
213 /* SPDIF2 */
214 #define IMX8MQ_CLK_SPDIF2		136
215 /* ENET_REF */
216 #define IMX8MQ_CLK_ENET_REF		137
217 /* ENET_TIMER */
218 #define IMX8MQ_CLK_ENET_TIMER		138
219 /* ENET_PHY */
220 #define IMX8MQ_CLK_ENET_PHY_REF		139
221 /* NAND */
222 #define IMX8MQ_CLK_NAND			140
223 /* QSPI */
224 #define IMX8MQ_CLK_QSPI			141
225 /* USDHC1 */
226 #define IMX8MQ_CLK_USDHC1		142
227 /* USDHC2 */
228 #define IMX8MQ_CLK_USDHC2		143
229 /* I2C1 */
230 #define IMX8MQ_CLK_I2C1			144
231 /* I2C2 */
232 #define IMX8MQ_CLK_I2C2			145
233 /* I2C3 */
234 #define IMX8MQ_CLK_I2C3			146
235 /* I2C4 */
236 #define IMX8MQ_CLK_I2C4			147
237 /* UART1 */
238 #define IMX8MQ_CLK_UART1		148
239 /* UART2 */
240 #define IMX8MQ_CLK_UART2		149
241 /* UART3 */
242 #define IMX8MQ_CLK_UART3		150
243 /* UART4 */
244 #define IMX8MQ_CLK_UART4		151
245 /* USB_CORE_REF */
246 #define IMX8MQ_CLK_USB_CORE_REF		152
247 /* USB_PHY_REF */
248 #define IMX8MQ_CLK_USB_PHY_REF		153
249 /* ECSPI1 */
250 #define IMX8MQ_CLK_ECSPI1		154
251 /* ECSPI2 */
252 #define IMX8MQ_CLK_ECSPI2		155
253 /* PWM1 */
254 #define IMX8MQ_CLK_PWM1			156
255 /* PWM2 */
256 #define IMX8MQ_CLK_PWM2			157
257 /* PWM3 */
258 #define IMX8MQ_CLK_PWM3			158
259 /* PWM4 */
260 #define IMX8MQ_CLK_PWM4			159
261 /* GPT1 */
262 #define IMX8MQ_CLK_GPT1			160
263 /* WDOG */
264 #define IMX8MQ_CLK_WDOG			161
265 /* WRCLK */
266 #define IMX8MQ_CLK_WRCLK		162
267 /* DSI_CORE */
268 #define IMX8MQ_CLK_DSI_CORE		163
269 /* DSI_PHY */
270 #define IMX8MQ_CLK_DSI_PHY_REF		164
271 /* DSI_DBI */
272 #define IMX8MQ_CLK_DSI_DBI		165
273 /*DSI_ESC */
274 #define IMX8MQ_CLK_DSI_ESC		166
275 /* CSI1_CORE */
276 #define IMX8MQ_CLK_CSI1_CORE		167
277 /* CSI1_PHY */
278 #define IMX8MQ_CLK_CSI1_PHY_REF		168
279 /* CSI_ESC */
280 #define IMX8MQ_CLK_CSI1_ESC		169
281 /* CSI2_CORE */
282 #define IMX8MQ_CLK_CSI2_CORE		170
283 /* CSI2_PHY */
284 #define IMX8MQ_CLK_CSI2_PHY_REF		171
285 /* CSI2_ESC */
286 #define IMX8MQ_CLK_CSI2_ESC		172
287 /* PCIE2_CTRL */
288 #define IMX8MQ_CLK_PCIE2_CTRL		173
289 /* PCIE2_PHY */
290 #define IMX8MQ_CLK_PCIE2_PHY		174
291 /* PCIE2_AUX */
292 #define IMX8MQ_CLK_PCIE2_AUX		175
293 /* ECSPI3 */
294 #define IMX8MQ_CLK_ECSPI3		176
295 
296 /* CCGR clocks */
297 #define IMX8MQ_CLK_A53_ROOT			177
298 #define IMX8MQ_CLK_DRAM_ROOT			178
299 #define IMX8MQ_CLK_ECSPI1_ROOT			179
300 #define IMX8MQ_CLK_ECSPI2_ROOT			180
301 #define IMX8MQ_CLK_ECSPI3_ROOT			181
302 #define IMX8MQ_CLK_ENET1_ROOT			182
303 #define IMX8MQ_CLK_GPT1_ROOT			183
304 #define IMX8MQ_CLK_I2C1_ROOT			184
305 #define IMX8MQ_CLK_I2C2_ROOT			185
306 #define IMX8MQ_CLK_I2C3_ROOT			186
307 #define IMX8MQ_CLK_I2C4_ROOT			187
308 #define IMX8MQ_CLK_M4_ROOT			188
309 #define IMX8MQ_CLK_PCIE1_ROOT			189
310 #define IMX8MQ_CLK_PCIE2_ROOT			190
311 #define IMX8MQ_CLK_PWM1_ROOT			191
312 #define IMX8MQ_CLK_PWM2_ROOT			192
313 #define IMX8MQ_CLK_PWM3_ROOT			193
314 #define IMX8MQ_CLK_PWM4_ROOT			194
315 #define IMX8MQ_CLK_QSPI_ROOT			195
316 #define IMX8MQ_CLK_SAI1_ROOT			196
317 #define IMX8MQ_CLK_SAI2_ROOT			197
318 #define IMX8MQ_CLK_SAI3_ROOT			198
319 #define IMX8MQ_CLK_SAI4_ROOT			199
320 #define IMX8MQ_CLK_SAI5_ROOT			200
321 #define IMX8MQ_CLK_SAI6_ROOT			201
322 #define IMX8MQ_CLK_UART1_ROOT			202
323 #define IMX8MQ_CLK_UART2_ROOT			203
324 #define IMX8MQ_CLK_UART3_ROOT			204
325 #define IMX8MQ_CLK_UART4_ROOT			205
326 #define IMX8MQ_CLK_USB1_CTRL_ROOT		206
327 #define IMX8MQ_CLK_USB2_CTRL_ROOT		207
328 #define IMX8MQ_CLK_USB1_PHY_ROOT		208
329 #define IMX8MQ_CLK_USB2_PHY_ROOT		209
330 #define IMX8MQ_CLK_USDHC1_ROOT			210
331 #define IMX8MQ_CLK_USDHC2_ROOT			211
332 #define IMX8MQ_CLK_WDOG1_ROOT			212
333 #define IMX8MQ_CLK_WDOG2_ROOT			213
334 #define IMX8MQ_CLK_WDOG3_ROOT			214
335 #define IMX8MQ_CLK_GPU_ROOT			215
336 #define IMX8MQ_CLK_HEVC_ROOT			216
337 #define IMX8MQ_CLK_AVC_ROOT			217
338 #define IMX8MQ_CLK_VP9_ROOT			218
339 #define IMX8MQ_CLK_HEVC_INTER_ROOT		219
340 #define IMX8MQ_CLK_DISP_ROOT			220
341 #define IMX8MQ_CLK_HDMI_ROOT			221
342 #define IMX8MQ_CLK_HDMI_PHY_ROOT		222
343 #define IMX8MQ_CLK_VPU_DEC_ROOT			223
344 #define IMX8MQ_CLK_CSI1_ROOT			224
345 #define IMX8MQ_CLK_CSI2_ROOT			225
346 #define IMX8MQ_CLK_RAWNAND_ROOT			226
347 #define IMX8MQ_CLK_SDMA1_ROOT			227
348 #define IMX8MQ_CLK_SDMA2_ROOT			228
349 #define IMX8MQ_CLK_VPU_G1_ROOT			229
350 #define IMX8MQ_CLK_VPU_G2_ROOT			230
351 
352 /* SCCG PLL GATE */
353 #define IMX8MQ_SYS1_PLL_OUT			231
354 #define IMX8MQ_SYS2_PLL_OUT			232
355 #define IMX8MQ_SYS3_PLL_OUT			233
356 #define IMX8MQ_DRAM_PLL_OUT			234
357 
358 #define IMX8MQ_GPT_3M_CLK			235
359 
360 #define IMX8MQ_CLK_IPG_ROOT			236
361 #define IMX8MQ_CLK_IPG_AUDIO_ROOT		237
362 #define IMX8MQ_CLK_SAI1_IPG			238
363 #define IMX8MQ_CLK_SAI2_IPG			239
364 #define IMX8MQ_CLK_SAI3_IPG			240
365 #define IMX8MQ_CLK_SAI4_IPG			241
366 #define IMX8MQ_CLK_SAI5_IPG			242
367 #define IMX8MQ_CLK_SAI6_IPG			243
368 
369 /* DSI AHB/IPG clocks */
370 /* rxesc clock */
371 #define IMX8MQ_CLK_DSI_AHB			244
372 /* txesc clock */
373 #define IMX8MQ_CLK_DSI_IPG_DIV                  245
374 
375 #define IMX8MQ_CLK_TMU_ROOT			246
376 
377 /* Display root clocks */
378 #define IMX8MQ_CLK_DISP_AXI_ROOT		247
379 #define IMX8MQ_CLK_DISP_APB_ROOT		248
380 #define IMX8MQ_CLK_DISP_RTRM_ROOT		249
381 
382 #define IMX8MQ_CLK_OCOTP_ROOT			250
383 
384 #define IMX8MQ_CLK_DRAM_ALT_ROOT		251
385 #define IMX8MQ_CLK_DRAM_CORE			252
386 
387 #define IMX8MQ_CLK_MU_ROOT			253
388 #define IMX8MQ_VIDEO2_PLL_OUT			254
389 
390 #define IMX8MQ_CLK_CLKO2			255
391 
392 #define IMX8MQ_CLK_NAND_USDHC_BUS_RAWNAND_CLK	256
393 
394 #define IMX8MQ_CLK_CLKO1			257
395 #define IMX8MQ_CLK_ARM				258
396 
397 #define IMX8MQ_CLK_GPIO1_ROOT			259
398 #define IMX8MQ_CLK_GPIO2_ROOT			260
399 #define IMX8MQ_CLK_GPIO3_ROOT			261
400 #define IMX8MQ_CLK_GPIO4_ROOT			262
401 #define IMX8MQ_CLK_GPIO5_ROOT			263
402 
403 #define IMX8MQ_CLK_SNVS_ROOT			264
404 #define IMX8MQ_CLK_GIC				265
405 
406 #define IMX8MQ_VIDEO2_PLL1_REF_SEL		266
407 
408 #define IMX8MQ_SYS1_PLL_40M_CG			267
409 #define IMX8MQ_SYS1_PLL_80M_CG			268
410 #define IMX8MQ_SYS1_PLL_100M_CG			269
411 #define IMX8MQ_SYS1_PLL_133M_CG			270
412 #define IMX8MQ_SYS1_PLL_160M_CG			271
413 #define IMX8MQ_SYS1_PLL_200M_CG			272
414 #define IMX8MQ_SYS1_PLL_266M_CG			273
415 #define IMX8MQ_SYS1_PLL_400M_CG			274
416 #define IMX8MQ_SYS1_PLL_800M_CG			275
417 #define IMX8MQ_SYS2_PLL_50M_CG			276
418 #define IMX8MQ_SYS2_PLL_100M_CG			277
419 #define IMX8MQ_SYS2_PLL_125M_CG			278
420 #define IMX8MQ_SYS2_PLL_166M_CG			279
421 #define IMX8MQ_SYS2_PLL_200M_CG			280
422 #define IMX8MQ_SYS2_PLL_250M_CG			281
423 #define IMX8MQ_SYS2_PLL_333M_CG			282
424 #define IMX8MQ_SYS2_PLL_500M_CG			283
425 #define IMX8MQ_SYS2_PLL_1000M_CG		284
426 
427 #define IMX8MQ_CLK_GPU_CORE			285
428 #define IMX8MQ_CLK_GPU_SHADER			286
429 #define IMX8MQ_CLK_M4_CORE			287
430 #define IMX8MQ_CLK_VPU_CORE			288
431 
432 #define IMX8MQ_CLK_A53_CORE			289
433 
434 #define IMX8MQ_CLK_MON_AUDIO_PLL1_DIV		290
435 #define IMX8MQ_CLK_MON_AUDIO_PLL2_DIV		291
436 #define IMX8MQ_CLK_MON_VIDEO_PLL1_DIV		292
437 #define IMX8MQ_CLK_MON_GPU_PLL_DIV		293
438 #define IMX8MQ_CLK_MON_VPU_PLL_DIV		294
439 #define IMX8MQ_CLK_MON_ARM_PLL_DIV		295
440 #define IMX8MQ_CLK_MON_SYS_PLL1_DIV		296
441 #define IMX8MQ_CLK_MON_SYS_PLL2_DIV		297
442 #define IMX8MQ_CLK_MON_SYS_PLL3_DIV		298
443 #define IMX8MQ_CLK_MON_DRAM_PLL_DIV		299
444 #define IMX8MQ_CLK_MON_VIDEO_PLL2_DIV		300
445 #define IMX8MQ_CLK_MON_SEL			301
446 #define IMX8MQ_CLK_MON_CLK2_OUT			302
447 
448 #define IMX8MQ_CLK_END				303
449 
450 #endif /* __DT_BINDINGS_CLOCK_IMX8MQ_H */
451