1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */ 3 4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H 6 7 /** @brief output of gate CLK_ENB_FUSE */ 8 #define TEGRA234_CLK_FUSE 40 9 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */ 10 #define TEGRA234_CLK_SDMMC4 123 11 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */ 12 #define TEGRA234_CLK_UARTA 155 13 14 #endif 15