1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2022, NVIDIA CORPORATION. All rights reserved. */
3 
4 #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
5 #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
6 
7 /**
8  * @file
9  * @defgroup bpmp_clock_ids Clock ID's
10  * @{
11  */
12 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
13 #define TEGRA234_CLK_AHUB			4U
14 /** @brief output of gate CLK_ENB_APB2APE */
15 #define TEGRA234_CLK_APB2APE			5U
16 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
17 #define TEGRA234_CLK_APE			6U
18 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
19 #define TEGRA234_CLK_AUD_MCLK			7U
20 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
21 #define TEGRA234_CLK_DMIC1			15U
22 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
23 #define TEGRA234_CLK_DMIC2			16U
24 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
25 #define TEGRA234_CLK_DMIC3			17U
26 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
27 #define TEGRA234_CLK_DMIC4			18U
28 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
29 #define TEGRA234_CLK_DSPK1			29U
30 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
31 #define TEGRA234_CLK_DSPK2			30U
32 /**
33  * @brief controls the EMC clock frequency.
34  * @details Doing a clk_set_rate on this clock will select the
35  * appropriate clock source, program the source rate and execute a
36  * specific sequence to switch to the new clock source for both memory
37  * controllers. This can be used to control the balance between memory
38  * throughput and memory controller power.
39  */
40 #define TEGRA234_CLK_EMC			31U
41 /** @brief output of gate CLK_ENB_FUSE */
42 #define TEGRA234_CLK_FUSE			40U
43 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C1 */
44 #define TEGRA234_CLK_I2C1			48U
45 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
46 #define TEGRA234_CLK_I2C2			49U
47 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
48 #define TEGRA234_CLK_I2C3			50U
49 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
50 #define TEGRA234_CLK_I2C4			51U
51 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
52 #define TEGRA234_CLK_I2C6			52U
53 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
54 #define TEGRA234_CLK_I2C7			53U
55 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
56 #define TEGRA234_CLK_I2C8			54U
57 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
58 #define TEGRA234_CLK_I2C9			55U
59 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
60 #define TEGRA234_CLK_I2S1			56U
61 /** @brief clock recovered from I2S1 input */
62 #define TEGRA234_CLK_I2S1_SYNC_INPUT		57U
63 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
64 #define TEGRA234_CLK_I2S2			58U
65 /** @brief clock recovered from I2S2 input */
66 #define TEGRA234_CLK_I2S2_SYNC_INPUT		59U
67 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
68 #define TEGRA234_CLK_I2S3			60U
69 /** @brief clock recovered from I2S3 input */
70 #define TEGRA234_CLK_I2S3_SYNC_INPUT		61U
71 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
72 #define TEGRA234_CLK_I2S4			62U
73 /** @brief clock recovered from I2S4 input */
74 #define TEGRA234_CLK_I2S4_SYNC_INPUT		63U
75 /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
76 #define TEGRA234_CLK_I2S5			64U
77 /** @brief clock recovered from I2S5 input */
78 #define TEGRA234_CLK_I2S5_SYNC_INPUT		65U
79 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S6 */
80 #define TEGRA234_CLK_I2S6			66U
81 /** @brief clock recovered from I2S6 input */
82 #define TEGRA234_CLK_I2S6_SYNC_INPUT		67U
83 /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
84 #define TEGRA234_CLK_PLLA			93U
85 /** @brief PLLP clk output */
86 #define TEGRA234_CLK_PLLP_OUT0			102U
87 /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
88 #define TEGRA234_CLK_PLLA_OUT0			104U
89 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
90 #define TEGRA234_CLK_PWM1			105U
91 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
92 #define TEGRA234_CLK_PWM2			106U
93 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
94 #define TEGRA234_CLK_PWM3			107U
95 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
96 #define TEGRA234_CLK_PWM4			108U
97 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
98 #define TEGRA234_CLK_PWM5			109U
99 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
100 #define TEGRA234_CLK_PWM6			110U
101 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
102 #define TEGRA234_CLK_PWM7			111U
103 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
104 #define TEGRA234_CLK_PWM8			112U
105 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
106 #define TEGRA234_CLK_SDMMC4			123U
107 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
108 #define TEGRA234_CLK_SYNC_DMIC1			139U
109 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
110 #define TEGRA234_CLK_SYNC_DMIC2			140U
111 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
112 #define TEGRA234_CLK_SYNC_DMIC3			141U
113 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
114 #define TEGRA234_CLK_SYNC_DMIC4			142U
115 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
116 #define TEGRA234_CLK_SYNC_DSPK1			143U
117 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
118 #define TEGRA234_CLK_SYNC_DSPK2			144U
119 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
120 #define TEGRA234_CLK_SYNC_I2S1			145U
121 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
122 #define TEGRA234_CLK_SYNC_I2S2			146U
123 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
124 #define TEGRA234_CLK_SYNC_I2S3			147U
125 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
126 #define TEGRA234_CLK_SYNC_I2S4			148U
127 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
128 #define TEGRA234_CLK_SYNC_I2S5			149U
129 /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
130 #define TEGRA234_CLK_SYNC_I2S6			150U
131 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
132 #define TEGRA234_CLK_UARTA			155U
133 /** @brief output of gate CLK_ENB_PEX1_CORE_6 */
134 #define TEGRA234_CLK_PEX1_C6_CORE		161U
135 /** @brief output of gate CLK_ENB_PEX2_CORE_7 */
136 #define TEGRA234_CLK_PEX2_C7_CORE		171U
137 /** @brief output of gate CLK_ENB_PEX2_CORE_8 */
138 #define TEGRA234_CLK_PEX2_C8_CORE		172U
139 /** @brief output of gate CLK_ENB_PEX2_CORE_9 */
140 #define TEGRA234_CLK_PEX2_C9_CORE		173U
141 /** @brief output of gate CLK_ENB_PEX2_CORE_10 */
142 #define TEGRA234_CLK_PEX2_C10_CORE		187U
143 /** @brief CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM switch divider output */
144 #define TEGRA234_CLK_SDMMC_LEGACY_TM		219U
145 /** @brief output of gate CLK_ENB_PEX0_CORE_0 */
146 #define TEGRA234_CLK_PEX0_C0_CORE		220U
147 /** @brief output of gate CLK_ENB_PEX0_CORE_1 */
148 #define TEGRA234_CLK_PEX0_C1_CORE		221U
149 /** @brief output of gate CLK_ENB_PEX0_CORE_2 */
150 #define TEGRA234_CLK_PEX0_C2_CORE		222U
151 /** @brief output of gate CLK_ENB_PEX0_CORE_3 */
152 #define TEGRA234_CLK_PEX0_C3_CORE		223U
153 /** @brief output of gate CLK_ENB_PEX0_CORE_4 */
154 #define TEGRA234_CLK_PEX0_C4_CORE		224U
155 /** @brief output of gate CLK_ENB_PEX1_CORE_5 */
156 #define TEGRA234_CLK_PEX1_C5_CORE		225U
157 /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
158 #define TEGRA234_CLK_PLLC4			237U
159 /** @brief 32K input clock provided by PMIC */
160 #define TEGRA234_CLK_CLK_32K			289U
161 /** @brief CLK_RST_CONTROLLER_AZA2XBITCLK_OUT_SWITCH_DIVIDER switch divider output (aza_2xbitclk) */
162 #define TEGRA234_CLK_AZA_2XBIT			457U
163 /** @brief aza_2xbitclk / 2 (aza_bitclk) */
164 #define TEGRA234_CLK_AZA_BIT			458U
165 #endif
166