1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright 2022 Fabio Estevam <festevam@denx.de>
4 */
5
6/dts-v1/;
7
8#include "imx8mm-tqma8mqml.dtsi"
9
10/ {
11	model = "Cloos i.MX8MM PHG board";
12	compatible = "cloos,imx8mm-phg", "tq,imx8mm-tqma8mqml", "fsl,imx8mm";
13
14	aliases {
15		mmc0 = &usdhc3;
16		mmc1 = &usdhc2;
17	};
18
19	chosen {
20		stdout-path = &uart2;
21	};
22
23	beeper {
24		compatible = "gpio-beeper";
25		pinctrl-0 = <&pinctrl_beeper>;
26		gpios = <&gpio1 0 GPIO_ACTIVE_HIGH>;
27	};
28
29	leds {
30		compatible = "gpio-leds";
31		pinctrl-names = "default";
32		pinctrl-0 = <&pinctrl_gpio_led>;
33
34		led-0 {
35			label = "status1";
36			gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>;
37		};
38
39		led-1 {
40			label = "status2";
41			gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>;
42		};
43
44		led-2 {
45			label = "status3";
46			gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
47		};
48
49		led-3 {
50			label = "run";
51			gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
52		};
53
54		led-4 {
55			label = "powerled";
56			gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>;
57		};
58	};
59
60	reg_usb_otg_vbus: regulator-usb-otg-vbus {
61		compatible = "regulator-fixed";
62		pinctrl-names = "default";
63		pinctrl-0 = <&pinctrl_otg_vbus_ctrl>;
64		regulator-name = "usb_otg_vbus";
65		regulator-min-microvolt = <5000000>;
66		regulator-max-microvolt = <5000000>;
67		gpio = <&gpio2 2 GPIO_ACTIVE_HIGH>;
68		enable-active-high;
69	};
70
71	reg_usdhc2_vmmc: regulator-vmmc {
72		compatible = "regulator-fixed";
73		pinctrl-names = "default";
74		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
75		regulator-name = "VSD_3V3";
76		regulator-min-microvolt = <3300000>;
77		regulator-max-microvolt = <3300000>;
78		gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
79		enable-active-high;
80		startup-delay-us = <100>;
81		off-on-delay-us = <12000>;
82	};
83};
84
85&ecspi1 {
86	pinctrl-names = "default";
87	pinctrl-0 = <&pinctrl_ecspi1>;
88	cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
89	status = "okay";
90};
91
92&fec1 {
93	pinctrl-names = "default";
94	pinctrl-0 = <&pinctrl_fec1>;
95	phy-mode = "rgmii-id";
96	phy-handle = <&ethphy0>;
97	fsl,magic-packet;
98	status = "okay";
99
100	mdio {
101		#address-cells = <1>;
102		#size-cells = <0>;
103
104		ethphy0: ethernet-phy@0 {
105			reg = <0>;
106			compatible = "ethernet-phy-ieee802.3-c22";
107		};
108	};
109};
110
111&i2c2 {
112	clock-frequency = <100000>;
113	pinctrl-names = "default";
114	pinctrl-0 = <&pinctrl_i2c2>;
115	status = "okay";
116};
117
118&uart2 {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_uart2>;
121	status = "okay";
122};
123
124&usbphynop1 {
125	power-domains = <&pgc_otg1>;
126};
127
128&usbphynop2 {
129	power-domains = <&pgc_otg2>;
130};
131
132&usbotg1 {
133	dr_mode = "host";
134	vbus-supply = <&reg_usb_otg_vbus>;
135	status = "okay";
136};
137
138&usbotg2 {
139	dr_mode = "host";
140	status = "okay";
141};
142
143&usdhc2 {
144	assigned-clocks = <&clk IMX8MM_CLK_USDHC2>;
145	assigned-clock-rates = <400000000>;
146	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_400M>;
147	pinctrl-names = "default", "state_100mhz", "state_200mhz";
148	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
149	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
150	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
151	bus-width = <4>;
152	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
153	disable-wp;
154	no-mmc;
155	no-sdio;
156	sd-uhs-sdr104;
157	sd-uhs-ddr50;
158	vmmc-supply = <&reg_usdhc2_vmmc>;
159	status = "okay";
160};
161
162&iomuxc {
163	pinctrl_beeper: beepergrp {
164		fsl,pins = <
165			MX8MM_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x19
166		>;
167	};
168
169	pinctrl_ecspi1: ecspi1grp {
170		fsl,pins = <
171			MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x82
172			MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x82
173			MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x82
174			MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9		0x19
175		>;
176	};
177
178	pinctrl_fec1: fec1grp {
179		fsl,pins = <
180			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC		0x40000002
181			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x40000002
182			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x14
183			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x14
184			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x14
185			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x14
186			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x90
187			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x90
188			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x90
189			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x90
190			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x14
191			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x90
192			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x90
193			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x14
194			MX8MM_IOMUXC_SAI2_RXC_GPIO4_IO22		0x10
195		>;
196	};
197
198	pinctrl_gpio_led: gpioledgrp {
199		fsl,pins = <
200			MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10		0x19
201			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x19
202			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
203			MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7		0x19
204			MX8MM_IOMUXC_GPIO1_IO01_GPIO1_IO1		0x19
205		>;
206	};
207
208	pinctrl_i2c2: i2c2grp {
209		fsl,pins = <
210			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
211			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
212		>;
213	};
214
215	pinctrl_otg_vbus_ctrl: otgvbusctrlgrp {
216		fsl,pins = <
217			MX8MM_IOMUXC_SD1_DATA0_GPIO2_IO2		0x119
218		>;
219	};
220
221	pinctrl_uart2: uart2grp {
222		fsl,pins = <
223			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX		0x140
224			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX		0x140
225		>;
226	};
227
228	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
229		fsl,pins = <
230			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12		0x1c4
231		>;
232	};
233
234	pinctrl_usdhc2: usdhc2grp {
235		fsl,pins = <
236			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
237			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
238			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d0
239			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d0
240			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d0
241			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d0
242		>;
243	};
244
245	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
246		fsl,pins = <
247			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
248			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
249			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d4
250			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d4
251			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d4
252			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d4
253		>;
254	};
255
256	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
257		fsl,pins = <
258			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
259			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
260			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0		0x1d6
261			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1		0x1d6
262			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2		0x1d6
263			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3		0x1d6
264		>;
265	};
266};
267