1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Device Tree Include file for Marvell Armada 37xx family of SoCs.
4 *
5 * Copyright (C) 2016 Marvell
6 *
7 * Gregory CLEMENT <gregory.clement@free-electrons.com>
8 *
9 */
10
11#include <dt-bindings/interrupt-controller/arm-gic.h>
12
13/ {
14	model = "Marvell Armada 37xx SoC";
15	compatible = "marvell,armada3700";
16	interrupt-parent = <&gic>;
17	#address-cells = <2>;
18	#size-cells = <2>;
19
20	aliases {
21		serial0 = &uart0;
22		serial1 = &uart1;
23	};
24
25	reserved-memory {
26		#address-cells = <2>;
27		#size-cells = <2>;
28		ranges;
29
30		/*
31		 * The PSCI firmware region depicted below is the default one
32		 * and should be updated by the bootloader.
33		 */
34		psci-area@4000000 {
35			reg = <0 0x4000000 0 0x200000>;
36			no-map;
37		};
38
39		tee@4400000 {
40			reg = <0 0x4400000 0 0x1000000>;
41			no-map;
42		};
43	};
44
45	cpus {
46		#address-cells = <1>;
47		#size-cells = <0>;
48		cpu0: cpu@0 {
49			device_type = "cpu";
50			compatible = "arm,cortex-a53";
51			reg = <0>;
52			clocks = <&nb_periph_clk 16>;
53			enable-method = "psci";
54		};
55	};
56
57	psci {
58		compatible = "arm,psci-0.2";
59		method = "smc";
60	};
61
62	timer {
63		compatible = "arm,armv8-timer";
64		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
65			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
66			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
67			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
68	};
69
70	pmu {
71		compatible = "arm,armv8-pmuv3";
72		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
73	};
74
75	soc {
76		compatible = "simple-bus";
77		#address-cells = <2>;
78		#size-cells = <2>;
79		ranges;
80
81		internal-regs@d0000000 {
82			#address-cells = <1>;
83			#size-cells = <1>;
84			compatible = "simple-bus";
85			/* 32M internal register @ 0xd000_0000 */
86			ranges = <0x0 0x0 0xd0000000 0x2000000>;
87
88			wdt: watchdog@8300 {
89				compatible = "marvell,armada-3700-wdt";
90				reg = <0x8300 0x40>;
91				marvell,system-controller = <&cpu_misc>;
92				clocks = <&xtalclk>;
93			};
94
95			cpu_misc: system-controller@d000 {
96				compatible = "marvell,armada-3700-cpu-misc",
97					     "syscon";
98				reg = <0xd000 0x1000>;
99			};
100
101			spi0: spi@10600 {
102				compatible = "marvell,armada-3700-spi";
103				#address-cells = <1>;
104				#size-cells = <0>;
105				reg = <0x10600 0xA00>;
106				clocks = <&nb_periph_clk 7>;
107				interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
108				num-cs = <4>;
109				status = "disabled";
110			};
111
112			i2c0: i2c@11000 {
113				compatible = "marvell,armada-3700-i2c";
114				reg = <0x11000 0x24>;
115				#address-cells = <1>;
116				#size-cells = <0>;
117				clocks = <&nb_periph_clk 10>;
118				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
119				mrvl,i2c-fast-mode;
120				status = "disabled";
121			};
122
123			i2c1: i2c@11080 {
124				compatible = "marvell,armada-3700-i2c";
125				reg = <0x11080 0x24>;
126				#address-cells = <1>;
127				#size-cells = <0>;
128				clocks = <&nb_periph_clk 9>;
129				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
130				mrvl,i2c-fast-mode;
131				status = "disabled";
132			};
133
134			avs: avs@11500 {
135				compatible = "marvell,armada-3700-avs",
136					     "syscon";
137				reg = <0x11500 0x40>;
138			};
139
140			uartclk: clock-controller@12010 {
141				compatible = "marvell,armada-3700-uart-clock";
142				reg = <0x12010 0x4>, <0x12210 0x4>;
143				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
144					 <&tbg 3>, <&xtalclk>;
145				clock-names = "TBG-A-P", "TBG-B-P", "TBG-A-S",
146					      "TBG-B-S", "xtal";
147				#clock-cells = <1>;
148			};
149
150			uart0: serial@12000 {
151				compatible = "marvell,armada-3700-uart";
152				reg = <0x12000 0x18>;
153				clocks = <&uartclk 0>;
154				interrupts =
155				<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
156				<GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
157				<GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
158				interrupt-names = "uart-sum", "uart-tx", "uart-rx";
159				status = "disabled";
160			};
161
162			uart1: serial@12200 {
163				compatible = "marvell,armada-3700-uart-ext";
164				reg = <0x12200 0x30>;
165				clocks = <&uartclk 1>;
166				interrupts =
167				<GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
168				<GIC_SPI 31 IRQ_TYPE_EDGE_RISING>;
169				interrupt-names = "uart-tx", "uart-rx";
170				status = "disabled";
171			};
172
173			nb_periph_clk: nb-periph-clk@13000 {
174				compatible = "marvell,armada-3700-periph-clock-nb",
175					     "syscon";
176				reg = <0x13000 0x100>;
177				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
178				<&tbg 3>, <&xtalclk>;
179				#clock-cells = <1>;
180			};
181
182			sb_periph_clk: sb-periph-clk@18000 {
183				compatible = "marvell,armada-3700-periph-clock-sb";
184				reg = <0x18000 0x100>;
185				clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
186				<&tbg 3>, <&xtalclk>;
187				#clock-cells = <1>;
188			};
189
190			tbg: tbg@13200 {
191				compatible = "marvell,armada-3700-tbg-clock";
192				reg = <0x13200 0x100>;
193				clocks = <&xtalclk>;
194				#clock-cells = <1>;
195			};
196
197			pinctrl_nb: pinctrl@13800 {
198				compatible = "marvell,armada3710-nb-pinctrl",
199					     "syscon", "simple-mfd";
200				reg = <0x13800 0x100>, <0x13C00 0x20>;
201				/* MPP1[19:0] */
202				gpionb: gpio {
203					#gpio-cells = <2>;
204					gpio-ranges = <&pinctrl_nb 0 0 36>;
205					gpio-controller;
206					interrupt-controller;
207					#interrupt-cells = <2>;
208					interrupts =
209					<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
210					<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
211					<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
212					<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
213					<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
214					<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
215					<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
216					<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
217					<GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>,
218					<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
219					<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>,
220					<GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
221				};
222
223				xtalclk: xtal-clk {
224					compatible = "marvell,armada-3700-xtal-clock";
225					clock-output-names = "xtal";
226					#clock-cells = <0>;
227				};
228
229				spi_quad_pins: spi-quad-pins {
230					groups = "spi_quad";
231					function = "spi";
232				};
233
234				spi_cs1_pins: spi-cs1-pins {
235					groups = "spi_cs1";
236					function = "spi";
237				};
238
239				i2c1_pins: i2c1-pins {
240					groups = "i2c1";
241					function = "i2c";
242				};
243
244				i2c2_pins: i2c2-pins {
245					groups = "i2c2";
246					function = "i2c";
247				};
248
249				uart1_pins: uart1-pins {
250					groups = "uart1";
251					function = "uart";
252				};
253
254				uart2_pins: uart2-pins {
255					groups = "uart2";
256					function = "uart";
257				};
258
259				mmc_pins: mmc-pins {
260					groups = "emmc_nb";
261					function = "emmc";
262				};
263			};
264
265			nb_pm: syscon@14000 {
266				compatible = "marvell,armada-3700-nb-pm",
267					     "syscon";
268				reg = <0x14000 0x60>;
269			};
270
271			comphy: phy@18300 {
272				compatible = "marvell,comphy-a3700";
273				reg = <0x18300 0x300>,
274				      <0x1F000 0x400>,
275				      <0x5C000 0x400>,
276				      <0xe0178 0x8>;
277				reg-names = "comphy",
278					    "lane1_pcie_gbe",
279					    "lane0_usb3_gbe",
280					    "lane2_sata_usb3";
281				#address-cells = <1>;
282				#size-cells = <0>;
283				clocks = <&xtalclk>;
284				clock-names = "xtal";
285
286				comphy0: phy@0 {
287					reg = <0>;
288					#phy-cells = <1>;
289				};
290
291				comphy1: phy@1 {
292					reg = <1>;
293					#phy-cells = <1>;
294				};
295
296				comphy2: phy@2 {
297					reg = <2>;
298					#phy-cells = <1>;
299				};
300			};
301
302			pinctrl_sb: pinctrl@18800 {
303				compatible = "marvell,armada3710-sb-pinctrl",
304					     "syscon", "simple-mfd";
305				reg = <0x18800 0x100>, <0x18C00 0x20>;
306				/* MPP2[23:0] */
307				gpiosb: gpio {
308					#gpio-cells = <2>;
309					gpio-ranges = <&pinctrl_sb 0 0 30>;
310					gpio-controller;
311					interrupt-controller;
312					#interrupt-cells = <2>;
313					interrupts =
314					<GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
315					<GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
316					<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
317					<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
318					<GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
319				};
320
321				rgmii_pins: mii-pins {
322					groups = "rgmii";
323					function = "mii";
324				};
325
326				smi_pins: smi-pins {
327					groups = "smi";
328					function = "smi";
329				};
330
331				sdio_pins: sdio-pins {
332					groups = "sdio_sb";
333					function = "sdio";
334				};
335
336				pcie_reset_pins: pcie-reset-pins {
337					groups = "pcie1"; /* this actually controls "pcie1_reset" */
338					function = "gpio";
339				};
340
341				pcie_clkreq_pins: pcie-clkreq-pins {
342					groups = "pcie1_clkreq";
343					function = "pcie";
344				};
345			};
346
347			eth0: ethernet@30000 {
348				   compatible = "marvell,armada-3700-neta";
349				   reg = <0x30000 0x4000>;
350				   interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
351				   clocks = <&sb_periph_clk 8>;
352				   status = "disabled";
353			};
354
355			mdio: mdio@32004 {
356				#address-cells = <1>;
357				#size-cells = <0>;
358				compatible = "marvell,orion-mdio";
359				reg = <0x32004 0x4>;
360			};
361
362			eth1: ethernet@40000 {
363				compatible = "marvell,armada-3700-neta";
364				reg = <0x40000 0x4000>;
365				interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
366				clocks = <&sb_periph_clk 7>;
367				status = "disabled";
368			};
369
370			usb3: usb@58000 {
371				compatible = "marvell,armada3700-xhci",
372				"generic-xhci";
373				reg = <0x58000 0x4000>;
374				marvell,usb-misc-reg = <&usb32_syscon>;
375				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
376				clocks = <&sb_periph_clk 12>;
377				phys = <&comphy0 0>, <&usb2_utmi_otg_phy>;
378				phy-names = "usb3-phy", "usb2-utmi-otg-phy";
379				status = "disabled";
380			};
381
382			usb2_utmi_otg_phy: phy@5d000 {
383				compatible = "marvell,a3700-utmi-otg-phy";
384				reg = <0x5d000 0x800>;
385				marvell,usb-misc-reg = <&usb32_syscon>;
386				#phy-cells = <0>;
387			};
388
389			usb32_syscon: system-controller@5d800 {
390				compatible = "marvell,armada-3700-usb2-host-device-misc",
391				"syscon";
392				reg = <0x5d800 0x800>;
393			};
394
395			usb2: usb@5e000 {
396				compatible = "marvell,armada-3700-ehci";
397				reg = <0x5e000 0x1000>;
398				marvell,usb-misc-reg = <&usb2_syscon>;
399				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
400				phys = <&usb2_utmi_host_phy>;
401				phy-names = "usb2-utmi-host-phy";
402				status = "disabled";
403			};
404
405			usb2_utmi_host_phy: phy@5f000 {
406				compatible = "marvell,a3700-utmi-host-phy";
407				reg = <0x5f000 0x800>;
408				marvell,usb-misc-reg = <&usb2_syscon>;
409				#phy-cells = <0>;
410			};
411
412			usb2_syscon: system-controller@5f800 {
413				compatible = "marvell,armada-3700-usb2-host-misc",
414				"syscon";
415				reg = <0x5f800 0x800>;
416			};
417
418			xor@60900 {
419				compatible = "marvell,armada-3700-xor";
420				reg = <0x60900 0x100>,
421				      <0x60b00 0x100>;
422
423				xor10 {
424					interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
425				};
426				xor11 {
427					interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
428				};
429			};
430
431			crypto: crypto@90000 {
432				compatible = "inside-secure,safexcel-eip97ies";
433				reg = <0x90000 0x20000>;
434				interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
435					     <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
436					     <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
437					     <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>,
438					     <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>,
439					     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
440				interrupt-names = "mem", "ring0", "ring1",
441						  "ring2", "ring3", "eip";
442				clocks = <&nb_periph_clk 15>;
443			};
444
445			rwtm: mailbox@b0000 {
446				compatible = "marvell,armada-3700-rwtm-mailbox";
447				reg = <0xb0000 0x100>;
448				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
449				#mbox-cells = <1>;
450			};
451
452			sdhci1: mmc@d0000 {
453				compatible = "marvell,armada-3700-sdhci",
454					     "marvell,sdhci-xenon";
455				reg = <0xd0000 0x300>,
456				      <0x1e808 0x4>;
457				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
458				clocks = <&nb_periph_clk 0>;
459				clock-names = "core";
460				status = "disabled";
461			};
462
463			sdhci0: mmc@d8000 {
464				compatible = "marvell,armada-3700-sdhci",
465					     "marvell,sdhci-xenon";
466				reg = <0xd8000 0x300>,
467				      <0x17808 0x4>;
468				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
469				clocks = <&nb_periph_clk 0>;
470				clock-names = "core";
471				status = "disabled";
472			};
473
474			sata: sata@e0000 {
475				compatible = "marvell,armada-3700-ahci";
476				reg = <0xe0000 0x178>;
477				interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
478				clocks = <&nb_periph_clk 1>;
479				phys = <&comphy2 0>;
480				phy-names = "sata-phy";
481				status = "disabled";
482			};
483
484			gic: interrupt-controller@1d00000 {
485				compatible = "arm,gic-v3";
486				#interrupt-cells = <3>;
487				interrupt-controller;
488				reg = <0x1d00000 0x10000>, /* GICD */
489				      <0x1d40000 0x40000>, /* GICR */
490				      <0x1d80000 0x2000>,  /* GICC */
491				      <0x1d90000 0x2000>,  /* GICH */
492				      <0x1da0000 0x20000>; /* GICV */
493				interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
494			};
495		};
496
497		pcie0: pcie@d0070000 {
498			compatible = "marvell,armada-3700-pcie";
499			device_type = "pci";
500			status = "disabled";
501			reg = <0 0xd0070000 0 0x20000>;
502			#address-cells = <3>;
503			#size-cells = <2>;
504			bus-range = <0x00 0xff>;
505			interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
506			#interrupt-cells = <1>;
507			clocks = <&sb_periph_clk 13>;
508			msi-parent = <&pcie0>;
509			msi-controller;
510			/*
511			 * The 128 MiB address range [0xe8000000-0xf0000000] is
512			 * dedicated for PCIe and can be assigned to 8 windows
513			 * with size a power of two. Use one 64 KiB window for
514			 * IO at the end and the remaining seven windows
515			 * (totaling 127 MiB) for MEM.
516			 */
517			ranges = <0x82000000 0 0xe8000000   0 0xe8000000   0 0x07f00000   /* Port 0 MEM */
518				  0x81000000 0 0x00000000   0 0xefff0000   0 0x00010000>; /* Port 0 IO */
519			interrupt-map-mask = <0 0 0 7>;
520			interrupt-map = <0 0 0 1 &pcie_intc 0>,
521					<0 0 0 2 &pcie_intc 1>,
522					<0 0 0 3 &pcie_intc 2>,
523					<0 0 0 4 &pcie_intc 3>;
524			max-link-speed = <2>;
525			phys = <&comphy1 0>;
526			pcie_intc: interrupt-controller {
527				interrupt-controller;
528				#interrupt-cells = <1>;
529			};
530		};
531	};
532
533	firmware {
534		armada-3700-rwtm {
535			compatible = "marvell,armada-3700-rwtm-firmware";
536			mboxes = <&rwtm 0>;
537			status = "okay";
538		};
539	};
540};
541