1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Device Tree Source for the R-Car V3U (R8A779A0) SoC 4 * 5 * Copyright (C) 2020 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/r8a779a0-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10#include <dt-bindings/power/r8a779a0-sysc.h> 11 12/ { 13 compatible = "renesas,r8a779a0"; 14 #address-cells = <2>; 15 #size-cells = <2>; 16 17 aliases { 18 i2c0 = &i2c0; 19 i2c1 = &i2c1; 20 i2c2 = &i2c2; 21 i2c3 = &i2c3; 22 i2c4 = &i2c4; 23 i2c5 = &i2c5; 24 i2c6 = &i2c6; 25 }; 26 27 cpus { 28 #address-cells = <1>; 29 #size-cells = <0>; 30 31 a76_0: cpu@0 { 32 compatible = "arm,cortex-a76"; 33 reg = <0>; 34 device_type = "cpu"; 35 power-domains = <&sysc R8A779A0_PD_A1E0D0C0>; 36 next-level-cache = <&L3_CA76_0>; 37 }; 38 39 L3_CA76_0: cache-controller-0 { 40 compatible = "cache"; 41 power-domains = <&sysc R8A779A0_PD_A2E0D0>; 42 cache-unified; 43 cache-level = <3>; 44 }; 45 }; 46 47 extal_clk: extal { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 /* This value must be overridden by the board */ 51 clock-frequency = <0>; 52 }; 53 54 extalr_clk: extalr { 55 compatible = "fixed-clock"; 56 #clock-cells = <0>; 57 /* This value must be overridden by the board */ 58 clock-frequency = <0>; 59 }; 60 61 pmu_a76 { 62 compatible = "arm,cortex-a76-pmu"; 63 interrupts-extended = <&gic GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 64 }; 65 66 /* External SCIF clock - to be overridden by boards that provide it */ 67 scif_clk: scif { 68 compatible = "fixed-clock"; 69 #clock-cells = <0>; 70 clock-frequency = <0>; 71 }; 72 73 soc: soc { 74 compatible = "simple-bus"; 75 interrupt-parent = <&gic>; 76 #address-cells = <2>; 77 #size-cells = <2>; 78 ranges; 79 80 rwdt: watchdog@e6020000 { 81 compatible = "renesas,r8a779a0-wdt", 82 "renesas,rcar-gen3-wdt"; 83 reg = <0 0xe6020000 0 0x0c>; 84 clocks = <&cpg CPG_MOD 907>; 85 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 86 resets = <&cpg 907>; 87 status = "disabled"; 88 }; 89 90 pfc: pin-controller@e6050000 { 91 compatible = "renesas,pfc-r8a779a0"; 92 reg = <0 0xe6050000 0 0x16c>, <0 0xe6050800 0 0x16c>, 93 <0 0xe6058000 0 0x16c>, <0 0xe6058800 0 0x16c>, 94 <0 0xe6060000 0 0x16c>, <0 0xe6060800 0 0x16c>, 95 <0 0xe6068000 0 0x16c>, <0 0xe6068800 0 0x16c>, 96 <0 0xe6069000 0 0x16c>, <0 0xe6069800 0 0x16c>; 97 }; 98 99 gpio0: gpio@e6058180 { 100 compatible = "renesas,gpio-r8a779a0"; 101 reg = <0 0xe6058180 0 0x54>; 102 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>; 103 clocks = <&cpg CPG_MOD 916>; 104 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 105 resets = <&cpg 916>; 106 gpio-controller; 107 #gpio-cells = <2>; 108 gpio-ranges = <&pfc 0 0 28>; 109 interrupt-controller; 110 #interrupt-cells = <2>; 111 }; 112 113 gpio1: gpio@e6050180 { 114 compatible = "renesas,gpio-r8a779a0"; 115 reg = <0 0xe6050180 0 0x54>; 116 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>; 117 clocks = <&cpg CPG_MOD 915>; 118 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 119 resets = <&cpg 915>; 120 gpio-controller; 121 #gpio-cells = <2>; 122 gpio-ranges = <&pfc 0 32 31>; 123 interrupt-controller; 124 #interrupt-cells = <2>; 125 }; 126 127 gpio2: gpio@e6050980 { 128 compatible = "renesas,gpio-r8a779a0"; 129 reg = <0 0xe6050980 0 0x54>; 130 interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>; 131 clocks = <&cpg CPG_MOD 915>; 132 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 133 resets = <&cpg 915>; 134 gpio-controller; 135 #gpio-cells = <2>; 136 gpio-ranges = <&pfc 0 64 25>; 137 interrupt-controller; 138 #interrupt-cells = <2>; 139 }; 140 141 gpio3: gpio@e6058980 { 142 compatible = "renesas,gpio-r8a779a0"; 143 reg = <0 0xe6058980 0 0x54>; 144 interrupts = <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>; 145 clocks = <&cpg CPG_MOD 916>; 146 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 147 resets = <&cpg 916>; 148 gpio-controller; 149 #gpio-cells = <2>; 150 gpio-ranges = <&pfc 0 96 17>; 151 interrupt-controller; 152 #interrupt-cells = <2>; 153 }; 154 155 gpio4: gpio@e6060180 { 156 compatible = "renesas,gpio-r8a779a0"; 157 reg = <0 0xe6060180 0 0x54>; 158 interrupts = <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>; 159 clocks = <&cpg CPG_MOD 917>; 160 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 161 resets = <&cpg 917>; 162 gpio-controller; 163 #gpio-cells = <2>; 164 gpio-ranges = <&pfc 0 128 27>; 165 interrupt-controller; 166 #interrupt-cells = <2>; 167 }; 168 169 gpio5: gpio@e6060980 { 170 compatible = "renesas,gpio-r8a779a0"; 171 reg = <0 0xe6060980 0 0x54>; 172 interrupts = <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>; 173 clocks = <&cpg CPG_MOD 917>; 174 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 175 resets = <&cpg 917>; 176 gpio-controller; 177 #gpio-cells = <2>; 178 gpio-ranges = <&pfc 0 160 21>; 179 interrupt-controller; 180 #interrupt-cells = <2>; 181 }; 182 183 gpio6: gpio@e6068180 { 184 compatible = "renesas,gpio-r8a779a0"; 185 reg = <0 0xe6068180 0 0x54>; 186 interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; 187 clocks = <&cpg CPG_MOD 918>; 188 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 189 resets = <&cpg 918>; 190 gpio-controller; 191 #gpio-cells = <2>; 192 gpio-ranges = <&pfc 0 192 21>; 193 interrupt-controller; 194 #interrupt-cells = <2>; 195 }; 196 197 gpio7: gpio@e6068980 { 198 compatible = "renesas,gpio-r8a779a0"; 199 reg = <0 0xe6068980 0 0x54>; 200 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 201 clocks = <&cpg CPG_MOD 918>; 202 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 203 resets = <&cpg 918>; 204 gpio-controller; 205 #gpio-cells = <2>; 206 gpio-ranges = <&pfc 0 224 21>; 207 interrupt-controller; 208 #interrupt-cells = <2>; 209 }; 210 211 gpio8: gpio@e6069180 { 212 compatible = "renesas,gpio-r8a779a0"; 213 reg = <0 0xe6069180 0 0x54>; 214 interrupts = <GIC_SPI 864 IRQ_TYPE_LEVEL_HIGH>; 215 clocks = <&cpg CPG_MOD 918>; 216 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 217 resets = <&cpg 918>; 218 gpio-controller; 219 #gpio-cells = <2>; 220 gpio-ranges = <&pfc 0 256 21>; 221 interrupt-controller; 222 #interrupt-cells = <2>; 223 }; 224 225 gpio9: gpio@e6069980 { 226 compatible = "renesas,gpio-r8a779a0"; 227 reg = <0 0xe6069980 0 0x54>; 228 interrupts = <GIC_SPI 868 IRQ_TYPE_LEVEL_HIGH>; 229 clocks = <&cpg CPG_MOD 918>; 230 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 231 resets = <&cpg 918>; 232 gpio-controller; 233 #gpio-cells = <2>; 234 gpio-ranges = <&pfc 0 288 21>; 235 interrupt-controller; 236 #interrupt-cells = <2>; 237 }; 238 239 cmt0: timer@e60f0000 { 240 compatible = "renesas,r8a779a0-cmt0", 241 "renesas,rcar-gen3-cmt0"; 242 reg = <0 0xe60f0000 0 0x1004>; 243 interrupts = <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 244 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>; 245 clocks = <&cpg CPG_MOD 910>; 246 clock-names = "fck"; 247 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 248 resets = <&cpg 910>; 249 status = "disabled"; 250 }; 251 252 cmt1: timer@e6130000 { 253 compatible = "renesas,r8a779a0-cmt1", 254 "renesas,rcar-gen3-cmt1"; 255 reg = <0 0xe6130000 0 0x1004>; 256 interrupts = <GIC_SPI 448 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 450 IRQ_TYPE_LEVEL_HIGH>, 259 <GIC_SPI 451 IRQ_TYPE_LEVEL_HIGH>, 260 <GIC_SPI 452 IRQ_TYPE_LEVEL_HIGH>, 261 <GIC_SPI 453 IRQ_TYPE_LEVEL_HIGH>, 262 <GIC_SPI 454 IRQ_TYPE_LEVEL_HIGH>, 263 <GIC_SPI 455 IRQ_TYPE_LEVEL_HIGH>; 264 clocks = <&cpg CPG_MOD 911>; 265 clock-names = "fck"; 266 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 267 resets = <&cpg 911>; 268 status = "disabled"; 269 }; 270 271 cmt2: timer@e6140000 { 272 compatible = "renesas,r8a779a0-cmt1", 273 "renesas,rcar-gen3-cmt1"; 274 reg = <0 0xe6140000 0 0x1004>; 275 interrupts = <GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, 276 <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, 277 <GIC_SPI 458 IRQ_TYPE_LEVEL_HIGH>, 278 <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 460 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>, 281 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>, 282 <GIC_SPI 463 IRQ_TYPE_LEVEL_HIGH>; 283 clocks = <&cpg CPG_MOD 912>; 284 clock-names = "fck"; 285 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 286 resets = <&cpg 912>; 287 status = "disabled"; 288 }; 289 290 cmt3: timer@e6148000 { 291 compatible = "renesas,r8a779a0-cmt1", 292 "renesas,rcar-gen3-cmt1"; 293 reg = <0 0xe6148000 0 0x1004>; 294 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>, 295 <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>, 296 <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>, 297 <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>, 298 <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>, 299 <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>, 300 <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>; 302 clocks = <&cpg CPG_MOD 913>; 303 clock-names = "fck"; 304 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 305 resets = <&cpg 913>; 306 status = "disabled"; 307 }; 308 309 cpg: clock-controller@e6150000 { 310 compatible = "renesas,r8a779a0-cpg-mssr"; 311 reg = <0 0xe6150000 0 0x4000>; 312 clocks = <&extal_clk>, <&extalr_clk>; 313 clock-names = "extal", "extalr"; 314 #clock-cells = <2>; 315 #power-domain-cells = <0>; 316 #reset-cells = <1>; 317 }; 318 319 rst: reset-controller@e6160000 { 320 compatible = "renesas,r8a779a0-rst"; 321 reg = <0 0xe6160000 0 0x4000>; 322 }; 323 324 sysc: system-controller@e6180000 { 325 compatible = "renesas,r8a779a0-sysc"; 326 reg = <0 0xe6180000 0 0x4000>; 327 #power-domain-cells = <1>; 328 }; 329 330 tmu0: timer@e61e0000 { 331 compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; 332 reg = <0 0xe61e0000 0 0x30>; 333 interrupts = <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 334 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 335 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>; 336 clocks = <&cpg CPG_MOD 713>; 337 clock-names = "fck"; 338 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 339 resets = <&cpg 713>; 340 status = "disabled"; 341 }; 342 343 tmu1: timer@e6fc0000 { 344 compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; 345 reg = <0 0xe6fc0000 0 0x30>; 346 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 347 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 348 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&cpg CPG_MOD 714>; 350 clock-names = "fck"; 351 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 352 resets = <&cpg 714>; 353 status = "disabled"; 354 }; 355 356 tmu2: timer@e6fd0000 { 357 compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; 358 reg = <0 0xe6fd0000 0 0x30>; 359 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 360 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 361 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>; 362 clocks = <&cpg CPG_MOD 715>; 363 clock-names = "fck"; 364 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 365 resets = <&cpg 715>; 366 status = "disabled"; 367 }; 368 369 tmu3: timer@e6fe0000 { 370 compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; 371 reg = <0 0xe6fe0000 0 0x30>; 372 interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>, 373 <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>, 374 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 375 clocks = <&cpg CPG_MOD 716>; 376 clock-names = "fck"; 377 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 378 resets = <&cpg 716>; 379 status = "disabled"; 380 }; 381 382 tmu4: timer@ffc00000 { 383 compatible = "renesas,tmu-r8a779a0", "renesas,tmu"; 384 reg = <0 0xffc00000 0 0x30>; 385 interrupts = <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>, 386 <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>, 387 <GIC_SPI 478 IRQ_TYPE_LEVEL_HIGH>; 388 clocks = <&cpg CPG_MOD 717>; 389 clock-names = "fck"; 390 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 391 resets = <&cpg 717>; 392 status = "disabled"; 393 }; 394 395 tsc: thermal@e6190000 { 396 compatible = "renesas,r8a779a0-thermal"; 397 reg = <0 0xe6190000 0 0x200>, 398 <0 0xe6198000 0 0x200>, 399 <0 0xe61a0000 0 0x200>, 400 <0 0xe61a8000 0 0x200>, 401 <0 0xe61b0000 0 0x200>; 402 clocks = <&cpg CPG_MOD 919>; 403 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 404 resets = <&cpg 919>; 405 #thermal-sensor-cells = <1>; 406 }; 407 408 i2c0: i2c@e6500000 { 409 compatible = "renesas,i2c-r8a779a0", 410 "renesas,rcar-gen3-i2c"; 411 reg = <0 0xe6500000 0 0x40>; 412 interrupts = <GIC_SPI 238 IRQ_TYPE_LEVEL_HIGH>; 413 clocks = <&cpg CPG_MOD 518>; 414 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 415 resets = <&cpg 518>; 416 dmas = <&dmac1 0x91>, <&dmac1 0x90>; 417 dma-names = "tx", "rx"; 418 i2c-scl-internal-delay-ns = <110>; 419 #address-cells = <1>; 420 #size-cells = <0>; 421 status = "disabled"; 422 }; 423 424 i2c1: i2c@e6508000 { 425 compatible = "renesas,i2c-r8a779a0", 426 "renesas,rcar-gen3-i2c"; 427 reg = <0 0xe6508000 0 0x40>; 428 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 429 clocks = <&cpg CPG_MOD 519>; 430 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 431 resets = <&cpg 519>; 432 dmas = <&dmac1 0x93>, <&dmac1 0x92>; 433 dma-names = "tx", "rx"; 434 i2c-scl-internal-delay-ns = <110>; 435 #address-cells = <1>; 436 #size-cells = <0>; 437 status = "disabled"; 438 }; 439 440 i2c2: i2c@e6510000 { 441 compatible = "renesas,i2c-r8a779a0", 442 "renesas,rcar-gen3-i2c"; 443 reg = <0 0xe6510000 0 0x40>; 444 interrupts = <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>; 445 clocks = <&cpg CPG_MOD 520>; 446 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 447 resets = <&cpg 520>; 448 dmas = <&dmac1 0x95>, <&dmac1 0x94>; 449 dma-names = "tx", "rx"; 450 i2c-scl-internal-delay-ns = <110>; 451 #address-cells = <1>; 452 #size-cells = <0>; 453 status = "disabled"; 454 }; 455 456 i2c3: i2c@e66d0000 { 457 compatible = "renesas,i2c-r8a779a0", 458 "renesas,rcar-gen3-i2c"; 459 reg = <0 0xe66d0000 0 0x40>; 460 interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>; 461 clocks = <&cpg CPG_MOD 521>; 462 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 463 resets = <&cpg 521>; 464 dmas = <&dmac1 0x97>, <&dmac1 0x96>; 465 dma-names = "tx", "rx"; 466 i2c-scl-internal-delay-ns = <110>; 467 #address-cells = <1>; 468 #size-cells = <0>; 469 status = "disabled"; 470 }; 471 472 i2c4: i2c@e66d8000 { 473 compatible = "renesas,i2c-r8a779a0", 474 "renesas,rcar-gen3-i2c"; 475 reg = <0 0xe66d8000 0 0x40>; 476 interrupts = <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>; 477 clocks = <&cpg CPG_MOD 522>; 478 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 479 resets = <&cpg 522>; 480 dmas = <&dmac1 0x99>, <&dmac1 0x98>; 481 dma-names = "tx", "rx"; 482 i2c-scl-internal-delay-ns = <110>; 483 #address-cells = <1>; 484 #size-cells = <0>; 485 status = "disabled"; 486 }; 487 488 i2c5: i2c@e66e0000 { 489 compatible = "renesas,i2c-r8a779a0", 490 "renesas,rcar-gen3-i2c"; 491 reg = <0 0xe66e0000 0 0x40>; 492 interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH>; 493 clocks = <&cpg CPG_MOD 523>; 494 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 495 resets = <&cpg 523>; 496 dmas = <&dmac1 0x9b>, <&dmac1 0x9a>; 497 dma-names = "tx", "rx"; 498 i2c-scl-internal-delay-ns = <110>; 499 #address-cells = <1>; 500 #size-cells = <0>; 501 status = "disabled"; 502 }; 503 504 i2c6: i2c@e66e8000 { 505 compatible = "renesas,i2c-r8a779a0", 506 "renesas,rcar-gen3-i2c"; 507 reg = <0 0xe66e8000 0 0x40>; 508 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cpg CPG_MOD 524>; 510 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 511 resets = <&cpg 524>; 512 dmas = <&dmac1 0x9d>, <&dmac1 0x9c>; 513 dma-names = "tx", "rx"; 514 i2c-scl-internal-delay-ns = <110>; 515 #address-cells = <1>; 516 #size-cells = <0>; 517 status = "disabled"; 518 }; 519 520 hscif0: serial@e6540000 { 521 compatible = "renesas,hscif-r8a779a0", 522 "renesas,rcar-gen3-hscif", "renesas,hscif"; 523 reg = <0 0xe6540000 0 0x60>; 524 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 525 clocks = <&cpg CPG_MOD 514>, 526 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 527 <&scif_clk>; 528 clock-names = "fck", "brg_int", "scif_clk"; 529 dmas = <&dmac1 0x31>, <&dmac1 0x30>; 530 dma-names = "tx", "rx"; 531 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 532 resets = <&cpg 514>; 533 status = "disabled"; 534 }; 535 536 hscif1: serial@e6550000 { 537 compatible = "renesas,hscif-r8a779a0", 538 "renesas,rcar-gen3-hscif", "renesas,hscif"; 539 reg = <0 0xe6550000 0 0x60>; 540 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 541 clocks = <&cpg CPG_MOD 515>, 542 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 543 <&scif_clk>; 544 clock-names = "fck", "brg_int", "scif_clk"; 545 dmas = <&dmac1 0x33>, <&dmac1 0x32>; 546 dma-names = "tx", "rx"; 547 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 548 resets = <&cpg 515>; 549 status = "disabled"; 550 }; 551 552 hscif2: serial@e6560000 { 553 compatible = "renesas,hscif-r8a779a0", 554 "renesas,rcar-gen3-hscif", "renesas,hscif"; 555 reg = <0 0xe6560000 0 0x60>; 556 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 557 clocks = <&cpg CPG_MOD 516>, 558 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 559 <&scif_clk>; 560 clock-names = "fck", "brg_int", "scif_clk"; 561 dmas = <&dmac1 0x35>, <&dmac1 0x34>; 562 dma-names = "tx", "rx"; 563 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 564 resets = <&cpg 516>; 565 status = "disabled"; 566 }; 567 568 hscif3: serial@e66a0000 { 569 compatible = "renesas,hscif-r8a779a0", 570 "renesas,rcar-gen3-hscif", "renesas,hscif"; 571 reg = <0 0xe66a0000 0 0x60>; 572 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&cpg CPG_MOD 517>, 574 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 575 <&scif_clk>; 576 clock-names = "fck", "brg_int", "scif_clk"; 577 dmas = <&dmac1 0x37>, <&dmac1 0x36>; 578 dma-names = "tx", "rx"; 579 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 580 resets = <&cpg 517>; 581 status = "disabled"; 582 }; 583 584 avb0: ethernet@e6800000 { 585 compatible = "renesas,etheravb-r8a779a0", 586 "renesas,etheravb-rcar-gen3"; 587 reg = <0 0xe6800000 0 0x800>; 588 interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, 589 <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH>, 590 <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH>, 591 <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>, 592 <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, 593 <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>, 594 <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH>, 595 <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>, 596 <GIC_SPI 264 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>, 599 <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>, 600 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 601 <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>, 602 <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>, 603 <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>, 604 <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>, 605 <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH>, 606 <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH>, 607 <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH>, 608 <GIC_SPI 276 IRQ_TYPE_LEVEL_HIGH>, 609 <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH>, 610 <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>, 611 <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 612 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>; 613 interrupt-names = "ch0", "ch1", "ch2", "ch3", 614 "ch4", "ch5", "ch6", "ch7", 615 "ch8", "ch9", "ch10", "ch11", 616 "ch12", "ch13", "ch14", "ch15", 617 "ch16", "ch17", "ch18", "ch19", 618 "ch20", "ch21", "ch22", "ch23", 619 "ch24"; 620 clocks = <&cpg CPG_MOD 211>; 621 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 622 resets = <&cpg 211>; 623 phy-mode = "rgmii"; 624 rx-internal-delay-ps = <0>; 625 tx-internal-delay-ps = <0>; 626 #address-cells = <1>; 627 #size-cells = <0>; 628 status = "disabled"; 629 }; 630 631 avb1: ethernet@e6810000 { 632 compatible = "renesas,etheravb-r8a779a0", 633 "renesas,etheravb-rcar-gen3"; 634 reg = <0 0xe6810000 0 0x800>; 635 interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 636 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 637 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 638 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 639 <GIC_SPI 285 IRQ_TYPE_LEVEL_HIGH>, 640 <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>, 641 <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>, 642 <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, 643 <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, 644 <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, 645 <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, 646 <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, 647 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 648 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 649 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 650 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 651 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 652 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, 653 <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, 654 <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, 655 <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, 656 <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, 657 <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>, 658 <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 659 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 660 interrupt-names = "ch0", "ch1", "ch2", "ch3", 661 "ch4", "ch5", "ch6", "ch7", 662 "ch8", "ch9", "ch10", "ch11", 663 "ch12", "ch13", "ch14", "ch15", 664 "ch16", "ch17", "ch18", "ch19", 665 "ch20", "ch21", "ch22", "ch23", 666 "ch24"; 667 clocks = <&cpg CPG_MOD 212>; 668 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 669 resets = <&cpg 212>; 670 phy-mode = "rgmii"; 671 rx-internal-delay-ps = <0>; 672 tx-internal-delay-ps = <0>; 673 #address-cells = <1>; 674 #size-cells = <0>; 675 status = "disabled"; 676 }; 677 678 avb2: ethernet@e6820000 { 679 compatible = "renesas,etheravb-r8a779a0", 680 "renesas,etheravb-rcar-gen3"; 681 reg = <0 0xe6820000 0 0x1000>; 682 interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 704 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 705 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 706 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>; 707 interrupt-names = "ch0", "ch1", "ch2", "ch3", 708 "ch4", "ch5", "ch6", "ch7", 709 "ch8", "ch9", "ch10", "ch11", 710 "ch12", "ch13", "ch14", "ch15", 711 "ch16", "ch17", "ch18", "ch19", 712 "ch20", "ch21", "ch22", "ch23", 713 "ch24"; 714 clocks = <&cpg CPG_MOD 213>; 715 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 716 resets = <&cpg 213>; 717 phy-mode = "rgmii"; 718 rx-internal-delay-ps = <0>; 719 tx-internal-delay-ps = <0>; 720 #address-cells = <1>; 721 #size-cells = <0>; 722 status = "disabled"; 723 }; 724 725 avb3: ethernet@e6830000 { 726 compatible = "renesas,etheravb-r8a779a0", 727 "renesas,etheravb-rcar-gen3"; 728 reg = <0 0xe6830000 0 0x1000>; 729 interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 754 interrupt-names = "ch0", "ch1", "ch2", "ch3", 755 "ch4", "ch5", "ch6", "ch7", 756 "ch8", "ch9", "ch10", "ch11", 757 "ch12", "ch13", "ch14", "ch15", 758 "ch16", "ch17", "ch18", "ch19", 759 "ch20", "ch21", "ch22", "ch23", 760 "ch24"; 761 clocks = <&cpg CPG_MOD 214>; 762 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 763 resets = <&cpg 214>; 764 phy-mode = "rgmii"; 765 rx-internal-delay-ps = <0>; 766 tx-internal-delay-ps = <0>; 767 #address-cells = <1>; 768 #size-cells = <0>; 769 status = "disabled"; 770 }; 771 772 avb4: ethernet@e6840000 { 773 compatible = "renesas,etheravb-r8a779a0", 774 "renesas,etheravb-rcar-gen3"; 775 reg = <0 0xe6840000 0 0x1000>; 776 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, 777 <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, 778 <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, 779 <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, 780 <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, 781 <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, 782 <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, 783 <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, 784 <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, 785 <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, 786 <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, 787 <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, 788 <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, 789 <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, 790 <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, 791 <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, 792 <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, 793 <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, 794 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 795 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 796 <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, 797 <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, 798 <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, 799 <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, 800 <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>; 801 interrupt-names = "ch0", "ch1", "ch2", "ch3", 802 "ch4", "ch5", "ch6", "ch7", 803 "ch8", "ch9", "ch10", "ch11", 804 "ch12", "ch13", "ch14", "ch15", 805 "ch16", "ch17", "ch18", "ch19", 806 "ch20", "ch21", "ch22", "ch23", 807 "ch24"; 808 clocks = <&cpg CPG_MOD 215>; 809 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 810 resets = <&cpg 215>; 811 phy-mode = "rgmii"; 812 rx-internal-delay-ps = <0>; 813 tx-internal-delay-ps = <0>; 814 #address-cells = <1>; 815 #size-cells = <0>; 816 status = "disabled"; 817 }; 818 819 avb5: ethernet@e6850000 { 820 compatible = "renesas,etheravb-r8a779a0", 821 "renesas,etheravb-rcar-gen3"; 822 reg = <0 0xe6850000 0 0x1000>; 823 interrupts = <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, 824 <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, 825 <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, 826 <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, 827 <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, 828 <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, 829 <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 388 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 389 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 390 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>; 848 interrupt-names = "ch0", "ch1", "ch2", "ch3", 849 "ch4", "ch5", "ch6", "ch7", 850 "ch8", "ch9", "ch10", "ch11", 851 "ch12", "ch13", "ch14", "ch15", 852 "ch16", "ch17", "ch18", "ch19", 853 "ch20", "ch21", "ch22", "ch23", 854 "ch24"; 855 clocks = <&cpg CPG_MOD 216>; 856 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 857 resets = <&cpg 216>; 858 phy-mode = "rgmii"; 859 rx-internal-delay-ps = <0>; 860 tx-internal-delay-ps = <0>; 861 #address-cells = <1>; 862 #size-cells = <0>; 863 status = "disabled"; 864 }; 865 866 scif0: serial@e6e60000 { 867 compatible = "renesas,scif-r8a779a0", 868 "renesas,rcar-gen3-scif", "renesas,scif"; 869 reg = <0 0xe6e60000 0 64>; 870 interrupts = <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; 871 clocks = <&cpg CPG_MOD 702>, 872 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 873 <&scif_clk>; 874 clock-names = "fck", "brg_int", "scif_clk"; 875 dmas = <&dmac1 0x51>, <&dmac1 0x50>; 876 dma-names = "tx", "rx"; 877 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 878 resets = <&cpg 702>; 879 status = "disabled"; 880 }; 881 882 scif1: serial@e6e68000 { 883 compatible = "renesas,scif-r8a779a0", 884 "renesas,rcar-gen3-scif", "renesas,scif"; 885 reg = <0 0xe6e68000 0 64>; 886 interrupts = <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>; 887 clocks = <&cpg CPG_MOD 703>, 888 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 889 <&scif_clk>; 890 clock-names = "fck", "brg_int", "scif_clk"; 891 dmas = <&dmac1 0x53>, <&dmac1 0x52>; 892 dma-names = "tx", "rx"; 893 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 894 resets = <&cpg 703>; 895 status = "disabled"; 896 }; 897 898 scif3: serial@e6c50000 { 899 compatible = "renesas,scif-r8a779a0", 900 "renesas,rcar-gen3-scif", "renesas,scif"; 901 reg = <0 0xe6c50000 0 64>; 902 interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>; 903 clocks = <&cpg CPG_MOD 704>, 904 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 905 <&scif_clk>; 906 clock-names = "fck", "brg_int", "scif_clk"; 907 dmas = <&dmac1 0x57>, <&dmac1 0x56>; 908 dma-names = "tx", "rx"; 909 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 910 resets = <&cpg 704>; 911 status = "disabled"; 912 }; 913 914 scif4: serial@e6c40000 { 915 compatible = "renesas,scif-r8a779a0", 916 "renesas,rcar-gen3-scif", "renesas,scif"; 917 reg = <0 0xe6c40000 0 64>; 918 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 919 clocks = <&cpg CPG_MOD 705>, 920 <&cpg CPG_CORE R8A779A0_CLK_S1D2>, 921 <&scif_clk>; 922 clock-names = "fck", "brg_int", "scif_clk"; 923 dmas = <&dmac1 0x59>, <&dmac1 0x58>; 924 dma-names = "tx", "rx"; 925 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 926 resets = <&cpg 705>; 927 status = "disabled"; 928 }; 929 930 msiof0: spi@e6e90000 { 931 compatible = "renesas,msiof-r8a779a0", 932 "renesas,rcar-gen3-msiof"; 933 reg = <0 0xe6e90000 0 0x0064>; 934 interrupts = <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>; 935 clocks = <&cpg CPG_MOD 618>; 936 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 937 resets = <&cpg 618>; 938 dmas = <&dmac1 0x41>, <&dmac1 0x40>; 939 dma-names = "tx", "rx"; 940 #address-cells = <1>; 941 #size-cells = <0>; 942 status = "disabled"; 943 }; 944 945 msiof1: spi@e6ea0000 { 946 compatible = "renesas,msiof-r8a779a0", 947 "renesas,rcar-gen3-msiof"; 948 reg = <0 0xe6ea0000 0 0x0064>; 949 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 950 clocks = <&cpg CPG_MOD 619>; 951 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 952 resets = <&cpg 619>; 953 dmas = <&dmac1 0x43>, <&dmac1 0x42>; 954 dma-names = "tx", "rx"; 955 #address-cells = <1>; 956 #size-cells = <0>; 957 status = "disabled"; 958 }; 959 960 msiof2: spi@e6c00000 { 961 compatible = "renesas,msiof-r8a779a0", 962 "renesas,rcar-gen3-msiof"; 963 reg = <0 0xe6c00000 0 0x0064>; 964 interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; 965 clocks = <&cpg CPG_MOD 620>; 966 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 967 resets = <&cpg 620>; 968 dmas = <&dmac1 0x45>, <&dmac1 0x44>; 969 dma-names = "tx", "rx"; 970 #address-cells = <1>; 971 #size-cells = <0>; 972 status = "disabled"; 973 }; 974 975 msiof3: spi@e6c10000 { 976 compatible = "renesas,msiof-r8a779a0", 977 "renesas,rcar-gen3-msiof"; 978 reg = <0 0xe6c10000 0 0x0064>; 979 interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>; 980 clocks = <&cpg CPG_MOD 621>; 981 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 982 resets = <&cpg 621>; 983 dmas = <&dmac1 0x47>, <&dmac1 0x46>; 984 dma-names = "tx", "rx"; 985 #address-cells = <1>; 986 #size-cells = <0>; 987 status = "disabled"; 988 }; 989 990 msiof4: spi@e6c20000 { 991 compatible = "renesas,msiof-r8a779a0", 992 "renesas,rcar-gen3-msiof"; 993 reg = <0 0xe6c20000 0 0x0064>; 994 interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>; 995 clocks = <&cpg CPG_MOD 622>; 996 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 997 resets = <&cpg 622>; 998 dmas = <&dmac1 0x49>, <&dmac1 0x48>; 999 dma-names = "tx", "rx"; 1000 #address-cells = <1>; 1001 #size-cells = <0>; 1002 status = "disabled"; 1003 }; 1004 1005 msiof5: spi@e6c28000 { 1006 compatible = "renesas,msiof-r8a779a0", 1007 "renesas,rcar-gen3-msiof"; 1008 reg = <0 0xe6c28000 0 0x0064>; 1009 interrupts = <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>; 1010 clocks = <&cpg CPG_MOD 623>; 1011 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1012 resets = <&cpg 623>; 1013 dmas = <&dmac1 0x4b>, <&dmac1 0x4a>; 1014 dma-names = "tx", "rx"; 1015 #address-cells = <1>; 1016 #size-cells = <0>; 1017 status = "disabled"; 1018 }; 1019 1020 dmac1: dma-controller@e7350000 { 1021 compatible = "renesas,dmac-r8a779a0"; 1022 reg = <0 0xe7350000 0 0x1000>, 1023 <0 0xe7300000 0 0x10000>; 1024 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 1041 interrupt-names = "error", 1042 "ch0", "ch1", "ch2", "ch3", "ch4", 1043 "ch5", "ch6", "ch7", "ch8", "ch9", 1044 "ch10", "ch11", "ch12", "ch13", 1045 "ch14", "ch15"; 1046 clocks = <&cpg CPG_MOD 709>; 1047 clock-names = "fck"; 1048 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1049 resets = <&cpg 709>; 1050 #dma-cells = <1>; 1051 dma-channels = <16>; 1052 }; 1053 1054 dmac2: dma-controller@e7351000 { 1055 compatible = "renesas,dmac-r8a779a0"; 1056 reg = <0 0xe7351000 0 0x1000>, 1057 <0 0xe7310000 0 0x10000>; 1058 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 1067 interrupt-names = "error", 1068 "ch0", "ch1", "ch2", "ch3", "ch4", 1069 "ch5", "ch6", "ch7"; 1070 clocks = <&cpg CPG_MOD 710>; 1071 clock-names = "fck"; 1072 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1073 resets = <&cpg 710>; 1074 #dma-cells = <1>; 1075 dma-channels = <8>; 1076 }; 1077 1078 mmc0: mmc@ee140000 { 1079 compatible = "renesas,sdhi-r8a779a0", 1080 "renesas,rcar-gen3-sdhi"; 1081 reg = <0 0xee140000 0 0x2000>; 1082 interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; 1083 clocks = <&cpg CPG_MOD 706>; 1084 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1085 resets = <&cpg 706>; 1086 max-frequency = <200000000>; 1087 status = "disabled"; 1088 }; 1089 1090 gic: interrupt-controller@f1000000 { 1091 compatible = "arm,gic-v3"; 1092 #interrupt-cells = <3>; 1093 #address-cells = <0>; 1094 interrupt-controller; 1095 reg = <0x0 0xf1000000 0 0x20000>, 1096 <0x0 0xf1060000 0 0x110000>; 1097 interrupts = <GIC_PPI 9 1098 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>; 1099 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1100 }; 1101 1102 fcpvd0: fcp@fea10000 { 1103 compatible = "renesas,fcpv"; 1104 reg = <0 0xfea10000 0 0x200>; 1105 clocks = <&cpg CPG_MOD 508>; 1106 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1107 resets = <&cpg 508>; 1108 }; 1109 1110 fcpvd1: fcp@fea11000 { 1111 compatible = "renesas,fcpv"; 1112 reg = <0 0xfea11000 0 0x200>; 1113 clocks = <&cpg CPG_MOD 509>; 1114 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1115 resets = <&cpg 509>; 1116 }; 1117 1118 vspd0: vsp@fea20000 { 1119 compatible = "renesas,vsp2"; 1120 reg = <0 0xfea20000 0 0x5000>; 1121 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; 1122 clocks = <&cpg CPG_MOD 830>; 1123 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1124 resets = <&cpg 830>; 1125 1126 renesas,fcp = <&fcpvd0>; 1127 }; 1128 1129 vspd1: vsp@fea28000 { 1130 compatible = "renesas,vsp2"; 1131 reg = <0 0xfea28000 0 0x5000>; 1132 interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; 1133 clocks = <&cpg CPG_MOD 831>; 1134 power-domains = <&sysc R8A779A0_PD_ALWAYS_ON>; 1135 resets = <&cpg 831>; 1136 1137 renesas,fcp = <&fcpvd1>; 1138 }; 1139 1140 prr: chipid@fff00044 { 1141 compatible = "renesas,prr"; 1142 reg = <0 0xfff00044 0 4>; 1143 }; 1144 }; 1145 1146 thermal-zones { 1147 sensor_thermal1: sensor-thermal1 { 1148 polling-delay-passive = <250>; 1149 polling-delay = <1000>; 1150 thermal-sensors = <&tsc 0>; 1151 1152 trips { 1153 sensor1_crit: sensor1-crit { 1154 temperature = <120000>; 1155 hysteresis = <1000>; 1156 type = "critical"; 1157 }; 1158 }; 1159 }; 1160 1161 sensor_thermal2: sensor-thermal2 { 1162 polling-delay-passive = <250>; 1163 polling-delay = <1000>; 1164 thermal-sensors = <&tsc 1>; 1165 1166 trips { 1167 sensor2_crit: sensor2-crit { 1168 temperature = <120000>; 1169 hysteresis = <1000>; 1170 type = "critical"; 1171 }; 1172 }; 1173 }; 1174 1175 sensor_thermal3: sensor-thermal3 { 1176 polling-delay-passive = <250>; 1177 polling-delay = <1000>; 1178 thermal-sensors = <&tsc 2>; 1179 1180 trips { 1181 sensor3_crit: sensor3-crit { 1182 temperature = <120000>; 1183 hysteresis = <1000>; 1184 type = "critical"; 1185 }; 1186 }; 1187 }; 1188 1189 sensor_thermal4: sensor-thermal4 { 1190 polling-delay-passive = <250>; 1191 polling-delay = <1000>; 1192 thermal-sensors = <&tsc 3>; 1193 1194 trips { 1195 sensor4_crit: sensor4-crit { 1196 temperature = <120000>; 1197 hysteresis = <1000>; 1198 type = "critical"; 1199 }; 1200 }; 1201 }; 1202 1203 sensor_thermal5: sensor-thermal5 { 1204 polling-delay-passive = <250>; 1205 polling-delay = <1000>; 1206 thermal-sensors = <&tsc 4>; 1207 1208 trips { 1209 sensor5_crit: sensor5-crit { 1210 temperature = <120000>; 1211 hysteresis = <1000>; 1212 type = "critical"; 1213 }; 1214 }; 1215 }; 1216 }; 1217 1218 timer { 1219 compatible = "arm,armv8-timer"; 1220 interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1221 <&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1222 <&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>, 1223 <&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>; 1224 }; 1225}; 1226