1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2/*
3 * Device Tree Source for the RZ/G2UL SMARC pincontrol parts
4 *
5 * Copyright (C) 2022 Renesas Electronics Corp.
6 */
7
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
10
11&pinctrl {
12	pinctrl-0 = <&sound_clk_pins>;
13	pinctrl-names = "default";
14
15	can0_pins: can0 {
16		pinmux = <RZG2L_PORT_PINMUX(1, 1, 3)>, /* TX */
17			 <RZG2L_PORT_PINMUX(1, 2, 3)>; /* RX */
18	};
19
20#if (SW_ET0_EN_N)
21	can0-stb-hog {
22		gpio-hog;
23		gpios = <RZG2L_GPIO(2, 2) GPIO_ACTIVE_HIGH>;
24		output-low;
25		line-name = "can0_stb";
26	};
27#endif
28
29	can1_pins: can1 {
30		pinmux = <RZG2L_PORT_PINMUX(2, 0, 3)>, /* TX */
31			 <RZG2L_PORT_PINMUX(2, 1, 3)>; /* RX */
32	};
33
34#if (SW_ET0_EN_N)
35	can1-stb-hog {
36		gpio-hog;
37		gpios = <RZG2L_GPIO(2, 3) GPIO_ACTIVE_HIGH>;
38		output-low;
39		line-name = "can1_stb";
40	};
41#endif
42
43	i2c0_pins: i2c0 {
44		pins = "RIIC0_SDA", "RIIC0_SCL";
45		input-enable;
46	};
47
48	i2c1_pins: i2c1 {
49		pins = "RIIC1_SDA", "RIIC1_SCL";
50		input-enable;
51	};
52
53	scif0_pins: scif0 {
54		pinmux = <RZG2L_PORT_PINMUX(6, 4, 6)>, /* TxD */
55			 <RZG2L_PORT_PINMUX(6, 3, 6)>; /* RxD */
56	};
57
58	sd1-pwr-en-hog {
59		gpio-hog;
60		gpios = <RZG2L_GPIO(0, 3) GPIO_ACTIVE_HIGH>;
61		output-high;
62		line-name = "sd1_pwr_en";
63	};
64
65	sdhi1_pins: sd1 {
66		sd1_data {
67			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
68			power-source = <3300>;
69		};
70
71		sd1_ctrl {
72			pins = "SD1_CLK", "SD1_CMD";
73			power-source = <3300>;
74		};
75
76		sd1_mux {
77			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
78		};
79	};
80
81	sdhi1_pins_uhs: sd1_uhs {
82		sd1_data_uhs {
83			pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
84			power-source = <1800>;
85		};
86
87		sd1_ctrl_uhs {
88			pins = "SD1_CLK", "SD1_CMD";
89			power-source = <1800>;
90		};
91
92		sd1_mux_uhs {
93			pinmux = <RZG2L_PORT_PINMUX(0, 2, 1)>; /* SD1_CD */
94		};
95	};
96
97	sound_clk_pins: sound_clk {
98		pins = "AUDIO_CLK1", "AUDIO_CLK2";
99		input-enable;
100	};
101
102	spi1_pins: spi1 {
103		pinmux = <RZG2L_PORT_PINMUX(4, 0, 2)>, /* CK */
104			 <RZG2L_PORT_PINMUX(4, 1, 2)>, /* MOSI */
105			 <RZG2L_PORT_PINMUX(4, 2, 2)>, /* MISO */
106			 <RZG2L_PORT_PINMUX(4, 3, 2)>; /* SSL */
107	};
108
109	ssi1_pins: ssi1 {
110		pinmux = <RZG2L_PORT_PINMUX(3, 0, 2)>, /* BCK */
111			 <RZG2L_PORT_PINMUX(3, 1, 2)>, /* RCK */
112			 <RZG2L_PORT_PINMUX(3, 2, 2)>, /* TXD */
113			 <RZG2L_PORT_PINMUX(3, 3, 2)>; /* RXD */
114	};
115
116	usb0_pins: usb0 {
117		pinmux = <RZG2L_PORT_PINMUX(5, 0, 1)>, /* VBUS */
118			 <RZG2L_PORT_PINMUX(5, 2, 1)>, /* OVC */
119			 <RZG2L_PORT_PINMUX(5, 3, 1)>; /* OTG_ID */
120	};
121
122	usb1_pins: usb1 {
123		pinmux = <RZG2L_PORT_PINMUX(5, 4, 5)>, /* OVC */
124			 <RZG2L_PORT_PINMUX(6, 0, 1)>; /* VBUS */
125	};
126};
127