1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd 4 */ 5 6#include <dt-bindings/clock/px30-cru.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10#include <dt-bindings/pinctrl/rockchip.h> 11#include <dt-bindings/power/px30-power.h> 12#include <dt-bindings/soc/rockchip,boot-mode.h> 13#include <dt-bindings/thermal/thermal.h> 14 15/ { 16 compatible = "rockchip,px30"; 17 18 interrupt-parent = <&gic>; 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 aliases { 23 ethernet0 = &gmac; 24 i2c0 = &i2c0; 25 i2c1 = &i2c1; 26 i2c2 = &i2c2; 27 i2c3 = &i2c3; 28 serial0 = &uart0; 29 serial1 = &uart1; 30 serial2 = &uart2; 31 serial3 = &uart3; 32 serial4 = &uart4; 33 serial5 = &uart5; 34 spi0 = &spi0; 35 spi1 = &spi1; 36 }; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "arm,cortex-a35"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 clocks = <&cru ARMCLK>; 48 #cooling-cells = <2>; 49 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 50 dynamic-power-coefficient = <90>; 51 operating-points-v2 = <&cpu0_opp_table>; 52 }; 53 54 cpu1: cpu@1 { 55 device_type = "cpu"; 56 compatible = "arm,cortex-a35"; 57 reg = <0x0 0x1>; 58 enable-method = "psci"; 59 clocks = <&cru ARMCLK>; 60 #cooling-cells = <2>; 61 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 62 dynamic-power-coefficient = <90>; 63 operating-points-v2 = <&cpu0_opp_table>; 64 }; 65 66 cpu2: cpu@2 { 67 device_type = "cpu"; 68 compatible = "arm,cortex-a35"; 69 reg = <0x0 0x2>; 70 enable-method = "psci"; 71 clocks = <&cru ARMCLK>; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 74 dynamic-power-coefficient = <90>; 75 operating-points-v2 = <&cpu0_opp_table>; 76 }; 77 78 cpu3: cpu@3 { 79 device_type = "cpu"; 80 compatible = "arm,cortex-a35"; 81 reg = <0x0 0x3>; 82 enable-method = "psci"; 83 clocks = <&cru ARMCLK>; 84 #cooling-cells = <2>; 85 cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>; 86 dynamic-power-coefficient = <90>; 87 operating-points-v2 = <&cpu0_opp_table>; 88 }; 89 90 idle-states { 91 entry-method = "psci"; 92 93 CPU_SLEEP: cpu-sleep { 94 compatible = "arm,idle-state"; 95 local-timer-stop; 96 arm,psci-suspend-param = <0x0010000>; 97 entry-latency-us = <120>; 98 exit-latency-us = <250>; 99 min-residency-us = <900>; 100 }; 101 102 CLUSTER_SLEEP: cluster-sleep { 103 compatible = "arm,idle-state"; 104 local-timer-stop; 105 arm,psci-suspend-param = <0x1010000>; 106 entry-latency-us = <400>; 107 exit-latency-us = <500>; 108 min-residency-us = <2000>; 109 }; 110 }; 111 }; 112 113 cpu0_opp_table: cpu0-opp-table { 114 compatible = "operating-points-v2"; 115 opp-shared; 116 117 opp-600000000 { 118 opp-hz = /bits/ 64 <600000000>; 119 opp-microvolt = <950000 950000 1350000>; 120 clock-latency-ns = <40000>; 121 opp-suspend; 122 }; 123 opp-816000000 { 124 opp-hz = /bits/ 64 <816000000>; 125 opp-microvolt = <1050000 1050000 1350000>; 126 clock-latency-ns = <40000>; 127 }; 128 opp-1008000000 { 129 opp-hz = /bits/ 64 <1008000000>; 130 opp-microvolt = <1175000 1175000 1350000>; 131 clock-latency-ns = <40000>; 132 }; 133 opp-1200000000 { 134 opp-hz = /bits/ 64 <1200000000>; 135 opp-microvolt = <1300000 1300000 1350000>; 136 clock-latency-ns = <40000>; 137 }; 138 opp-1296000000 { 139 opp-hz = /bits/ 64 <1296000000>; 140 opp-microvolt = <1350000 1350000 1350000>; 141 clock-latency-ns = <40000>; 142 }; 143 }; 144 145 arm-pmu { 146 compatible = "arm,cortex-a35-pmu"; 147 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 148 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 149 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 150 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; 151 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; 152 }; 153 154 display_subsystem: display-subsystem { 155 compatible = "rockchip,display-subsystem"; 156 ports = <&vopb_out>, <&vopl_out>; 157 status = "disabled"; 158 }; 159 160 gmac_clkin: external-gmac-clock { 161 compatible = "fixed-clock"; 162 clock-frequency = <50000000>; 163 clock-output-names = "gmac_clkin"; 164 #clock-cells = <0>; 165 }; 166 167 psci { 168 compatible = "arm,psci-1.0"; 169 method = "smc"; 170 }; 171 172 timer { 173 compatible = "arm,armv8-timer"; 174 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 175 <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 176 <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>, 177 <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 178 }; 179 180 thermal_zones: thermal-zones { 181 soc_thermal: soc-thermal { 182 polling-delay-passive = <20>; 183 polling-delay = <1000>; 184 sustainable-power = <750>; 185 thermal-sensors = <&tsadc 0>; 186 187 trips { 188 threshold: trip-point-0 { 189 temperature = <70000>; 190 hysteresis = <2000>; 191 type = "passive"; 192 }; 193 194 target: trip-point-1 { 195 temperature = <85000>; 196 hysteresis = <2000>; 197 type = "passive"; 198 }; 199 200 soc_crit: soc-crit { 201 temperature = <115000>; 202 hysteresis = <2000>; 203 type = "critical"; 204 }; 205 }; 206 207 cooling-maps { 208 map0 { 209 trip = <&target>; 210 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 211 contribution = <4096>; 212 }; 213 214 map1 { 215 trip = <&target>; 216 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 217 contribution = <4096>; 218 }; 219 }; 220 }; 221 222 gpu_thermal: gpu-thermal { 223 polling-delay-passive = <100>; /* milliseconds */ 224 polling-delay = <1000>; /* milliseconds */ 225 thermal-sensors = <&tsadc 1>; 226 }; 227 }; 228 229 xin24m: xin24m { 230 compatible = "fixed-clock"; 231 #clock-cells = <0>; 232 clock-frequency = <24000000>; 233 clock-output-names = "xin24m"; 234 }; 235 236 pmu: power-management@ff000000 { 237 compatible = "rockchip,px30-pmu", "syscon", "simple-mfd"; 238 reg = <0x0 0xff000000 0x0 0x1000>; 239 240 power: power-controller { 241 compatible = "rockchip,px30-power-controller"; 242 #power-domain-cells = <1>; 243 #address-cells = <1>; 244 #size-cells = <0>; 245 246 /* These power domains are grouped by VD_LOGIC */ 247 pd_usb@PX30_PD_USB { 248 reg = <PX30_PD_USB>; 249 clocks = <&cru HCLK_HOST>, 250 <&cru HCLK_OTG>, 251 <&cru SCLK_OTG_ADP>; 252 pm_qos = <&qos_usb_host>, <&qos_usb_otg>; 253 }; 254 pd_sdcard@PX30_PD_SDCARD { 255 reg = <PX30_PD_SDCARD>; 256 clocks = <&cru HCLK_SDMMC>, 257 <&cru SCLK_SDMMC>; 258 pm_qos = <&qos_sdmmc>; 259 }; 260 pd_gmac@PX30_PD_GMAC { 261 reg = <PX30_PD_GMAC>; 262 clocks = <&cru ACLK_GMAC>, 263 <&cru PCLK_GMAC>, 264 <&cru SCLK_MAC_REF>, 265 <&cru SCLK_GMAC_RX_TX>; 266 pm_qos = <&qos_gmac>; 267 }; 268 pd_mmc_nand@PX30_PD_MMC_NAND { 269 reg = <PX30_PD_MMC_NAND>; 270 clocks = <&cru HCLK_NANDC>, 271 <&cru HCLK_EMMC>, 272 <&cru HCLK_SDIO>, 273 <&cru HCLK_SFC>, 274 <&cru SCLK_EMMC>, 275 <&cru SCLK_NANDC>, 276 <&cru SCLK_SDIO>, 277 <&cru SCLK_SFC>; 278 pm_qos = <&qos_emmc>, <&qos_nand>, 279 <&qos_sdio>, <&qos_sfc>; 280 }; 281 pd_vpu@PX30_PD_VPU { 282 reg = <PX30_PD_VPU>; 283 clocks = <&cru ACLK_VPU>, 284 <&cru HCLK_VPU>, 285 <&cru SCLK_CORE_VPU>; 286 pm_qos = <&qos_vpu>, <&qos_vpu_r128>; 287 }; 288 pd_vo@PX30_PD_VO { 289 reg = <PX30_PD_VO>; 290 clocks = <&cru ACLK_RGA>, 291 <&cru ACLK_VOPB>, 292 <&cru ACLK_VOPL>, 293 <&cru DCLK_VOPB>, 294 <&cru DCLK_VOPL>, 295 <&cru HCLK_RGA>, 296 <&cru HCLK_VOPB>, 297 <&cru HCLK_VOPL>, 298 <&cru PCLK_MIPI_DSI>, 299 <&cru SCLK_RGA_CORE>, 300 <&cru SCLK_VOPB_PWM>; 301 pm_qos = <&qos_rga_rd>, <&qos_rga_wr>, 302 <&qos_vop_m0>, <&qos_vop_m1>; 303 }; 304 pd_vi@PX30_PD_VI { 305 reg = <PX30_PD_VI>; 306 clocks = <&cru ACLK_CIF>, 307 <&cru ACLK_ISP>, 308 <&cru HCLK_CIF>, 309 <&cru HCLK_ISP>, 310 <&cru SCLK_ISP>; 311 pm_qos = <&qos_isp_128>, <&qos_isp_rd>, 312 <&qos_isp_wr>, <&qos_isp_m1>, 313 <&qos_vip>; 314 }; 315 pd_gpu@PX30_PD_GPU { 316 reg = <PX30_PD_GPU>; 317 clocks = <&cru SCLK_GPU>; 318 pm_qos = <&qos_gpu>; 319 }; 320 }; 321 }; 322 323 pmugrf: syscon@ff010000 { 324 compatible = "rockchip,px30-pmugrf", "syscon", "simple-mfd"; 325 reg = <0x0 0xff010000 0x0 0x1000>; 326 #address-cells = <1>; 327 #size-cells = <1>; 328 329 pmu_io_domains: io-domains { 330 compatible = "rockchip,px30-pmu-io-voltage-domain"; 331 status = "disabled"; 332 }; 333 334 reboot-mode { 335 compatible = "syscon-reboot-mode"; 336 offset = <0x200>; 337 mode-bootloader = <BOOT_BL_DOWNLOAD>; 338 mode-fastboot = <BOOT_FASTBOOT>; 339 mode-loader = <BOOT_BL_DOWNLOAD>; 340 mode-normal = <BOOT_NORMAL>; 341 mode-recovery = <BOOT_RECOVERY>; 342 }; 343 }; 344 345 uart0: serial@ff030000 { 346 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 347 reg = <0x0 0xff030000 0x0 0x100>; 348 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&pmucru SCLK_UART0_PMU>, <&pmucru PCLK_UART0_PMU>; 350 clock-names = "baudclk", "apb_pclk"; 351 dmas = <&dmac 0>, <&dmac 1>; 352 dma-names = "tx", "rx"; 353 reg-shift = <2>; 354 reg-io-width = <4>; 355 pinctrl-names = "default"; 356 pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; 357 status = "disabled"; 358 }; 359 360 i2s1_2ch: i2s@ff070000 { 361 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 362 reg = <0x0 0xff070000 0x0 0x1000>; 363 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 364 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1>; 365 clock-names = "i2s_clk", "i2s_hclk"; 366 dmas = <&dmac 18>, <&dmac 19>; 367 dma-names = "tx", "rx"; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2s1_2ch_sclk &i2s1_2ch_lrck 370 &i2s1_2ch_sdi &i2s1_2ch_sdo>; 371 #sound-dai-cells = <0>; 372 status = "disabled"; 373 }; 374 375 i2s2_2ch: i2s@ff080000 { 376 compatible = "rockchip,px30-i2s", "rockchip,rk3066-i2s"; 377 reg = <0x0 0xff080000 0x0 0x1000>; 378 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 379 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2>; 380 clock-names = "i2s_clk", "i2s_hclk"; 381 dmas = <&dmac 20>, <&dmac 21>; 382 dma-names = "tx", "rx"; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&i2s2_2ch_sclk &i2s2_2ch_lrck 385 &i2s2_2ch_sdi &i2s2_2ch_sdo>; 386 #sound-dai-cells = <0>; 387 status = "disabled"; 388 }; 389 390 gic: interrupt-controller@ff131000 { 391 compatible = "arm,gic-400"; 392 #interrupt-cells = <3>; 393 #address-cells = <0>; 394 interrupt-controller; 395 reg = <0x0 0xff131000 0 0x1000>, 396 <0x0 0xff132000 0 0x2000>, 397 <0x0 0xff134000 0 0x2000>, 398 <0x0 0xff136000 0 0x2000>; 399 interrupts = <GIC_PPI 9 400 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; 401 }; 402 403 grf: syscon@ff140000 { 404 compatible = "rockchip,px30-grf", "syscon", "simple-mfd"; 405 reg = <0x0 0xff140000 0x0 0x1000>; 406 #address-cells = <1>; 407 #size-cells = <1>; 408 409 io_domains: io-domains { 410 compatible = "rockchip,px30-io-voltage-domain"; 411 status = "disabled"; 412 }; 413 414 lvds: lvds { 415 compatible = "rockchip,px30-lvds"; 416 phys = <&dsi_dphy>; 417 phy-names = "dphy"; 418 rockchip,grf = <&grf>; 419 rockchip,output = "lvds"; 420 status = "disabled"; 421 422 ports { 423 #address-cells = <1>; 424 #size-cells = <0>; 425 426 port@0 { 427 reg = <0>; 428 #address-cells = <1>; 429 #size-cells = <0>; 430 431 lvds_vopb_in: endpoint@0 { 432 reg = <0>; 433 remote-endpoint = <&vopb_out_lvds>; 434 }; 435 436 lvds_vopl_in: endpoint@1 { 437 reg = <1>; 438 remote-endpoint = <&vopl_out_lvds>; 439 }; 440 }; 441 }; 442 }; 443 }; 444 445 uart1: serial@ff158000 { 446 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 447 reg = <0x0 0xff158000 0x0 0x100>; 448 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 449 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; 450 clock-names = "baudclk", "apb_pclk"; 451 dmas = <&dmac 2>, <&dmac 3>; 452 dma-names = "tx", "rx"; 453 reg-shift = <2>; 454 reg-io-width = <4>; 455 pinctrl-names = "default"; 456 pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>; 457 status = "disabled"; 458 }; 459 460 uart2: serial@ff160000 { 461 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 462 reg = <0x0 0xff160000 0x0 0x100>; 463 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 464 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; 465 clock-names = "baudclk", "apb_pclk"; 466 dmas = <&dmac 4>, <&dmac 5>; 467 dma-names = "tx", "rx"; 468 reg-shift = <2>; 469 reg-io-width = <4>; 470 pinctrl-names = "default"; 471 pinctrl-0 = <&uart2m0_xfer>; 472 status = "disabled"; 473 }; 474 475 uart3: serial@ff168000 { 476 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 477 reg = <0x0 0xff168000 0x0 0x100>; 478 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; 479 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; 480 clock-names = "baudclk", "apb_pclk"; 481 dmas = <&dmac 6>, <&dmac 7>; 482 dma-names = "tx", "rx"; 483 reg-shift = <2>; 484 reg-io-width = <4>; 485 pinctrl-names = "default"; 486 pinctrl-0 = <&uart3m1_xfer &uart3m1_cts &uart3m1_rts>; 487 status = "disabled"; 488 }; 489 490 uart4: serial@ff170000 { 491 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 492 reg = <0x0 0xff170000 0x0 0x100>; 493 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 494 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; 495 clock-names = "baudclk", "apb_pclk"; 496 dmas = <&dmac 8>, <&dmac 9>; 497 dma-names = "tx", "rx"; 498 reg-shift = <2>; 499 reg-io-width = <4>; 500 pinctrl-names = "default"; 501 pinctrl-0 = <&uart4_xfer &uart4_cts &uart4_rts>; 502 status = "disabled"; 503 }; 504 505 uart5: serial@ff178000 { 506 compatible = "rockchip,px30-uart", "snps,dw-apb-uart"; 507 reg = <0x0 0xff178000 0x0 0x100>; 508 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 509 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; 510 clock-names = "baudclk", "apb_pclk"; 511 dmas = <&dmac 10>, <&dmac 11>; 512 dma-names = "tx", "rx"; 513 reg-shift = <2>; 514 reg-io-width = <4>; 515 pinctrl-names = "default"; 516 pinctrl-0 = <&uart5_xfer &uart5_cts &uart5_rts>; 517 status = "disabled"; 518 }; 519 520 i2c0: i2c@ff180000 { 521 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 522 reg = <0x0 0xff180000 0x0 0x1000>; 523 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>; 524 clock-names = "i2c", "pclk"; 525 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; 526 pinctrl-names = "default"; 527 pinctrl-0 = <&i2c0_xfer>; 528 #address-cells = <1>; 529 #size-cells = <0>; 530 status = "disabled"; 531 }; 532 533 i2c1: i2c@ff190000 { 534 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 535 reg = <0x0 0xff190000 0x0 0x1000>; 536 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>; 537 clock-names = "i2c", "pclk"; 538 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 539 pinctrl-names = "default"; 540 pinctrl-0 = <&i2c1_xfer>; 541 #address-cells = <1>; 542 #size-cells = <0>; 543 status = "disabled"; 544 }; 545 546 i2c2: i2c@ff1a0000 { 547 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 548 reg = <0x0 0xff1a0000 0x0 0x1000>; 549 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>; 550 clock-names = "i2c", "pclk"; 551 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 552 pinctrl-names = "default"; 553 pinctrl-0 = <&i2c2_xfer>; 554 #address-cells = <1>; 555 #size-cells = <0>; 556 status = "disabled"; 557 }; 558 559 i2c3: i2c@ff1b0000 { 560 compatible = "rockchip,px30-i2c", "rockchip,rk3399-i2c"; 561 reg = <0x0 0xff1b0000 0x0 0x1000>; 562 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>; 563 clock-names = "i2c", "pclk"; 564 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 565 pinctrl-names = "default"; 566 pinctrl-0 = <&i2c3_xfer>; 567 #address-cells = <1>; 568 #size-cells = <0>; 569 status = "disabled"; 570 }; 571 572 spi0: spi@ff1d0000 { 573 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 574 reg = <0x0 0xff1d0000 0x0 0x1000>; 575 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 576 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; 577 clock-names = "spiclk", "apb_pclk"; 578 dmas = <&dmac 12>, <&dmac 13>; 579 dma-names = "tx", "rx"; 580 pinctrl-names = "default"; 581 pinctrl-0 = <&spi0_clk &spi0_csn &spi0_miso &spi0_mosi>; 582 #address-cells = <1>; 583 #size-cells = <0>; 584 status = "disabled"; 585 }; 586 587 spi1: spi@ff1d8000 { 588 compatible = "rockchip,px30-spi", "rockchip,rk3066-spi"; 589 reg = <0x0 0xff1d8000 0x0 0x1000>; 590 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 591 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>; 592 clock-names = "spiclk", "apb_pclk"; 593 dmas = <&dmac 14>, <&dmac 15>; 594 dma-names = "tx", "rx"; 595 pinctrl-names = "default"; 596 pinctrl-0 = <&spi1_clk &spi1_csn0 &spi1_csn1 &spi1_miso &spi1_mosi>; 597 #address-cells = <1>; 598 #size-cells = <0>; 599 status = "disabled"; 600 }; 601 602 wdt: watchdog@ff1e0000 { 603 compatible = "rockchip,px30-wdt", "snps,dw-wdt"; 604 reg = <0x0 0xff1e0000 0x0 0x100>; 605 clocks = <&cru PCLK_WDT_NS>; 606 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 607 status = "disabled"; 608 }; 609 610 pwm0: pwm@ff200000 { 611 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 612 reg = <0x0 0xff200000 0x0 0x10>; 613 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 614 clock-names = "pwm", "pclk"; 615 pinctrl-names = "default"; 616 pinctrl-0 = <&pwm0_pin>; 617 #pwm-cells = <3>; 618 status = "disabled"; 619 }; 620 621 pwm1: pwm@ff200010 { 622 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 623 reg = <0x0 0xff200010 0x0 0x10>; 624 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 625 clock-names = "pwm", "pclk"; 626 pinctrl-names = "default"; 627 pinctrl-0 = <&pwm1_pin>; 628 #pwm-cells = <3>; 629 status = "disabled"; 630 }; 631 632 pwm2: pwm@ff200020 { 633 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 634 reg = <0x0 0xff200020 0x0 0x10>; 635 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 636 clock-names = "pwm", "pclk"; 637 pinctrl-names = "default"; 638 pinctrl-0 = <&pwm2_pin>; 639 #pwm-cells = <3>; 640 status = "disabled"; 641 }; 642 643 pwm3: pwm@ff200030 { 644 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 645 reg = <0x0 0xff200030 0x0 0x10>; 646 clocks = <&cru SCLK_PWM0>, <&cru PCLK_PWM0>; 647 clock-names = "pwm", "pclk"; 648 pinctrl-names = "default"; 649 pinctrl-0 = <&pwm3_pin>; 650 #pwm-cells = <3>; 651 status = "disabled"; 652 }; 653 654 pwm4: pwm@ff208000 { 655 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 656 reg = <0x0 0xff208000 0x0 0x10>; 657 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 658 clock-names = "pwm", "pclk"; 659 pinctrl-names = "default"; 660 pinctrl-0 = <&pwm4_pin>; 661 #pwm-cells = <3>; 662 status = "disabled"; 663 }; 664 665 pwm5: pwm@ff208010 { 666 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 667 reg = <0x0 0xff208010 0x0 0x10>; 668 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 669 clock-names = "pwm", "pclk"; 670 pinctrl-names = "default"; 671 pinctrl-0 = <&pwm5_pin>; 672 #pwm-cells = <3>; 673 status = "disabled"; 674 }; 675 676 pwm6: pwm@ff208020 { 677 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 678 reg = <0x0 0xff208020 0x0 0x10>; 679 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 680 clock-names = "pwm", "pclk"; 681 pinctrl-names = "default"; 682 pinctrl-0 = <&pwm6_pin>; 683 #pwm-cells = <3>; 684 status = "disabled"; 685 }; 686 687 pwm7: pwm@ff208030 { 688 compatible = "rockchip,px30-pwm", "rockchip,rk3328-pwm"; 689 reg = <0x0 0xff208030 0x0 0x10>; 690 clocks = <&cru SCLK_PWM1>, <&cru PCLK_PWM1>; 691 clock-names = "pwm", "pclk"; 692 pinctrl-names = "default"; 693 pinctrl-0 = <&pwm7_pin>; 694 #pwm-cells = <3>; 695 status = "disabled"; 696 }; 697 698 rktimer: timer@ff210000 { 699 compatible = "rockchip,px30-timer", "rockchip,rk3288-timer"; 700 reg = <0x0 0xff210000 0x0 0x1000>; 701 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 702 clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>; 703 clock-names = "pclk", "timer"; 704 }; 705 706 dmac: dmac@ff240000 { 707 compatible = "arm,pl330", "arm,primecell"; 708 reg = <0x0 0xff240000 0x0 0x4000>; 709 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, 710 <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; 711 arm,pl330-periph-burst; 712 clocks = <&cru ACLK_DMAC>; 713 clock-names = "apb_pclk"; 714 #dma-cells = <1>; 715 }; 716 717 tsadc: tsadc@ff280000 { 718 compatible = "rockchip,px30-tsadc"; 719 reg = <0x0 0xff280000 0x0 0x100>; 720 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; 721 assigned-clocks = <&cru SCLK_TSADC>; 722 assigned-clock-rates = <50000>; 723 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>; 724 clock-names = "tsadc", "apb_pclk"; 725 resets = <&cru SRST_TSADC>; 726 reset-names = "tsadc-apb"; 727 rockchip,grf = <&grf>; 728 rockchip,hw-tshut-temp = <120000>; 729 pinctrl-names = "init", "default", "sleep"; 730 pinctrl-0 = <&tsadc_otp_pin>; 731 pinctrl-1 = <&tsadc_otp_out>; 732 pinctrl-2 = <&tsadc_otp_pin>; 733 #thermal-sensor-cells = <1>; 734 status = "disabled"; 735 }; 736 737 saradc: saradc@ff288000 { 738 compatible = "rockchip,px30-saradc", "rockchip,rk3399-saradc"; 739 reg = <0x0 0xff288000 0x0 0x100>; 740 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 741 #io-channel-cells = <1>; 742 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; 743 clock-names = "saradc", "apb_pclk"; 744 resets = <&cru SRST_SARADC_P>; 745 reset-names = "saradc-apb"; 746 status = "disabled"; 747 }; 748 749 otp: nvmem@ff290000 { 750 compatible = "rockchip,px30-otp"; 751 reg = <0x0 0xff290000 0x0 0x4000>; 752 clocks = <&cru SCLK_OTP_USR>, <&cru PCLK_OTP_NS>, 753 <&cru PCLK_OTP_PHY>; 754 clock-names = "otp", "apb_pclk", "phy"; 755 resets = <&cru SRST_OTP_PHY>; 756 reset-names = "phy"; 757 #address-cells = <1>; 758 #size-cells = <1>; 759 760 /* Data cells */ 761 cpu_id: id@7 { 762 reg = <0x07 0x10>; 763 }; 764 cpu_leakage: cpu-leakage@17 { 765 reg = <0x17 0x1>; 766 }; 767 performance: performance@1e { 768 reg = <0x1e 0x1>; 769 bits = <4 3>; 770 }; 771 }; 772 773 cru: clock-controller@ff2b0000 { 774 compatible = "rockchip,px30-cru"; 775 reg = <0x0 0xff2b0000 0x0 0x1000>; 776 clocks = <&xin24m>, <&pmucru PLL_GPLL>; 777 clock-names = "xin24m", "gpll"; 778 rockchip,grf = <&grf>; 779 #clock-cells = <1>; 780 #reset-cells = <1>; 781 782 assigned-clocks = <&cru PLL_NPLL>, 783 <&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>, 784 <&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>, 785 <&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>; 786 787 assigned-clock-rates = <1188000000>, 788 <200000000>, <200000000>, 789 <150000000>, <150000000>, 790 <100000000>, <200000000>; 791 }; 792 793 pmucru: clock-controller@ff2bc000 { 794 compatible = "rockchip,px30-pmucru"; 795 reg = <0x0 0xff2bc000 0x0 0x1000>; 796 clocks = <&xin24m>; 797 clock-names = "xin24m"; 798 rockchip,grf = <&grf>; 799 #clock-cells = <1>; 800 #reset-cells = <1>; 801 802 assigned-clocks = 803 <&pmucru PLL_GPLL>, <&pmucru PCLK_PMU_PRE>, 804 <&pmucru SCLK_WIFI_PMU>; 805 assigned-clock-rates = 806 <1200000000>, <100000000>, 807 <26000000>; 808 }; 809 810 usb2phy_grf: syscon@ff2c0000 { 811 compatible = "rockchip,px30-usb2phy-grf", "syscon", 812 "simple-mfd"; 813 reg = <0x0 0xff2c0000 0x0 0x10000>; 814 #address-cells = <1>; 815 #size-cells = <1>; 816 817 u2phy: usb2-phy@100 { 818 compatible = "rockchip,px30-usb2phy"; 819 reg = <0x100 0x20>; 820 clocks = <&pmucru SCLK_USBPHY_REF>; 821 clock-names = "phyclk"; 822 #clock-cells = <0>; 823 assigned-clocks = <&cru USB480M>; 824 assigned-clock-parents = <&u2phy>; 825 clock-output-names = "usb480m_phy"; 826 status = "disabled"; 827 828 u2phy_host: host-port { 829 #phy-cells = <0>; 830 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 831 interrupt-names = "linestate"; 832 status = "disabled"; 833 }; 834 835 u2phy_otg: otg-port { 836 #phy-cells = <0>; 837 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 840 interrupt-names = "otg-bvalid", "otg-id", 841 "linestate"; 842 status = "disabled"; 843 }; 844 }; 845 }; 846 847 dsi_dphy: phy@ff2e0000 { 848 compatible = "rockchip,px30-dsi-dphy"; 849 reg = <0x0 0xff2e0000 0x0 0x10000>; 850 clocks = <&pmucru SCLK_MIPIDSIPHY_REF>, <&cru PCLK_MIPIDSIPHY>; 851 clock-names = "ref", "pclk"; 852 resets = <&cru SRST_MIPIDSIPHY_P>; 853 reset-names = "apb"; 854 #phy-cells = <0>; 855 power-domains = <&power PX30_PD_VO>; 856 status = "disabled"; 857 }; 858 859 usb20_otg: usb@ff300000 { 860 compatible = "rockchip,px30-usb", "rockchip,rk3066-usb", 861 "snps,dwc2"; 862 reg = <0x0 0xff300000 0x0 0x40000>; 863 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 864 clocks = <&cru HCLK_OTG>; 865 clock-names = "otg"; 866 dr_mode = "otg"; 867 g-np-tx-fifo-size = <16>; 868 g-rx-fifo-size = <280>; 869 g-tx-fifo-size = <256 128 128 64 32 16>; 870 phys = <&u2phy_otg>; 871 phy-names = "usb2-phy"; 872 power-domains = <&power PX30_PD_USB>; 873 status = "disabled"; 874 }; 875 876 usb_host0_ehci: usb@ff340000 { 877 compatible = "generic-ehci"; 878 reg = <0x0 0xff340000 0x0 0x10000>; 879 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; 880 clocks = <&cru HCLK_HOST>; 881 phys = <&u2phy_host>; 882 phy-names = "usb"; 883 power-domains = <&power PX30_PD_USB>; 884 status = "disabled"; 885 }; 886 887 usb_host0_ohci: usb@ff350000 { 888 compatible = "generic-ohci"; 889 reg = <0x0 0xff350000 0x0 0x10000>; 890 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 891 clocks = <&cru HCLK_HOST>; 892 phys = <&u2phy_host>; 893 phy-names = "usb"; 894 power-domains = <&power PX30_PD_USB>; 895 status = "disabled"; 896 }; 897 898 gmac: ethernet@ff360000 { 899 compatible = "rockchip,px30-gmac"; 900 reg = <0x0 0xff360000 0x0 0x10000>; 901 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 902 interrupt-names = "macirq"; 903 clocks = <&cru SCLK_GMAC>, <&cru SCLK_GMAC_RX_TX>, 904 <&cru SCLK_GMAC_RX_TX>, <&cru SCLK_MAC_REF>, 905 <&cru SCLK_MAC_REFOUT>, <&cru ACLK_GMAC>, 906 <&cru PCLK_GMAC>, <&cru SCLK_GMAC_RMII>; 907 clock-names = "stmmaceth", "mac_clk_rx", 908 "mac_clk_tx", "clk_mac_ref", 909 "clk_mac_refout", "aclk_mac", 910 "pclk_mac", "clk_mac_speed"; 911 rockchip,grf = <&grf>; 912 phy-mode = "rmii"; 913 pinctrl-names = "default"; 914 pinctrl-0 = <&rmii_pins &mac_refclk_12ma>; 915 power-domains = <&power PX30_PD_GMAC>; 916 resets = <&cru SRST_GMAC_A>; 917 reset-names = "stmmaceth"; 918 status = "disabled"; 919 }; 920 921 sdmmc: mmc@ff370000 { 922 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 923 reg = <0x0 0xff370000 0x0 0x4000>; 924 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 925 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, 926 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; 927 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 928 bus-width = <4>; 929 fifo-depth = <0x100>; 930 max-frequency = <150000000>; 931 pinctrl-names = "default"; 932 pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>; 933 power-domains = <&power PX30_PD_SDCARD>; 934 status = "disabled"; 935 }; 936 937 sdio: mmc@ff380000 { 938 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 939 reg = <0x0 0xff380000 0x0 0x4000>; 940 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, 942 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; 943 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 944 bus-width = <4>; 945 fifo-depth = <0x100>; 946 max-frequency = <150000000>; 947 pinctrl-names = "default"; 948 pinctrl-0 = <&sdio_bus4 &sdio_cmd &sdio_clk>; 949 power-domains = <&power PX30_PD_MMC_NAND>; 950 status = "disabled"; 951 }; 952 953 emmc: mmc@ff390000 { 954 compatible = "rockchip,px30-dw-mshc", "rockchip,rk3288-dw-mshc"; 955 reg = <0x0 0xff390000 0x0 0x4000>; 956 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 957 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, 958 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; 959 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; 960 bus-width = <8>; 961 fifo-depth = <0x100>; 962 max-frequency = <150000000>; 963 pinctrl-names = "default"; 964 pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; 965 power-domains = <&power PX30_PD_MMC_NAND>; 966 status = "disabled"; 967 }; 968 969 nfc: nand-controller@ff3b0000 { 970 compatible = "rockchip,px30-nfc"; 971 reg = <0x0 0xff3b0000 0x0 0x4000>; 972 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 973 clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; 974 clock-names = "ahb", "nfc"; 975 assigned-clocks = <&cru SCLK_NANDC>; 976 assigned-clock-rates = <150000000>; 977 pinctrl-names = "default"; 978 pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 979 &flash_rdn &flash_rdy &flash_wrn &flash_dqs>; 980 power-domains = <&power PX30_PD_MMC_NAND>; 981 status = "disabled"; 982 }; 983 984 gpu_opp_table: opp-table2 { 985 compatible = "operating-points-v2"; 986 987 opp-200000000 { 988 opp-hz = /bits/ 64 <200000000>; 989 opp-microvolt = <950000>; 990 }; 991 opp-300000000 { 992 opp-hz = /bits/ 64 <300000000>; 993 opp-microvolt = <975000>; 994 }; 995 opp-400000000 { 996 opp-hz = /bits/ 64 <400000000>; 997 opp-microvolt = <1050000>; 998 }; 999 opp-480000000 { 1000 opp-hz = /bits/ 64 <480000000>; 1001 opp-microvolt = <1125000>; 1002 }; 1003 }; 1004 1005 gpu: gpu@ff400000 { 1006 compatible = "rockchip,px30-mali", "arm,mali-bifrost"; 1007 reg = <0x0 0xff400000 0x0 0x4000>; 1008 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, 1009 <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, 1010 <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 1011 interrupt-names = "job", "mmu", "gpu"; 1012 clocks = <&cru SCLK_GPU>; 1013 #cooling-cells = <2>; 1014 power-domains = <&power PX30_PD_GPU>; 1015 operating-points-v2 = <&gpu_opp_table>; 1016 status = "disabled"; 1017 }; 1018 1019 dsi: dsi@ff450000 { 1020 compatible = "rockchip,px30-mipi-dsi"; 1021 reg = <0x0 0xff450000 0x0 0x10000>; 1022 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 1023 clocks = <&cru PCLK_MIPI_DSI>; 1024 clock-names = "pclk"; 1025 phys = <&dsi_dphy>; 1026 phy-names = "dphy"; 1027 power-domains = <&power PX30_PD_VO>; 1028 resets = <&cru SRST_MIPIDSI_HOST_P>; 1029 reset-names = "apb"; 1030 rockchip,grf = <&grf>; 1031 #address-cells = <1>; 1032 #size-cells = <0>; 1033 status = "disabled"; 1034 1035 ports { 1036 #address-cells = <1>; 1037 #size-cells = <0>; 1038 1039 port@0 { 1040 reg = <0>; 1041 #address-cells = <1>; 1042 #size-cells = <0>; 1043 1044 dsi_in_vopb: endpoint@0 { 1045 reg = <0>; 1046 remote-endpoint = <&vopb_out_dsi>; 1047 }; 1048 1049 dsi_in_vopl: endpoint@1 { 1050 reg = <1>; 1051 remote-endpoint = <&vopl_out_dsi>; 1052 }; 1053 }; 1054 }; 1055 }; 1056 1057 vopb: vop@ff460000 { 1058 compatible = "rockchip,px30-vop-big"; 1059 reg = <0x0 0xff460000 0x0 0xefc>; 1060 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1061 clocks = <&cru ACLK_VOPB>, <&cru DCLK_VOPB>, 1062 <&cru HCLK_VOPB>; 1063 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1064 resets = <&cru SRST_VOPB_A>, <&cru SRST_VOPB_H>, <&cru SRST_VOPB>; 1065 reset-names = "axi", "ahb", "dclk"; 1066 iommus = <&vopb_mmu>; 1067 power-domains = <&power PX30_PD_VO>; 1068 status = "disabled"; 1069 1070 vopb_out: port { 1071 #address-cells = <1>; 1072 #size-cells = <0>; 1073 1074 vopb_out_dsi: endpoint@0 { 1075 reg = <0>; 1076 remote-endpoint = <&dsi_in_vopb>; 1077 }; 1078 1079 vopb_out_lvds: endpoint@1 { 1080 reg = <1>; 1081 remote-endpoint = <&lvds_vopb_in>; 1082 }; 1083 }; 1084 }; 1085 1086 vopb_mmu: iommu@ff460f00 { 1087 compatible = "rockchip,iommu"; 1088 reg = <0x0 0xff460f00 0x0 0x100>; 1089 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 1090 interrupt-names = "vopb_mmu"; 1091 clocks = <&cru ACLK_VOPB>, <&cru HCLK_VOPB>; 1092 clock-names = "aclk", "iface"; 1093 power-domains = <&power PX30_PD_VO>; 1094 #iommu-cells = <0>; 1095 status = "disabled"; 1096 }; 1097 1098 vopl: vop@ff470000 { 1099 compatible = "rockchip,px30-vop-lit"; 1100 reg = <0x0 0xff470000 0x0 0xefc>; 1101 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1102 clocks = <&cru ACLK_VOPL>, <&cru DCLK_VOPL>, 1103 <&cru HCLK_VOPL>; 1104 clock-names = "aclk_vop", "dclk_vop", "hclk_vop"; 1105 resets = <&cru SRST_VOPL_A>, <&cru SRST_VOPL_H>, <&cru SRST_VOPL>; 1106 reset-names = "axi", "ahb", "dclk"; 1107 iommus = <&vopl_mmu>; 1108 power-domains = <&power PX30_PD_VO>; 1109 status = "disabled"; 1110 1111 vopl_out: port { 1112 #address-cells = <1>; 1113 #size-cells = <0>; 1114 1115 vopl_out_dsi: endpoint@0 { 1116 reg = <0>; 1117 remote-endpoint = <&dsi_in_vopl>; 1118 }; 1119 1120 vopl_out_lvds: endpoint@1 { 1121 reg = <1>; 1122 remote-endpoint = <&lvds_vopl_in>; 1123 }; 1124 }; 1125 }; 1126 1127 vopl_mmu: iommu@ff470f00 { 1128 compatible = "rockchip,iommu"; 1129 reg = <0x0 0xff470f00 0x0 0x100>; 1130 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 1131 interrupt-names = "vopl_mmu"; 1132 clocks = <&cru ACLK_VOPL>, <&cru HCLK_VOPL>; 1133 clock-names = "aclk", "iface"; 1134 power-domains = <&power PX30_PD_VO>; 1135 #iommu-cells = <0>; 1136 status = "disabled"; 1137 }; 1138 1139 qos_gmac: qos@ff518000 { 1140 compatible = "rockchip,px30-qos", "syscon"; 1141 reg = <0x0 0xff518000 0x0 0x20>; 1142 }; 1143 1144 qos_gpu: qos@ff520000 { 1145 compatible = "rockchip,px30-qos", "syscon"; 1146 reg = <0x0 0xff520000 0x0 0x20>; 1147 }; 1148 1149 qos_sdmmc: qos@ff52c000 { 1150 compatible = "rockchip,px30-qos", "syscon"; 1151 reg = <0x0 0xff52c000 0x0 0x20>; 1152 }; 1153 1154 qos_emmc: qos@ff538000 { 1155 compatible = "rockchip,px30-qos", "syscon"; 1156 reg = <0x0 0xff538000 0x0 0x20>; 1157 }; 1158 1159 qos_nand: qos@ff538080 { 1160 compatible = "rockchip,px30-qos", "syscon"; 1161 reg = <0x0 0xff538080 0x0 0x20>; 1162 }; 1163 1164 qos_sdio: qos@ff538100 { 1165 compatible = "rockchip,px30-qos", "syscon"; 1166 reg = <0x0 0xff538100 0x0 0x20>; 1167 }; 1168 1169 qos_sfc: qos@ff538180 { 1170 compatible = "rockchip,px30-qos", "syscon"; 1171 reg = <0x0 0xff538180 0x0 0x20>; 1172 }; 1173 1174 qos_usb_host: qos@ff540000 { 1175 compatible = "rockchip,px30-qos", "syscon"; 1176 reg = <0x0 0xff540000 0x0 0x20>; 1177 }; 1178 1179 qos_usb_otg: qos@ff540080 { 1180 compatible = "rockchip,px30-qos", "syscon"; 1181 reg = <0x0 0xff540080 0x0 0x20>; 1182 }; 1183 1184 qos_isp_128: qos@ff548000 { 1185 compatible = "rockchip,px30-qos", "syscon"; 1186 reg = <0x0 0xff548000 0x0 0x20>; 1187 }; 1188 1189 qos_isp_rd: qos@ff548080 { 1190 compatible = "rockchip,px30-qos", "syscon"; 1191 reg = <0x0 0xff548080 0x0 0x20>; 1192 }; 1193 1194 qos_isp_wr: qos@ff548100 { 1195 compatible = "rockchip,px30-qos", "syscon"; 1196 reg = <0x0 0xff548100 0x0 0x20>; 1197 }; 1198 1199 qos_isp_m1: qos@ff548180 { 1200 compatible = "rockchip,px30-qos", "syscon"; 1201 reg = <0x0 0xff548180 0x0 0x20>; 1202 }; 1203 1204 qos_vip: qos@ff548200 { 1205 compatible = "rockchip,px30-qos", "syscon"; 1206 reg = <0x0 0xff548200 0x0 0x20>; 1207 }; 1208 1209 qos_rga_rd: qos@ff550000 { 1210 compatible = "rockchip,px30-qos", "syscon"; 1211 reg = <0x0 0xff550000 0x0 0x20>; 1212 }; 1213 1214 qos_rga_wr: qos@ff550080 { 1215 compatible = "rockchip,px30-qos", "syscon"; 1216 reg = <0x0 0xff550080 0x0 0x20>; 1217 }; 1218 1219 qos_vop_m0: qos@ff550100 { 1220 compatible = "rockchip,px30-qos", "syscon"; 1221 reg = <0x0 0xff550100 0x0 0x20>; 1222 }; 1223 1224 qos_vop_m1: qos@ff550180 { 1225 compatible = "rockchip,px30-qos", "syscon"; 1226 reg = <0x0 0xff550180 0x0 0x20>; 1227 }; 1228 1229 qos_vpu: qos@ff558000 { 1230 compatible = "rockchip,px30-qos", "syscon"; 1231 reg = <0x0 0xff558000 0x0 0x20>; 1232 }; 1233 1234 qos_vpu_r128: qos@ff558080 { 1235 compatible = "rockchip,px30-qos", "syscon"; 1236 reg = <0x0 0xff558080 0x0 0x20>; 1237 }; 1238 1239 pinctrl: pinctrl { 1240 compatible = "rockchip,px30-pinctrl"; 1241 rockchip,grf = <&grf>; 1242 rockchip,pmu = <&pmugrf>; 1243 #address-cells = <2>; 1244 #size-cells = <2>; 1245 ranges; 1246 1247 gpio0: gpio0@ff040000 { 1248 compatible = "rockchip,gpio-bank"; 1249 reg = <0x0 0xff040000 0x0 0x100>; 1250 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; 1251 clocks = <&pmucru PCLK_GPIO0_PMU>; 1252 gpio-controller; 1253 #gpio-cells = <2>; 1254 1255 interrupt-controller; 1256 #interrupt-cells = <2>; 1257 }; 1258 1259 gpio1: gpio1@ff250000 { 1260 compatible = "rockchip,gpio-bank"; 1261 reg = <0x0 0xff250000 0x0 0x100>; 1262 interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; 1263 clocks = <&cru PCLK_GPIO1>; 1264 gpio-controller; 1265 #gpio-cells = <2>; 1266 1267 interrupt-controller; 1268 #interrupt-cells = <2>; 1269 }; 1270 1271 gpio2: gpio2@ff260000 { 1272 compatible = "rockchip,gpio-bank"; 1273 reg = <0x0 0xff260000 0x0 0x100>; 1274 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1275 clocks = <&cru PCLK_GPIO2>; 1276 gpio-controller; 1277 #gpio-cells = <2>; 1278 1279 interrupt-controller; 1280 #interrupt-cells = <2>; 1281 }; 1282 1283 gpio3: gpio3@ff270000 { 1284 compatible = "rockchip,gpio-bank"; 1285 reg = <0x0 0xff270000 0x0 0x100>; 1286 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 1287 clocks = <&cru PCLK_GPIO3>; 1288 gpio-controller; 1289 #gpio-cells = <2>; 1290 1291 interrupt-controller; 1292 #interrupt-cells = <2>; 1293 }; 1294 1295 pcfg_pull_up: pcfg-pull-up { 1296 bias-pull-up; 1297 }; 1298 1299 pcfg_pull_down: pcfg-pull-down { 1300 bias-pull-down; 1301 }; 1302 1303 pcfg_pull_none: pcfg-pull-none { 1304 bias-disable; 1305 }; 1306 1307 pcfg_pull_none_2ma: pcfg-pull-none-2ma { 1308 bias-disable; 1309 drive-strength = <2>; 1310 }; 1311 1312 pcfg_pull_up_2ma: pcfg-pull-up-2ma { 1313 bias-pull-up; 1314 drive-strength = <2>; 1315 }; 1316 1317 pcfg_pull_up_4ma: pcfg-pull-up-4ma { 1318 bias-pull-up; 1319 drive-strength = <4>; 1320 }; 1321 1322 pcfg_pull_none_4ma: pcfg-pull-none-4ma { 1323 bias-disable; 1324 drive-strength = <4>; 1325 }; 1326 1327 pcfg_pull_down_4ma: pcfg-pull-down-4ma { 1328 bias-pull-down; 1329 drive-strength = <4>; 1330 }; 1331 1332 pcfg_pull_none_8ma: pcfg-pull-none-8ma { 1333 bias-disable; 1334 drive-strength = <8>; 1335 }; 1336 1337 pcfg_pull_up_8ma: pcfg-pull-up-8ma { 1338 bias-pull-up; 1339 drive-strength = <8>; 1340 }; 1341 1342 pcfg_pull_none_12ma: pcfg-pull-none-12ma { 1343 bias-disable; 1344 drive-strength = <12>; 1345 }; 1346 1347 pcfg_pull_up_12ma: pcfg-pull-up-12ma { 1348 bias-pull-up; 1349 drive-strength = <12>; 1350 }; 1351 1352 pcfg_pull_none_smt: pcfg-pull-none-smt { 1353 bias-disable; 1354 input-schmitt-enable; 1355 }; 1356 1357 pcfg_output_high: pcfg-output-high { 1358 output-high; 1359 }; 1360 1361 pcfg_output_low: pcfg-output-low { 1362 output-low; 1363 }; 1364 1365 pcfg_input_high: pcfg-input-high { 1366 bias-pull-up; 1367 input-enable; 1368 }; 1369 1370 pcfg_input: pcfg-input { 1371 input-enable; 1372 }; 1373 1374 i2c0 { 1375 i2c0_xfer: i2c0-xfer { 1376 rockchip,pins = 1377 <0 RK_PB0 1 &pcfg_pull_none_smt>, 1378 <0 RK_PB1 1 &pcfg_pull_none_smt>; 1379 }; 1380 }; 1381 1382 i2c1 { 1383 i2c1_xfer: i2c1-xfer { 1384 rockchip,pins = 1385 <0 RK_PC2 1 &pcfg_pull_none_smt>, 1386 <0 RK_PC3 1 &pcfg_pull_none_smt>; 1387 }; 1388 }; 1389 1390 i2c2 { 1391 i2c2_xfer: i2c2-xfer { 1392 rockchip,pins = 1393 <2 RK_PB7 2 &pcfg_pull_none_smt>, 1394 <2 RK_PC0 2 &pcfg_pull_none_smt>; 1395 }; 1396 }; 1397 1398 i2c3 { 1399 i2c3_xfer: i2c3-xfer { 1400 rockchip,pins = 1401 <1 RK_PB4 4 &pcfg_pull_none_smt>, 1402 <1 RK_PB5 4 &pcfg_pull_none_smt>; 1403 }; 1404 }; 1405 1406 tsadc { 1407 tsadc_otp_pin: tsadc-otp-pin { 1408 rockchip,pins = 1409 <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>; 1410 }; 1411 1412 tsadc_otp_out: tsadc-otp-out { 1413 rockchip,pins = 1414 <0 RK_PA6 1 &pcfg_pull_none>; 1415 }; 1416 }; 1417 1418 uart0 { 1419 uart0_xfer: uart0-xfer { 1420 rockchip,pins = 1421 <0 RK_PB2 1 &pcfg_pull_up>, 1422 <0 RK_PB3 1 &pcfg_pull_up>; 1423 }; 1424 1425 uart0_cts: uart0-cts { 1426 rockchip,pins = 1427 <0 RK_PB4 1 &pcfg_pull_none>; 1428 }; 1429 1430 uart0_rts: uart0-rts { 1431 rockchip,pins = 1432 <0 RK_PB5 1 &pcfg_pull_none>; 1433 }; 1434 }; 1435 1436 uart1 { 1437 uart1_xfer: uart1-xfer { 1438 rockchip,pins = 1439 <1 RK_PC1 1 &pcfg_pull_up>, 1440 <1 RK_PC0 1 &pcfg_pull_up>; 1441 }; 1442 1443 uart1_cts: uart1-cts { 1444 rockchip,pins = 1445 <1 RK_PC2 1 &pcfg_pull_none>; 1446 }; 1447 1448 uart1_rts: uart1-rts { 1449 rockchip,pins = 1450 <1 RK_PC3 1 &pcfg_pull_none>; 1451 }; 1452 }; 1453 1454 uart2-m0 { 1455 uart2m0_xfer: uart2m0-xfer { 1456 rockchip,pins = 1457 <1 RK_PD2 2 &pcfg_pull_up>, 1458 <1 RK_PD3 2 &pcfg_pull_up>; 1459 }; 1460 }; 1461 1462 uart2-m1 { 1463 uart2m1_xfer: uart2m1-xfer { 1464 rockchip,pins = 1465 <2 RK_PB4 2 &pcfg_pull_up>, 1466 <2 RK_PB6 2 &pcfg_pull_up>; 1467 }; 1468 }; 1469 1470 uart3-m0 { 1471 uart3m0_xfer: uart3m0-xfer { 1472 rockchip,pins = 1473 <0 RK_PC0 2 &pcfg_pull_up>, 1474 <0 RK_PC1 2 &pcfg_pull_up>; 1475 }; 1476 1477 uart3m0_cts: uart3m0-cts { 1478 rockchip,pins = 1479 <0 RK_PC2 2 &pcfg_pull_none>; 1480 }; 1481 1482 uart3m0_rts: uart3m0-rts { 1483 rockchip,pins = 1484 <0 RK_PC3 2 &pcfg_pull_none>; 1485 }; 1486 }; 1487 1488 uart3-m1 { 1489 uart3m1_xfer: uart3m1-xfer { 1490 rockchip,pins = 1491 <1 RK_PB6 2 &pcfg_pull_up>, 1492 <1 RK_PB7 2 &pcfg_pull_up>; 1493 }; 1494 1495 uart3m1_cts: uart3m1-cts { 1496 rockchip,pins = 1497 <1 RK_PB4 2 &pcfg_pull_none>; 1498 }; 1499 1500 uart3m1_rts: uart3m1-rts { 1501 rockchip,pins = 1502 <1 RK_PB5 2 &pcfg_pull_none>; 1503 }; 1504 }; 1505 1506 uart4 { 1507 uart4_xfer: uart4-xfer { 1508 rockchip,pins = 1509 <1 RK_PD4 2 &pcfg_pull_up>, 1510 <1 RK_PD5 2 &pcfg_pull_up>; 1511 }; 1512 1513 uart4_cts: uart4-cts { 1514 rockchip,pins = 1515 <1 RK_PD6 2 &pcfg_pull_none>; 1516 }; 1517 1518 uart4_rts: uart4-rts { 1519 rockchip,pins = 1520 <1 RK_PD7 2 &pcfg_pull_none>; 1521 }; 1522 }; 1523 1524 uart5 { 1525 uart5_xfer: uart5-xfer { 1526 rockchip,pins = 1527 <3 RK_PA2 4 &pcfg_pull_up>, 1528 <3 RK_PA1 4 &pcfg_pull_up>; 1529 }; 1530 1531 uart5_cts: uart5-cts { 1532 rockchip,pins = 1533 <3 RK_PA3 4 &pcfg_pull_none>; 1534 }; 1535 1536 uart5_rts: uart5-rts { 1537 rockchip,pins = 1538 <3 RK_PA5 4 &pcfg_pull_none>; 1539 }; 1540 }; 1541 1542 spi0 { 1543 spi0_clk: spi0-clk { 1544 rockchip,pins = 1545 <1 RK_PB7 3 &pcfg_pull_up_4ma>; 1546 }; 1547 1548 spi0_csn: spi0-csn { 1549 rockchip,pins = 1550 <1 RK_PB6 3 &pcfg_pull_up_4ma>; 1551 }; 1552 1553 spi0_miso: spi0-miso { 1554 rockchip,pins = 1555 <1 RK_PB5 3 &pcfg_pull_up_4ma>; 1556 }; 1557 1558 spi0_mosi: spi0-mosi { 1559 rockchip,pins = 1560 <1 RK_PB4 3 &pcfg_pull_up_4ma>; 1561 }; 1562 1563 spi0_clk_hs: spi0-clk-hs { 1564 rockchip,pins = 1565 <1 RK_PB7 3 &pcfg_pull_up_8ma>; 1566 }; 1567 1568 spi0_miso_hs: spi0-miso-hs { 1569 rockchip,pins = 1570 <1 RK_PB5 3 &pcfg_pull_up_8ma>; 1571 }; 1572 1573 spi0_mosi_hs: spi0-mosi-hs { 1574 rockchip,pins = 1575 <1 RK_PB4 3 &pcfg_pull_up_8ma>; 1576 }; 1577 }; 1578 1579 spi1 { 1580 spi1_clk: spi1-clk { 1581 rockchip,pins = 1582 <3 RK_PB7 4 &pcfg_pull_up_4ma>; 1583 }; 1584 1585 spi1_csn0: spi1-csn0 { 1586 rockchip,pins = 1587 <3 RK_PB1 4 &pcfg_pull_up_4ma>; 1588 }; 1589 1590 spi1_csn1: spi1-csn1 { 1591 rockchip,pins = 1592 <3 RK_PB2 2 &pcfg_pull_up_4ma>; 1593 }; 1594 1595 spi1_miso: spi1-miso { 1596 rockchip,pins = 1597 <3 RK_PB6 4 &pcfg_pull_up_4ma>; 1598 }; 1599 1600 spi1_mosi: spi1-mosi { 1601 rockchip,pins = 1602 <3 RK_PB4 4 &pcfg_pull_up_4ma>; 1603 }; 1604 1605 spi1_clk_hs: spi1-clk-hs { 1606 rockchip,pins = 1607 <3 RK_PB7 4 &pcfg_pull_up_8ma>; 1608 }; 1609 1610 spi1_miso_hs: spi1-miso-hs { 1611 rockchip,pins = 1612 <3 RK_PB6 4 &pcfg_pull_up_8ma>; 1613 }; 1614 1615 spi1_mosi_hs: spi1-mosi-hs { 1616 rockchip,pins = 1617 <3 RK_PB4 4 &pcfg_pull_up_8ma>; 1618 }; 1619 }; 1620 1621 pdm { 1622 pdm_clk0m0: pdm-clk0m0 { 1623 rockchip,pins = 1624 <3 RK_PC6 2 &pcfg_pull_none>; 1625 }; 1626 1627 pdm_clk0m1: pdm-clk0m1 { 1628 rockchip,pins = 1629 <2 RK_PC6 1 &pcfg_pull_none>; 1630 }; 1631 1632 pdm_clk1: pdm-clk1 { 1633 rockchip,pins = 1634 <3 RK_PC7 2 &pcfg_pull_none>; 1635 }; 1636 1637 pdm_sdi0m0: pdm-sdi0m0 { 1638 rockchip,pins = 1639 <3 RK_PD3 2 &pcfg_pull_none>; 1640 }; 1641 1642 pdm_sdi0m1: pdm-sdi0m1 { 1643 rockchip,pins = 1644 <2 RK_PC5 2 &pcfg_pull_none>; 1645 }; 1646 1647 pdm_sdi1: pdm-sdi1 { 1648 rockchip,pins = 1649 <3 RK_PD0 2 &pcfg_pull_none>; 1650 }; 1651 1652 pdm_sdi2: pdm-sdi2 { 1653 rockchip,pins = 1654 <3 RK_PD1 2 &pcfg_pull_none>; 1655 }; 1656 1657 pdm_sdi3: pdm-sdi3 { 1658 rockchip,pins = 1659 <3 RK_PD2 2 &pcfg_pull_none>; 1660 }; 1661 1662 pdm_clk0m0_sleep: pdm-clk0m0-sleep { 1663 rockchip,pins = 1664 <3 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1665 }; 1666 1667 pdm_clk0m_sleep1: pdm-clk0m1-sleep { 1668 rockchip,pins = 1669 <2 RK_PC6 RK_FUNC_GPIO &pcfg_input_high>; 1670 }; 1671 1672 pdm_clk1_sleep: pdm-clk1-sleep { 1673 rockchip,pins = 1674 <3 RK_PC7 RK_FUNC_GPIO &pcfg_input_high>; 1675 }; 1676 1677 pdm_sdi0m0_sleep: pdm-sdi0m0-sleep { 1678 rockchip,pins = 1679 <3 RK_PD3 RK_FUNC_GPIO &pcfg_input_high>; 1680 }; 1681 1682 pdm_sdi0m1_sleep: pdm-sdi0m1-sleep { 1683 rockchip,pins = 1684 <2 RK_PC5 RK_FUNC_GPIO &pcfg_input_high>; 1685 }; 1686 1687 pdm_sdi1_sleep: pdm-sdi1-sleep { 1688 rockchip,pins = 1689 <3 RK_PD0 RK_FUNC_GPIO &pcfg_input_high>; 1690 }; 1691 1692 pdm_sdi2_sleep: pdm-sdi2-sleep { 1693 rockchip,pins = 1694 <3 RK_PD1 RK_FUNC_GPIO &pcfg_input_high>; 1695 }; 1696 1697 pdm_sdi3_sleep: pdm-sdi3-sleep { 1698 rockchip,pins = 1699 <3 RK_PD2 RK_FUNC_GPIO &pcfg_input_high>; 1700 }; 1701 }; 1702 1703 i2s0 { 1704 i2s0_8ch_mclk: i2s0-8ch-mclk { 1705 rockchip,pins = 1706 <3 RK_PC1 2 &pcfg_pull_none>; 1707 }; 1708 1709 i2s0_8ch_sclktx: i2s0-8ch-sclktx { 1710 rockchip,pins = 1711 <3 RK_PC3 2 &pcfg_pull_none>; 1712 }; 1713 1714 i2s0_8ch_sclkrx: i2s0-8ch-sclkrx { 1715 rockchip,pins = 1716 <3 RK_PB4 2 &pcfg_pull_none>; 1717 }; 1718 1719 i2s0_8ch_lrcktx: i2s0-8ch-lrcktx { 1720 rockchip,pins = 1721 <3 RK_PC2 2 &pcfg_pull_none>; 1722 }; 1723 1724 i2s0_8ch_lrckrx: i2s0-8ch-lrckrx { 1725 rockchip,pins = 1726 <3 RK_PB5 2 &pcfg_pull_none>; 1727 }; 1728 1729 i2s0_8ch_sdo0: i2s0-8ch-sdo0 { 1730 rockchip,pins = 1731 <3 RK_PC4 2 &pcfg_pull_none>; 1732 }; 1733 1734 i2s0_8ch_sdo1: i2s0-8ch-sdo1 { 1735 rockchip,pins = 1736 <3 RK_PC0 2 &pcfg_pull_none>; 1737 }; 1738 1739 i2s0_8ch_sdo2: i2s0-8ch-sdo2 { 1740 rockchip,pins = 1741 <3 RK_PB7 2 &pcfg_pull_none>; 1742 }; 1743 1744 i2s0_8ch_sdo3: i2s0-8ch-sdo3 { 1745 rockchip,pins = 1746 <3 RK_PB6 2 &pcfg_pull_none>; 1747 }; 1748 1749 i2s0_8ch_sdi0: i2s0-8ch-sdi0 { 1750 rockchip,pins = 1751 <3 RK_PC5 2 &pcfg_pull_none>; 1752 }; 1753 1754 i2s0_8ch_sdi1: i2s0-8ch-sdi1 { 1755 rockchip,pins = 1756 <3 RK_PB3 2 &pcfg_pull_none>; 1757 }; 1758 1759 i2s0_8ch_sdi2: i2s0-8ch-sdi2 { 1760 rockchip,pins = 1761 <3 RK_PB1 2 &pcfg_pull_none>; 1762 }; 1763 1764 i2s0_8ch_sdi3: i2s0-8ch-sdi3 { 1765 rockchip,pins = 1766 <3 RK_PB0 2 &pcfg_pull_none>; 1767 }; 1768 }; 1769 1770 i2s1 { 1771 i2s1_2ch_mclk: i2s1-2ch-mclk { 1772 rockchip,pins = 1773 <2 RK_PC3 1 &pcfg_pull_none>; 1774 }; 1775 1776 i2s1_2ch_sclk: i2s1-2ch-sclk { 1777 rockchip,pins = 1778 <2 RK_PC2 1 &pcfg_pull_none>; 1779 }; 1780 1781 i2s1_2ch_lrck: i2s1-2ch-lrck { 1782 rockchip,pins = 1783 <2 RK_PC1 1 &pcfg_pull_none>; 1784 }; 1785 1786 i2s1_2ch_sdi: i2s1-2ch-sdi { 1787 rockchip,pins = 1788 <2 RK_PC5 1 &pcfg_pull_none>; 1789 }; 1790 1791 i2s1_2ch_sdo: i2s1-2ch-sdo { 1792 rockchip,pins = 1793 <2 RK_PC4 1 &pcfg_pull_none>; 1794 }; 1795 }; 1796 1797 i2s2 { 1798 i2s2_2ch_mclk: i2s2-2ch-mclk { 1799 rockchip,pins = 1800 <3 RK_PA1 2 &pcfg_pull_none>; 1801 }; 1802 1803 i2s2_2ch_sclk: i2s2-2ch-sclk { 1804 rockchip,pins = 1805 <3 RK_PA2 2 &pcfg_pull_none>; 1806 }; 1807 1808 i2s2_2ch_lrck: i2s2-2ch-lrck { 1809 rockchip,pins = 1810 <3 RK_PA3 2 &pcfg_pull_none>; 1811 }; 1812 1813 i2s2_2ch_sdi: i2s2-2ch-sdi { 1814 rockchip,pins = 1815 <3 RK_PA5 2 &pcfg_pull_none>; 1816 }; 1817 1818 i2s2_2ch_sdo: i2s2-2ch-sdo { 1819 rockchip,pins = 1820 <3 RK_PA7 2 &pcfg_pull_none>; 1821 }; 1822 }; 1823 1824 sdmmc { 1825 sdmmc_clk: sdmmc-clk { 1826 rockchip,pins = 1827 <1 RK_PD6 1 &pcfg_pull_none_8ma>; 1828 }; 1829 1830 sdmmc_cmd: sdmmc-cmd { 1831 rockchip,pins = 1832 <1 RK_PD7 1 &pcfg_pull_up_8ma>; 1833 }; 1834 1835 sdmmc_det: sdmmc-det { 1836 rockchip,pins = 1837 <0 RK_PA3 1 &pcfg_pull_up_8ma>; 1838 }; 1839 1840 sdmmc_bus1: sdmmc-bus1 { 1841 rockchip,pins = 1842 <1 RK_PD2 1 &pcfg_pull_up_8ma>; 1843 }; 1844 1845 sdmmc_bus4: sdmmc-bus4 { 1846 rockchip,pins = 1847 <1 RK_PD2 1 &pcfg_pull_up_8ma>, 1848 <1 RK_PD3 1 &pcfg_pull_up_8ma>, 1849 <1 RK_PD4 1 &pcfg_pull_up_8ma>, 1850 <1 RK_PD5 1 &pcfg_pull_up_8ma>; 1851 }; 1852 }; 1853 1854 sdio { 1855 sdio_clk: sdio-clk { 1856 rockchip,pins = 1857 <1 RK_PC5 1 &pcfg_pull_none>; 1858 }; 1859 1860 sdio_cmd: sdio-cmd { 1861 rockchip,pins = 1862 <1 RK_PC4 1 &pcfg_pull_up>; 1863 }; 1864 1865 sdio_bus4: sdio-bus4 { 1866 rockchip,pins = 1867 <1 RK_PC6 1 &pcfg_pull_up>, 1868 <1 RK_PC7 1 &pcfg_pull_up>, 1869 <1 RK_PD0 1 &pcfg_pull_up>, 1870 <1 RK_PD1 1 &pcfg_pull_up>; 1871 }; 1872 }; 1873 1874 emmc { 1875 emmc_clk: emmc-clk { 1876 rockchip,pins = 1877 <1 RK_PB1 2 &pcfg_pull_none_8ma>; 1878 }; 1879 1880 emmc_cmd: emmc-cmd { 1881 rockchip,pins = 1882 <1 RK_PB2 2 &pcfg_pull_up_8ma>; 1883 }; 1884 1885 emmc_rstnout: emmc-rstnout { 1886 rockchip,pins = 1887 <1 RK_PB3 2 &pcfg_pull_none>; 1888 }; 1889 1890 emmc_bus1: emmc-bus1 { 1891 rockchip,pins = 1892 <1 RK_PA0 2 &pcfg_pull_up_8ma>; 1893 }; 1894 1895 emmc_bus4: emmc-bus4 { 1896 rockchip,pins = 1897 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1898 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1899 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1900 <1 RK_PA3 2 &pcfg_pull_up_8ma>; 1901 }; 1902 1903 emmc_bus8: emmc-bus8 { 1904 rockchip,pins = 1905 <1 RK_PA0 2 &pcfg_pull_up_8ma>, 1906 <1 RK_PA1 2 &pcfg_pull_up_8ma>, 1907 <1 RK_PA2 2 &pcfg_pull_up_8ma>, 1908 <1 RK_PA3 2 &pcfg_pull_up_8ma>, 1909 <1 RK_PA4 2 &pcfg_pull_up_8ma>, 1910 <1 RK_PA5 2 &pcfg_pull_up_8ma>, 1911 <1 RK_PA6 2 &pcfg_pull_up_8ma>, 1912 <1 RK_PA7 2 &pcfg_pull_up_8ma>; 1913 }; 1914 }; 1915 1916 flash { 1917 flash_cs0: flash-cs0 { 1918 rockchip,pins = 1919 <1 RK_PB0 1 &pcfg_pull_none>; 1920 }; 1921 1922 flash_rdy: flash-rdy { 1923 rockchip,pins = 1924 <1 RK_PB1 1 &pcfg_pull_none>; 1925 }; 1926 1927 flash_dqs: flash-dqs { 1928 rockchip,pins = 1929 <1 RK_PB2 1 &pcfg_pull_none>; 1930 }; 1931 1932 flash_ale: flash-ale { 1933 rockchip,pins = 1934 <1 RK_PB3 1 &pcfg_pull_none>; 1935 }; 1936 1937 flash_cle: flash-cle { 1938 rockchip,pins = 1939 <1 RK_PB4 1 &pcfg_pull_none>; 1940 }; 1941 1942 flash_wrn: flash-wrn { 1943 rockchip,pins = 1944 <1 RK_PB5 1 &pcfg_pull_none>; 1945 }; 1946 1947 flash_csl: flash-csl { 1948 rockchip,pins = 1949 <1 RK_PB6 1 &pcfg_pull_none>; 1950 }; 1951 1952 flash_rdn: flash-rdn { 1953 rockchip,pins = 1954 <1 RK_PB7 1 &pcfg_pull_none>; 1955 }; 1956 1957 flash_bus8: flash-bus8 { 1958 rockchip,pins = 1959 <1 RK_PA0 1 &pcfg_pull_up_12ma>, 1960 <1 RK_PA1 1 &pcfg_pull_up_12ma>, 1961 <1 RK_PA2 1 &pcfg_pull_up_12ma>, 1962 <1 RK_PA3 1 &pcfg_pull_up_12ma>, 1963 <1 RK_PA4 1 &pcfg_pull_up_12ma>, 1964 <1 RK_PA5 1 &pcfg_pull_up_12ma>, 1965 <1 RK_PA6 1 &pcfg_pull_up_12ma>, 1966 <1 RK_PA7 1 &pcfg_pull_up_12ma>; 1967 }; 1968 }; 1969 1970 lcdc { 1971 lcdc_rgb_dclk_pin: lcdc-rgb-dclk-pin { 1972 rockchip,pins = 1973 <3 RK_PA0 1 &pcfg_pull_none_12ma>; 1974 }; 1975 1976 lcdc_rgb_m0_hsync_pin: lcdc-rgb-m0-hsync-pin { 1977 rockchip,pins = 1978 <3 RK_PA1 1 &pcfg_pull_none_12ma>; 1979 }; 1980 1981 lcdc_rgb_m0_vsync_pin: lcdc-rgb-m0-vsync-pin { 1982 rockchip,pins = 1983 <3 RK_PA2 1 &pcfg_pull_none_12ma>; 1984 }; 1985 1986 lcdc_rgb_m0_den_pin: lcdc-rgb-m0-den-pin { 1987 rockchip,pins = 1988 <3 RK_PA3 1 &pcfg_pull_none_12ma>; 1989 }; 1990 1991 lcdc_rgb888_m0_data_pins: lcdc-rgb888-m0-data-pins { 1992 rockchip,pins = 1993 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 1994 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 1995 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 1996 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 1997 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 1998 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 1999 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2000 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2001 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2002 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2003 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2004 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2005 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2006 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2007 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2008 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2009 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2010 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2011 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2012 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2013 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2014 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2015 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2016 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2017 }; 2018 2019 lcdc_rgb666_m0_data_pins: lcdc-rgb666-m0-data-pins { 2020 rockchip,pins = 2021 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2022 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2023 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2024 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2025 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2026 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2027 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2028 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2029 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2030 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2031 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2032 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2033 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2034 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2035 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2036 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2037 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2038 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2039 }; 2040 2041 lcdc_rgb565_m0_data_pins: lcdc-rgb565-m0-data-pins { 2042 rockchip,pins = 2043 <3 RK_PA7 1 &pcfg_pull_none_8ma>, /* lcdc_d3 */ 2044 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2045 <3 RK_PA5 1 &pcfg_pull_none_8ma>, /* lcdc_d1 */ 2046 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2047 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2048 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2049 <3 RK_PB1 1 &pcfg_pull_none_8ma>, /* lcdc_d5 */ 2050 <3 RK_PB0 1 &pcfg_pull_none_8ma>, /* lcdc_d4 */ 2051 <3 RK_PB7 1 &pcfg_pull_none_8ma>, /* lcdc_d11 */ 2052 <3 RK_PB6 1 &pcfg_pull_none_8ma>, /* lcdc_d10 */ 2053 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2054 <3 RK_PB4 1 &pcfg_pull_none_8ma>, /* lcdc_d8 */ 2055 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2056 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2057 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2058 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2059 }; 2060 2061 lcdc_rgb888_m1_data_pins: lcdc-rgb888-m1-data-pins { 2062 rockchip,pins = 2063 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2064 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2065 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2066 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2067 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2068 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2069 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2070 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2071 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2072 <3 RK_PC7 1 &pcfg_pull_none_8ma>, /* lcdc_d19 */ 2073 <3 RK_PC6 1 &pcfg_pull_none_8ma>, /* lcdc_d18 */ 2074 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2075 <3 RK_PC4 1 &pcfg_pull_none_8ma>, /* lcdc_d16 */ 2076 <3 RK_PD3 1 &pcfg_pull_none_8ma>, /* lcdc_d23 */ 2077 <3 RK_PD2 1 &pcfg_pull_none_8ma>, /* lcdc_d22 */ 2078 <3 RK_PD1 1 &pcfg_pull_none_8ma>, /* lcdc_d21 */ 2079 <3 RK_PD0 1 &pcfg_pull_none_8ma>; /* lcdc_d20 */ 2080 }; 2081 2082 lcdc_rgb666_m1_data_pins: lcdc-rgb666-m1-data-pins { 2083 rockchip,pins = 2084 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2085 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2086 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2087 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2088 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2089 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2090 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2091 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2092 <3 RK_PC0 1 &pcfg_pull_none_8ma>, /* lcdc_d12 */ 2093 <3 RK_PC5 1 &pcfg_pull_none_8ma>, /* lcdc_d17 */ 2094 <3 RK_PC4 1 &pcfg_pull_none_8ma>; /* lcdc_d16 */ 2095 }; 2096 2097 lcdc_rgb565_m1_data_pins: lcdc-rgb565-m1-data-pins { 2098 rockchip,pins = 2099 <3 RK_PA6 1 &pcfg_pull_none_8ma>, /* lcdc_d2 */ 2100 <3 RK_PA4 1 &pcfg_pull_none_8ma>, /* lcdc_d0 */ 2101 <3 RK_PB3 1 &pcfg_pull_none_8ma>, /* lcdc_d7 */ 2102 <3 RK_PB2 1 &pcfg_pull_none_8ma>, /* lcdc_d6 */ 2103 <3 RK_PB5 1 &pcfg_pull_none_8ma>, /* lcdc_d9 */ 2104 <3 RK_PC3 1 &pcfg_pull_none_8ma>, /* lcdc_d15 */ 2105 <3 RK_PC2 1 &pcfg_pull_none_8ma>, /* lcdc_d14 */ 2106 <3 RK_PC1 1 &pcfg_pull_none_8ma>, /* lcdc_d13 */ 2107 <3 RK_PC0 1 &pcfg_pull_none_8ma>; /* lcdc_d12 */ 2108 }; 2109 }; 2110 2111 pwm0 { 2112 pwm0_pin: pwm0-pin { 2113 rockchip,pins = 2114 <0 RK_PB7 1 &pcfg_pull_none>; 2115 }; 2116 }; 2117 2118 pwm1 { 2119 pwm1_pin: pwm1-pin { 2120 rockchip,pins = 2121 <0 RK_PC0 1 &pcfg_pull_none>; 2122 }; 2123 }; 2124 2125 pwm2 { 2126 pwm2_pin: pwm2-pin { 2127 rockchip,pins = 2128 <2 RK_PB5 1 &pcfg_pull_none>; 2129 }; 2130 }; 2131 2132 pwm3 { 2133 pwm3_pin: pwm3-pin { 2134 rockchip,pins = 2135 <0 RK_PC1 1 &pcfg_pull_none>; 2136 }; 2137 }; 2138 2139 pwm4 { 2140 pwm4_pin: pwm4-pin { 2141 rockchip,pins = 2142 <3 RK_PC2 3 &pcfg_pull_none>; 2143 }; 2144 }; 2145 2146 pwm5 { 2147 pwm5_pin: pwm5-pin { 2148 rockchip,pins = 2149 <3 RK_PC3 3 &pcfg_pull_none>; 2150 }; 2151 }; 2152 2153 pwm6 { 2154 pwm6_pin: pwm6-pin { 2155 rockchip,pins = 2156 <3 RK_PC4 3 &pcfg_pull_none>; 2157 }; 2158 }; 2159 2160 pwm7 { 2161 pwm7_pin: pwm7-pin { 2162 rockchip,pins = 2163 <3 RK_PC5 3 &pcfg_pull_none>; 2164 }; 2165 }; 2166 2167 gmac { 2168 rmii_pins: rmii-pins { 2169 rockchip,pins = 2170 <2 RK_PA0 2 &pcfg_pull_none_12ma>, /* mac_txen */ 2171 <2 RK_PA1 2 &pcfg_pull_none_12ma>, /* mac_txd1 */ 2172 <2 RK_PA2 2 &pcfg_pull_none_12ma>, /* mac_txd0 */ 2173 <2 RK_PA3 2 &pcfg_pull_none>, /* mac_rxd0 */ 2174 <2 RK_PA4 2 &pcfg_pull_none>, /* mac_rxd1 */ 2175 <2 RK_PA5 2 &pcfg_pull_none>, /* mac_rxer */ 2176 <2 RK_PA6 2 &pcfg_pull_none>, /* mac_rxdv */ 2177 <2 RK_PA7 2 &pcfg_pull_none>, /* mac_mdio */ 2178 <2 RK_PB1 2 &pcfg_pull_none>; /* mac_mdc */ 2179 }; 2180 2181 mac_refclk_12ma: mac-refclk-12ma { 2182 rockchip,pins = 2183 <2 RK_PB2 2 &pcfg_pull_none_12ma>; 2184 }; 2185 2186 mac_refclk: mac-refclk { 2187 rockchip,pins = 2188 <2 RK_PB2 2 &pcfg_pull_none>; 2189 }; 2190 }; 2191 2192 cif-m0 { 2193 cif_clkout_m0: cif-clkout-m0 { 2194 rockchip,pins = 2195 <2 RK_PB3 1 &pcfg_pull_none>; 2196 }; 2197 2198 dvp_d2d9_m0: dvp-d2d9-m0 { 2199 rockchip,pins = 2200 <2 RK_PA0 1 &pcfg_pull_none>, /* cif_data2 */ 2201 <2 RK_PA1 1 &pcfg_pull_none>, /* cif_data3 */ 2202 <2 RK_PA2 1 &pcfg_pull_none>, /* cif_data4 */ 2203 <2 RK_PA3 1 &pcfg_pull_none>, /* cif_data5 */ 2204 <2 RK_PA4 1 &pcfg_pull_none>, /* cif_data6 */ 2205 <2 RK_PA5 1 &pcfg_pull_none>, /* cif_data7 */ 2206 <2 RK_PA6 1 &pcfg_pull_none>, /* cif_data8 */ 2207 <2 RK_PA7 1 &pcfg_pull_none>, /* cif_data9 */ 2208 <2 RK_PB0 1 &pcfg_pull_none>, /* cif_sync */ 2209 <2 RK_PB1 1 &pcfg_pull_none>, /* cif_href */ 2210 <2 RK_PB2 1 &pcfg_pull_none>, /* cif_clkin */ 2211 <2 RK_PB3 1 &pcfg_pull_none>; /* cif_clkout */ 2212 }; 2213 2214 dvp_d0d1_m0: dvp-d0d1-m0 { 2215 rockchip,pins = 2216 <2 RK_PB4 1 &pcfg_pull_none>, /* cif_data0 */ 2217 <2 RK_PB6 1 &pcfg_pull_none>; /* cif_data1 */ 2218 }; 2219 2220 dvp_d10d11_m0:d10-d11-m0 { 2221 rockchip,pins = 2222 <2 RK_PB7 1 &pcfg_pull_none>, /* cif_data10 */ 2223 <2 RK_PC0 1 &pcfg_pull_none>; /* cif_data11 */ 2224 }; 2225 }; 2226 2227 cif-m1 { 2228 cif_clkout_m1: cif-clkout-m1 { 2229 rockchip,pins = 2230 <3 RK_PD0 3 &pcfg_pull_none>; 2231 }; 2232 2233 dvp_d2d9_m1: dvp-d2d9-m1 { 2234 rockchip,pins = 2235 <3 RK_PA3 3 &pcfg_pull_none>, /* cif_data2 */ 2236 <3 RK_PA5 3 &pcfg_pull_none>, /* cif_data3 */ 2237 <3 RK_PA7 3 &pcfg_pull_none>, /* cif_data4 */ 2238 <3 RK_PB0 3 &pcfg_pull_none>, /* cif_data5 */ 2239 <3 RK_PB1 3 &pcfg_pull_none>, /* cif_data6 */ 2240 <3 RK_PB4 3 &pcfg_pull_none>, /* cif_data7 */ 2241 <3 RK_PB6 3 &pcfg_pull_none>, /* cif_data8 */ 2242 <3 RK_PB7 3 &pcfg_pull_none>, /* cif_data9 */ 2243 <3 RK_PD1 3 &pcfg_pull_none>, /* cif_sync */ 2244 <3 RK_PD2 3 &pcfg_pull_none>, /* cif_href */ 2245 <3 RK_PD3 3 &pcfg_pull_none>, /* cif_clkin */ 2246 <3 RK_PD0 3 &pcfg_pull_none>; /* cif_clkout */ 2247 }; 2248 2249 dvp_d0d1_m1: dvp-d0d1-m1 { 2250 rockchip,pins = 2251 <3 RK_PA1 3 &pcfg_pull_none>, /* cif_data0 */ 2252 <3 RK_PA2 3 &pcfg_pull_none>; /* cif_data1 */ 2253 }; 2254 2255 dvp_d10d11_m1:d10-d11-m1 { 2256 rockchip,pins = 2257 <3 RK_PC6 3 &pcfg_pull_none>, /* cif_data10 */ 2258 <3 RK_PC7 3 &pcfg_pull_none>; /* cif_data11 */ 2259 }; 2260 }; 2261 2262 isp { 2263 isp_prelight: isp-prelight { 2264 rockchip,pins = 2265 <3 RK_PD1 4 &pcfg_pull_none>; 2266 }; 2267 }; 2268 }; 2269}; 2270