1// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include "rk356x.dtsi"
7
8/ {
9	compatible = "rockchip,rk3568";
10
11	pipe_phy_grf0: syscon@fdc70000 {
12		compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
13		reg = <0x0 0xfdc70000 0x0 0x1000>;
14	};
15
16	qos_pcie3x1: qos@fe190080 {
17		compatible = "rockchip,rk3568-qos", "syscon";
18		reg = <0x0 0xfe190080 0x0 0x20>;
19	};
20
21	qos_pcie3x2: qos@fe190100 {
22		compatible = "rockchip,rk3568-qos", "syscon";
23		reg = <0x0 0xfe190100 0x0 0x20>;
24	};
25
26	qos_sata0: qos@fe190200 {
27		compatible = "rockchip,rk3568-qos", "syscon";
28		reg = <0x0 0xfe190200 0x0 0x20>;
29	};
30
31	gmac0: ethernet@fe2a0000 {
32		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
33		reg = <0x0 0xfe2a0000 0x0 0x10000>;
34		interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>,
35			     <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
36		interrupt-names = "macirq", "eth_wake_irq";
37		clocks = <&cru SCLK_GMAC0>, <&cru SCLK_GMAC0_RX_TX>,
38			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
39			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
40			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>;
41		clock-names = "stmmaceth", "mac_clk_rx",
42			      "mac_clk_tx", "clk_mac_refout",
43			      "aclk_mac", "pclk_mac",
44			      "clk_mac_speed", "ptp_ref";
45		resets = <&cru SRST_A_GMAC0>;
46		reset-names = "stmmaceth";
47		rockchip,grf = <&grf>;
48		snps,axi-config = <&gmac0_stmmac_axi_setup>;
49		snps,mixed-burst;
50		snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
51		snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
52		snps,tso;
53		status = "disabled";
54
55		mdio0: mdio {
56			compatible = "snps,dwmac-mdio";
57			#address-cells = <0x1>;
58			#size-cells = <0x0>;
59		};
60
61		gmac0_stmmac_axi_setup: stmmac-axi-config {
62			snps,blen = <0 0 0 0 16 8 4>;
63			snps,rd_osr_lmt = <8>;
64			snps,wr_osr_lmt = <4>;
65		};
66
67		gmac0_mtl_rx_setup: rx-queues-config {
68			snps,rx-queues-to-use = <1>;
69			queue0 {};
70		};
71
72		gmac0_mtl_tx_setup: tx-queues-config {
73			snps,tx-queues-to-use = <1>;
74			queue0 {};
75		};
76	};
77
78	combphy0: phy@fe820000 {
79		compatible = "rockchip,rk3568-naneng-combphy";
80		reg = <0x0 0xfe820000 0x0 0x100>;
81		clocks = <&pmucru CLK_PCIEPHY0_REF>,
82			 <&cru PCLK_PIPEPHY0>,
83			 <&cru PCLK_PIPE>;
84		clock-names = "ref", "apb", "pipe";
85		assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
86		assigned-clock-rates = <100000000>;
87		resets = <&cru SRST_PIPEPHY0>;
88		rockchip,pipe-grf = <&pipegrf>;
89		rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
90		#phy-cells = <1>;
91		status = "disabled";
92	};
93};
94
95&cpu0_opp_table {
96	opp-1992000000 {
97		opp-hz = /bits/ 64 <1992000000>;
98		opp-microvolt = <1150000 1150000 1150000>;
99	};
100};
101
102&power {
103	power-domain@RK3568_PD_PIPE {
104		reg = <RK3568_PD_PIPE>;
105		clocks = <&cru PCLK_PIPE>;
106		pm_qos = <&qos_pcie2x1>,
107			 <&qos_pcie3x1>,
108			 <&qos_pcie3x2>,
109			 <&qos_sata0>,
110			 <&qos_sata1>,
111			 <&qos_sata2>,
112			 <&qos_usb3_0>,
113			 <&qos_usb3_1>;
114		#power-domain-cells = <0>;
115	};
116};
117