1c9ccf3a3SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0 2c9ccf3a3SEmmanuel Vadot/* 3c9ccf3a3SEmmanuel Vadot * Device Tree Source for AM62 SoC Family 4c9ccf3a3SEmmanuel Vadot * 5c9ccf3a3SEmmanuel Vadot * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/ 6c9ccf3a3SEmmanuel Vadot */ 7c9ccf3a3SEmmanuel Vadot 8c9ccf3a3SEmmanuel Vadot#include <dt-bindings/gpio/gpio.h> 9c9ccf3a3SEmmanuel Vadot#include <dt-bindings/interrupt-controller/irq.h> 10c9ccf3a3SEmmanuel Vadot#include <dt-bindings/interrupt-controller/arm-gic.h> 11c9ccf3a3SEmmanuel Vadot#include <dt-bindings/soc/ti,sci_pm_domain.h> 12c9ccf3a3SEmmanuel Vadot 13fac71e4eSEmmanuel Vadot#include "k3-pinctrl.h" 14fac71e4eSEmmanuel Vadot 15c9ccf3a3SEmmanuel Vadot/ { 16c9ccf3a3SEmmanuel Vadot model = "Texas Instruments K3 AM625 SoC"; 17c9ccf3a3SEmmanuel Vadot compatible = "ti,am625"; 18c9ccf3a3SEmmanuel Vadot interrupt-parent = <&gic500>; 19c9ccf3a3SEmmanuel Vadot #address-cells = <2>; 20c9ccf3a3SEmmanuel Vadot #size-cells = <2>; 21c9ccf3a3SEmmanuel Vadot 22c9ccf3a3SEmmanuel Vadot chosen { }; 23c9ccf3a3SEmmanuel Vadot 24c9ccf3a3SEmmanuel Vadot firmware { 25c9ccf3a3SEmmanuel Vadot optee { 26c9ccf3a3SEmmanuel Vadot compatible = "linaro,optee-tz"; 27c9ccf3a3SEmmanuel Vadot method = "smc"; 28c9ccf3a3SEmmanuel Vadot }; 29c9ccf3a3SEmmanuel Vadot 30c9ccf3a3SEmmanuel Vadot psci: psci { 31c9ccf3a3SEmmanuel Vadot compatible = "arm,psci-1.0"; 32c9ccf3a3SEmmanuel Vadot method = "smc"; 33c9ccf3a3SEmmanuel Vadot }; 34c9ccf3a3SEmmanuel Vadot }; 35c9ccf3a3SEmmanuel Vadot 36c9ccf3a3SEmmanuel Vadot a53_timer0: timer-cl0-cpu0 { 37c9ccf3a3SEmmanuel Vadot compatible = "arm,armv8-timer"; 38c9ccf3a3SEmmanuel Vadot interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* cntpsirq */ 39c9ccf3a3SEmmanuel Vadot <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* cntpnsirq */ 40c9ccf3a3SEmmanuel Vadot <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* cntvirq */ 41c9ccf3a3SEmmanuel Vadot <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* cnthpirq */ 42c9ccf3a3SEmmanuel Vadot }; 43c9ccf3a3SEmmanuel Vadot 44c9ccf3a3SEmmanuel Vadot pmu: pmu { 45c9ccf3a3SEmmanuel Vadot compatible = "arm,cortex-a53-pmu"; 46c9ccf3a3SEmmanuel Vadot interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 47c9ccf3a3SEmmanuel Vadot }; 48c9ccf3a3SEmmanuel Vadot 49c9ccf3a3SEmmanuel Vadot cbass_main: bus@f0000 { 50*84943d6fSEmmanuel Vadot bootph-all; 51c9ccf3a3SEmmanuel Vadot compatible = "simple-bus"; 52c9ccf3a3SEmmanuel Vadot #address-cells = <2>; 53c9ccf3a3SEmmanuel Vadot #size-cells = <2>; 54c9ccf3a3SEmmanuel Vadot 55c9ccf3a3SEmmanuel Vadot ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */ 56c9ccf3a3SEmmanuel Vadot <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */ 57c9ccf3a3SEmmanuel Vadot <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */ 58c9ccf3a3SEmmanuel Vadot <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */ 59c9ccf3a3SEmmanuel Vadot <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */ 60c9ccf3a3SEmmanuel Vadot <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */ 61c9ccf3a3SEmmanuel Vadot <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */ 62c9ccf3a3SEmmanuel Vadot <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */ 63c9ccf3a3SEmmanuel Vadot <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */ 64c9ccf3a3SEmmanuel Vadot <0x00 0x0fd00000 0x00 0x0fd00000 0x00 0x00020000>, /* GPU */ 65c9ccf3a3SEmmanuel Vadot <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */ 66c9ccf3a3SEmmanuel Vadot <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */ 67c9ccf3a3SEmmanuel Vadot <0x00 0x30101000 0x00 0x30101000 0x00 0x00010100>, /* CSI window */ 68c9ccf3a3SEmmanuel Vadot <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */ 69c9ccf3a3SEmmanuel Vadot <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */ 70c9ccf3a3SEmmanuel Vadot <0x00 0x31100000 0x00 0x31100000 0x00 0x00050000>, /* USB1 DWC3 Core window */ 71d5b0e70fSEmmanuel Vadot <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */ 72c9ccf3a3SEmmanuel Vadot <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */ 73c9ccf3a3SEmmanuel Vadot <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */ 74c9ccf3a3SEmmanuel Vadot <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */ 75c9ccf3a3SEmmanuel Vadot <0x00 0x48000000 0x00 0x48000000 0x00 0x06400000>, /* DMSS */ 76c9ccf3a3SEmmanuel Vadot <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */ 77c9ccf3a3SEmmanuel Vadot <0x00 0x70000000 0x00 0x70000000 0x00 0x00010000>, /* OCSRAM */ 78c9ccf3a3SEmmanuel Vadot <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */ 79c9ccf3a3SEmmanuel Vadot <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */ 80c9ccf3a3SEmmanuel Vadot 81c9ccf3a3SEmmanuel Vadot /* MCU Domain Range */ 82c9ccf3a3SEmmanuel Vadot <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>, 83c9ccf3a3SEmmanuel Vadot 84c9ccf3a3SEmmanuel Vadot /* Wakeup Domain Range */ 85f126890aSEmmanuel Vadot <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 86c9ccf3a3SEmmanuel Vadot <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, 87c9ccf3a3SEmmanuel Vadot <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; 88c9ccf3a3SEmmanuel Vadot 89c9ccf3a3SEmmanuel Vadot cbass_mcu: bus@4000000 { 90*84943d6fSEmmanuel Vadot bootph-all; 91c9ccf3a3SEmmanuel Vadot compatible = "simple-bus"; 92c9ccf3a3SEmmanuel Vadot #address-cells = <2>; 93c9ccf3a3SEmmanuel Vadot #size-cells = <2>; 94c9ccf3a3SEmmanuel Vadot ranges = <0x00 0x04000000 0x00 0x04000000 0x00 0x01ff1400>; /* Peripheral window */ 95c9ccf3a3SEmmanuel Vadot }; 96c9ccf3a3SEmmanuel Vadot 97f126890aSEmmanuel Vadot cbass_wakeup: bus@b00000 { 98*84943d6fSEmmanuel Vadot bootph-all; 99c9ccf3a3SEmmanuel Vadot compatible = "simple-bus"; 100c9ccf3a3SEmmanuel Vadot #address-cells = <2>; 101c9ccf3a3SEmmanuel Vadot #size-cells = <2>; 102f126890aSEmmanuel Vadot ranges = <0x00 0x00b00000 0x00 0x00b00000 0x00 0x00002400>, /* VTM */ 103f126890aSEmmanuel Vadot <0x00 0x2b000000 0x00 0x2b000000 0x00 0x00300400>, /* Peripheral Window */ 104c9ccf3a3SEmmanuel Vadot <0x00 0x43000000 0x00 0x43000000 0x00 0x00020000>; 105c9ccf3a3SEmmanuel Vadot }; 106c9ccf3a3SEmmanuel Vadot }; 107f126890aSEmmanuel Vadot 108aa1a8ff2SEmmanuel Vadot dss_vp1_clk: clock-divider-oldi { 109aa1a8ff2SEmmanuel Vadot compatible = "fixed-factor-clock"; 110aa1a8ff2SEmmanuel Vadot clocks = <&k3_clks 186 0>; 111aa1a8ff2SEmmanuel Vadot #clock-cells = <0>; 112aa1a8ff2SEmmanuel Vadot clock-div = <7>; 113aa1a8ff2SEmmanuel Vadot clock-mult = <1>; 114aa1a8ff2SEmmanuel Vadot }; 115aa1a8ff2SEmmanuel Vadot 116f126890aSEmmanuel Vadot #include "k3-am62-thermal.dtsi" 117c9ccf3a3SEmmanuel Vadot}; 118c9ccf3a3SEmmanuel Vadot 119c9ccf3a3SEmmanuel Vadot/* Now include the peripherals for each bus segments */ 120c9ccf3a3SEmmanuel Vadot#include "k3-am62-main.dtsi" 121c9ccf3a3SEmmanuel Vadot#include "k3-am62-mcu.dtsi" 122c9ccf3a3SEmmanuel Vadot#include "k3-am62-wakeup.dtsi" 123