1// SPDX-License-Identifier: GPL-2.0 2/* 3 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/ 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/mux/ti-serdes.h> 9#include <dt-bindings/phy/phy.h> 10#include <dt-bindings/gpio/gpio.h> 11#include <dt-bindings/net/ti-dp83867.h> 12#include <dt-bindings/leds/common.h> 13#include "k3-am642.dtsi" 14 15/ { 16 compatible = "ti,am642-sk", "ti,am642"; 17 model = "Texas Instruments AM642 SK"; 18 19 chosen { 20 stdout-path = "serial2:115200n8"; 21 bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; 22 }; 23 24 memory@80000000 { 25 device_type = "memory"; 26 /* 2G RAM */ 27 reg = <0x00000000 0x80000000 0x00000000 0x80000000>; 28 29 }; 30 31 reserved-memory { 32 #address-cells = <2>; 33 #size-cells = <2>; 34 ranges; 35 36 secure_ddr: optee@9e800000 { 37 reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */ 38 alignment = <0x1000>; 39 no-map; 40 }; 41 42 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 43 compatible = "shared-dma-pool"; 44 reg = <0x00 0xa0000000 0x00 0x100000>; 45 no-map; 46 }; 47 48 main_r5fss0_core0_memory_region: r5f-memory@a0100000 { 49 compatible = "shared-dma-pool"; 50 reg = <0x00 0xa0100000 0x00 0xf00000>; 51 no-map; 52 }; 53 54 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 55 compatible = "shared-dma-pool"; 56 reg = <0x00 0xa1000000 0x00 0x100000>; 57 no-map; 58 }; 59 60 main_r5fss0_core1_memory_region: r5f-memory@a1100000 { 61 compatible = "shared-dma-pool"; 62 reg = <0x00 0xa1100000 0x00 0xf00000>; 63 no-map; 64 }; 65 66 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a2000000 { 67 compatible = "shared-dma-pool"; 68 reg = <0x00 0xa2000000 0x00 0x100000>; 69 no-map; 70 }; 71 72 main_r5fss1_core0_memory_region: r5f-memory@a2100000 { 73 compatible = "shared-dma-pool"; 74 reg = <0x00 0xa2100000 0x00 0xf00000>; 75 no-map; 76 }; 77 78 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a3000000 { 79 compatible = "shared-dma-pool"; 80 reg = <0x00 0xa3000000 0x00 0x100000>; 81 no-map; 82 }; 83 84 main_r5fss1_core1_memory_region: r5f-memory@a3100000 { 85 compatible = "shared-dma-pool"; 86 reg = <0x00 0xa3100000 0x00 0xf00000>; 87 no-map; 88 }; 89 90 rtos_ipc_memory_region: ipc-memories@a5000000 { 91 reg = <0x00 0xa5000000 0x00 0x00800000>; 92 alignment = <0x1000>; 93 no-map; 94 }; 95 }; 96 97 vusb_main: fixed-regulator-vusb-main5v0 { 98 /* USB MAIN INPUT 5V DC */ 99 compatible = "regulator-fixed"; 100 regulator-name = "vusb_main5v0"; 101 regulator-min-microvolt = <5000000>; 102 regulator-max-microvolt = <5000000>; 103 regulator-always-on; 104 regulator-boot-on; 105 }; 106 107 vcc_3v3_sys: fixedregulator-vcc-3v3-sys { 108 /* output of LP8733xx */ 109 compatible = "regulator-fixed"; 110 regulator-name = "vcc_3v3_sys"; 111 regulator-min-microvolt = <3300000>; 112 regulator-max-microvolt = <3300000>; 113 vin-supply = <&vusb_main>; 114 regulator-always-on; 115 regulator-boot-on; 116 }; 117 118 vdd_mmc1: fixed-regulator-sd { 119 /* TPS2051BD */ 120 compatible = "regulator-fixed"; 121 regulator-name = "vdd_mmc1"; 122 regulator-min-microvolt = <3300000>; 123 regulator-max-microvolt = <3300000>; 124 regulator-boot-on; 125 enable-active-high; 126 vin-supply = <&vcc_3v3_sys>; 127 gpio = <&exp1 3 GPIO_ACTIVE_HIGH>; 128 }; 129 130 com8_ls_en: regulator-1 { 131 compatible = "regulator-fixed"; 132 regulator-name = "com8_ls_en"; 133 regulator-min-microvolt = <3300000>; 134 regulator-max-microvolt = <3300000>; 135 regulator-always-on; 136 regulator-boot-on; 137 pinctrl-0 = <&main_com8_ls_en_pins_default>; 138 pinctrl-names = "default"; 139 gpio = <&main_gpio0 62 GPIO_ACTIVE_LOW>; 140 }; 141 142 wlan_en: regulator-2 { 143 /* output of SN74AVC4T245RSVR */ 144 compatible = "regulator-fixed"; 145 regulator-name = "wlan_en"; 146 regulator-min-microvolt = <1800000>; 147 regulator-max-microvolt = <1800000>; 148 enable-active-high; 149 pinctrl-0 = <&main_wlan_en_pins_default>; 150 pinctrl-names = "default"; 151 vin-supply = <&com8_ls_en>; 152 gpio = <&main_gpio0 48 GPIO_ACTIVE_HIGH>; 153 }; 154 155 led-controller { 156 compatible = "gpio-leds"; 157 158 led-0 { 159 color = <LED_COLOR_ID_GREEN>; 160 function = LED_FUNCTION_INDICATOR; 161 function-enumerator = <1>; 162 gpios = <&exp2 0 GPIO_ACTIVE_HIGH>; 163 default-state = "off"; 164 }; 165 166 led-1 { 167 color = <LED_COLOR_ID_RED>; 168 function = LED_FUNCTION_INDICATOR; 169 function-enumerator = <2>; 170 gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; 171 default-state = "off"; 172 }; 173 174 led-2 { 175 color = <LED_COLOR_ID_GREEN>; 176 function = LED_FUNCTION_INDICATOR; 177 function-enumerator = <3>; 178 gpios = <&exp2 2 GPIO_ACTIVE_HIGH>; 179 default-state = "off"; 180 }; 181 182 led-3 { 183 color = <LED_COLOR_ID_AMBER>; 184 function = LED_FUNCTION_INDICATOR; 185 function-enumerator = <4>; 186 gpios = <&exp2 3 GPIO_ACTIVE_HIGH>; 187 default-state = "off"; 188 }; 189 190 led-4 { 191 color = <LED_COLOR_ID_GREEN>; 192 function = LED_FUNCTION_INDICATOR; 193 function-enumerator = <5>; 194 gpios = <&exp2 4 GPIO_ACTIVE_HIGH>; 195 default-state = "off"; 196 }; 197 198 led-5 { 199 color = <LED_COLOR_ID_RED>; 200 function = LED_FUNCTION_INDICATOR; 201 function-enumerator = <6>; 202 gpios = <&exp2 5 GPIO_ACTIVE_HIGH>; 203 default-state = "off"; 204 }; 205 206 led-6 { 207 color = <LED_COLOR_ID_GREEN>; 208 function = LED_FUNCTION_INDICATOR; 209 function-enumerator = <7>; 210 gpios = <&exp2 6 GPIO_ACTIVE_HIGH>; 211 default-state = "off"; 212 }; 213 214 led-7 { 215 color = <LED_COLOR_ID_AMBER>; 216 function = LED_FUNCTION_HEARTBEAT; 217 function-enumerator = <8>; 218 linux,default-trigger = "heartbeat"; 219 gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 220 }; 221 }; 222}; 223 224&main_pmx0 { 225 main_mmc1_pins_default: main-mmc1-pins-default { 226 pinctrl-single,pins = < 227 AM64X_IOPAD(0x0294, PIN_INPUT, 0) /* (J19) MMC1_CMD */ 228 AM64X_IOPAD(0x0290, PIN_INPUT, 0) /* (#N/A) MMC1_CLKLB */ 229 AM64X_IOPAD(0x028c, PIN_INPUT, 0) /* (L20) MMC1_CLK */ 230 AM64X_IOPAD(0x0288, PIN_INPUT, 0) /* (K21) MMC1_DAT0 */ 231 AM64X_IOPAD(0x0284, PIN_INPUT, 0) /* (L21) MMC1_DAT1 */ 232 AM64X_IOPAD(0x0280, PIN_INPUT, 0) /* (K19) MMC1_DAT2 */ 233 AM64X_IOPAD(0x027c, PIN_INPUT, 0) /* (K18) MMC1_DAT3 */ 234 AM64X_IOPAD(0x0298, PIN_INPUT, 0) /* (D19) MMC1_SDCD */ 235 >; 236 }; 237 238 main_uart0_pins_default: main-uart0-pins-default { 239 pinctrl-single,pins = < 240 AM64X_IOPAD(0x0238, PIN_INPUT, 0) /* (B16) UART0_CTSn */ 241 AM64X_IOPAD(0x023c, PIN_OUTPUT, 0) /* (A16) UART0_RTSn */ 242 AM64X_IOPAD(0x0230, PIN_INPUT, 0) /* (D15) UART0_RXD */ 243 AM64X_IOPAD(0x0234, PIN_OUTPUT, 0) /* (C16) UART0_TXD */ 244 >; 245 }; 246 247 main_usb0_pins_default: main-usb0-pins-default { 248 pinctrl-single,pins = < 249 AM64X_IOPAD(0x02a8, PIN_OUTPUT, 0) /* (E19) USB0_DRVVBUS */ 250 >; 251 }; 252 253 main_i2c1_pins_default: main-i2c1-pins-default { 254 pinctrl-single,pins = < 255 AM64X_IOPAD(0x0268, PIN_INPUT_PULLUP, 0) /* (C18) I2C1_SCL */ 256 AM64X_IOPAD(0x026c, PIN_INPUT_PULLUP, 0) /* (B19) I2C1_SDA */ 257 >; 258 }; 259 260 mdio1_pins_default: mdio1-pins-default { 261 pinctrl-single,pins = < 262 AM64X_IOPAD(0x01fc, PIN_OUTPUT, 4) /* (R2) PRG0_PRU1_GPO19.MDIO0_MDC */ 263 AM64X_IOPAD(0x01f8, PIN_INPUT, 4) /* (P5) PRG0_PRU1_GPO18.MDIO0_MDIO */ 264 >; 265 }; 266 267 rgmii1_pins_default: rgmii1-pins-default { 268 pinctrl-single,pins = < 269 AM64X_IOPAD(0x011c, PIN_INPUT, 4) /* (AA13) PRG1_PRU1_GPO5.RGMII1_RD0 */ 270 AM64X_IOPAD(0x0128, PIN_INPUT, 4) /* (U12) PRG1_PRU1_GPO8.RGMII1_RD1 */ 271 AM64X_IOPAD(0x0150, PIN_INPUT, 4) /* (Y13) PRG1_PRU1_GPO18.RGMII1_RD2 */ 272 AM64X_IOPAD(0x0154, PIN_INPUT, 4) /* (V12) PRG1_PRU1_GPO19.RGMII1_RD3 */ 273 AM64X_IOPAD(0x00d8, PIN_INPUT, 4) /* (W13) PRG1_PRU0_GPO8.RGMII1_RXC */ 274 AM64X_IOPAD(0x00cc, PIN_INPUT, 4) /* (V13) PRG1_PRU0_GPO5.RGMII1_RX_CTL */ 275 AM64X_IOPAD(0x0124, PIN_OUTPUT, 4) /* (V15) PRG1_PRU1_GPO7.RGMII1_TD0 */ 276 AM64X_IOPAD(0x012c, PIN_OUTPUT, 4) /* (V14) PRG1_PRU1_GPO9.RGMII1_TD1 */ 277 AM64X_IOPAD(0x0130, PIN_OUTPUT, 4) /* (W14) PRG1_PRU1_GPO10.RGMII1_TD2 */ 278 AM64X_IOPAD(0x014c, PIN_OUTPUT, 4) /* (AA14) PRG1_PRU1_GPO17.RGMII1_TD3 */ 279 AM64X_IOPAD(0x00e0, PIN_OUTPUT, 4) /* (U14) PRG1_PRU0_GPO10.RGMII1_TXC */ 280 AM64X_IOPAD(0x00dc, PIN_OUTPUT, 4) /* (U15) PRG1_PRU0_GPO9.RGMII1_TX_CTL */ 281 >; 282 }; 283 284 rgmii2_pins_default: rgmii2-pins-default { 285 pinctrl-single,pins = < 286 AM64X_IOPAD(0x0108, PIN_INPUT, 4) /* (W11) PRG1_PRU1_GPO0.RGMII2_RD0 */ 287 AM64X_IOPAD(0x010c, PIN_INPUT, 4) /* (V11) PRG1_PRU1_GPO1.RGMII2_RD1 */ 288 AM64X_IOPAD(0x0110, PIN_INPUT, 4) /* (AA12) PRG1_PRU1_GPO2.RGMII2_RD2 */ 289 AM64X_IOPAD(0x0114, PIN_INPUT, 4) /* (Y12) PRG1_PRU1_GPO3.RGMII2_RD3 */ 290 AM64X_IOPAD(0x0120, PIN_INPUT, 4) /* (U11) PRG1_PRU1_GPO6.RGMII2_RXC */ 291 AM64X_IOPAD(0x0118, PIN_INPUT, 4) /* (W12) PRG1_PRU1_GPO4.RGMII2_RX_CTL */ 292 AM64X_IOPAD(0x0134, PIN_OUTPUT, 4) /* (AA10) PRG1_PRU1_GPO11.RGMII2_TD0 */ 293 AM64X_IOPAD(0x0138, PIN_OUTPUT, 4) /* (V10) PRG1_PRU1_GPO12.RGMII2_TD1 */ 294 AM64X_IOPAD(0x013c, PIN_OUTPUT, 4) /* (U10) PRG1_PRU1_GPO13.RGMII2_TD2 */ 295 AM64X_IOPAD(0x0140, PIN_OUTPUT, 4) /* (AA11) PRG1_PRU1_GPO14.RGMII2_TD3 */ 296 AM64X_IOPAD(0x0148, PIN_OUTPUT, 4) /* (Y10) PRG1_PRU1_GPO16.RGMII2_TXC */ 297 AM64X_IOPAD(0x0144, PIN_OUTPUT, 4) /* (Y11) PRG1_PRU1_GPO15.RGMII2_TX_CTL */ 298 >; 299 }; 300 301 ospi0_pins_default: ospi0-pins-default { 302 pinctrl-single,pins = < 303 AM64X_IOPAD(0x0000, PIN_OUTPUT, 0) /* (N20) OSPI0_CLK */ 304 AM64X_IOPAD(0x002c, PIN_OUTPUT, 0) /* (L19) OSPI0_CSn0 */ 305 AM64X_IOPAD(0x000c, PIN_INPUT, 0) /* (M19) OSPI0_D0 */ 306 AM64X_IOPAD(0x0010, PIN_INPUT, 0) /* (M18) OSPI0_D1 */ 307 AM64X_IOPAD(0x0014, PIN_INPUT, 0) /* (M20) OSPI0_D2 */ 308 AM64X_IOPAD(0x0018, PIN_INPUT, 0) /* (M21) OSPI0_D3 */ 309 AM64X_IOPAD(0x001c, PIN_INPUT, 0) /* (P21) OSPI0_D4 */ 310 AM64X_IOPAD(0x0020, PIN_INPUT, 0) /* (P20) OSPI0_D5 */ 311 AM64X_IOPAD(0x0024, PIN_INPUT, 0) /* (N18) OSPI0_D6 */ 312 AM64X_IOPAD(0x0028, PIN_INPUT, 0) /* (M17) OSPI0_D7 */ 313 AM64X_IOPAD(0x0008, PIN_INPUT, 0) /* (N19) OSPI0_DQS */ 314 >; 315 }; 316 317 main_ecap0_pins_default: main-ecap0-pins-default { 318 pinctrl-single,pins = < 319 AM64X_IOPAD(0x0270, PIN_INPUT, 0) /* (D18) ECAP0_IN_APWM_OUT */ 320 >; 321 }; 322 main_wlan_en_pins_default: main-wlan-en-pins-default { 323 pinctrl-single,pins = < 324 AM64X_IOPAD(0x00c4, PIN_OUTPUT_PULLUP, 7) /* (V8) GPIO0_48 */ 325 >; 326 }; 327 328 main_com8_ls_en_pins_default: main-com8-ls-en-pins-default { 329 pinctrl-single,pins = < 330 AM64X_IOPAD(0x00fc, PIN_OUTPUT, 7) /* (U7) PRG1_PRU0_GPO17.GPIO0_62 */ 331 >; 332 }; 333 334 main_wlan_pins_default: main-wlan-pins-default { 335 pinctrl-single,pins = < 336 AM64X_IOPAD(0x00bc, PIN_INPUT, 7) /* (U8) GPIO0_46 */ 337 >; 338 }; 339}; 340 341&main_uart0 { 342 status = "okay"; 343 pinctrl-names = "default"; 344 pinctrl-0 = <&main_uart0_pins_default>; 345}; 346 347&main_uart1 { 348 /* main_uart1 is reserved for firmware usage */ 349 status = "reserved"; 350}; 351 352&main_i2c1 { 353 status = "okay"; 354 pinctrl-names = "default"; 355 pinctrl-0 = <&main_i2c1_pins_default>; 356 clock-frequency = <400000>; 357 358 exp1: gpio@70 { 359 compatible = "nxp,pca9538"; 360 reg = <0x70>; 361 gpio-controller; 362 #gpio-cells = <2>; 363 gpio-line-names = "GPIO_CPSW2_RST", "GPIO_CPSW1_RST", 364 "PRU_DETECT", "MMC1_SD_EN", 365 "VPP_LDO_EN", "RPI_PS_3V3_En", 366 "RPI_PS_5V0_En", "RPI_HAT_DETECT"; 367 }; 368 369 exp2: gpio@60 { 370 compatible = "ti,tpic2810"; 371 reg = <0x60>; 372 gpio-controller; 373 #gpio-cells = <2>; 374 gpio-line-names = "LED1","LED2","LED3","LED4","LED5","LED6","LED7","LED8"; 375 }; 376}; 377 378/* mcu_gpio0 is reserved for mcu firmware usage */ 379&mcu_gpio0 { 380 status = "reserved"; 381}; 382 383&sdhci0 { 384 vmmc-supply = <&wlan_en>; 385 bus-width = <4>; 386 non-removable; 387 cap-power-off-card; 388 keep-power-in-suspend; 389 ti,driver-strength-ohm = <50>; 390 391 #address-cells = <1>; 392 #size-cells = <0>; 393 wlcore: wlcore@2 { 394 compatible = "ti,wl1837"; 395 reg = <2>; 396 pinctrl-0 = <&main_wlan_pins_default>; 397 pinctrl-names = "default"; 398 interrupt-parent = <&main_gpio0>; 399 interrupts = <46 IRQ_TYPE_EDGE_FALLING>; 400 }; 401}; 402 403&sdhci1 { 404 /* SD/MMC */ 405 vmmc-supply = <&vdd_mmc1>; 406 pinctrl-names = "default"; 407 bus-width = <4>; 408 pinctrl-0 = <&main_mmc1_pins_default>; 409 ti,driver-strength-ohm = <50>; 410 disable-wp; 411}; 412 413&serdes_ln_ctrl { 414 idle-states = <AM64_SERDES0_LANE0_USB>; 415}; 416 417&serdes0 { 418 serdes0_usb_link: phy@0 { 419 reg = <0>; 420 cdns,num-lanes = <1>; 421 #phy-cells = <0>; 422 cdns,phy-type = <PHY_TYPE_USB3>; 423 resets = <&serdes_wiz0 1>; 424 }; 425}; 426 427&usbss0 { 428 ti,vbus-divider; 429}; 430 431&usb0 { 432 dr_mode = "host"; 433 maximum-speed = "super-speed"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&main_usb0_pins_default>; 436 phys = <&serdes0_usb_link>; 437 phy-names = "cdns3,usb3-phy"; 438}; 439 440&cpsw3g { 441 pinctrl-names = "default"; 442 pinctrl-0 = <&rgmii1_pins_default 443 &rgmii2_pins_default>; 444}; 445 446&cpsw_port1 { 447 phy-mode = "rgmii-rxid"; 448 phy-handle = <&cpsw3g_phy0>; 449}; 450 451&cpsw_port2 { 452 phy-mode = "rgmii-rxid"; 453 phy-handle = <&cpsw3g_phy1>; 454}; 455 456&cpsw3g_mdio { 457 status = "okay"; 458 pinctrl-names = "default"; 459 pinctrl-0 = <&mdio1_pins_default>; 460 461 cpsw3g_phy0: ethernet-phy@0 { 462 reg = <0>; 463 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 464 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 465 }; 466 467 cpsw3g_phy1: ethernet-phy@1 { 468 reg = <1>; 469 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 470 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 471 }; 472}; 473 474&tscadc0 { 475 status = "disabled"; 476}; 477 478&ospi0 { 479 pinctrl-names = "default"; 480 pinctrl-0 = <&ospi0_pins_default>; 481 482 flash@0 { 483 compatible = "jedec,spi-nor"; 484 reg = <0x0>; 485 spi-tx-bus-width = <8>; 486 spi-rx-bus-width = <8>; 487 spi-max-frequency = <25000000>; 488 cdns,tshsl-ns = <60>; 489 cdns,tsd2d-ns = <60>; 490 cdns,tchsh-ns = <60>; 491 cdns,tslch-ns = <60>; 492 cdns,read-delay = <4>; 493 }; 494}; 495 496&mailbox0_cluster2 { 497 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 498 ti,mbox-rx = <0 0 2>; 499 ti,mbox-tx = <1 0 2>; 500 }; 501 502 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 503 ti,mbox-rx = <2 0 2>; 504 ti,mbox-tx = <3 0 2>; 505 }; 506}; 507 508&mailbox0_cluster3 { 509 status = "disabled"; 510}; 511 512&mailbox0_cluster4 { 513 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 514 ti,mbox-rx = <0 0 2>; 515 ti,mbox-tx = <1 0 2>; 516 }; 517 518 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 519 ti,mbox-rx = <2 0 2>; 520 ti,mbox-tx = <3 0 2>; 521 }; 522}; 523 524&mailbox0_cluster5 { 525 status = "disabled"; 526}; 527 528&mailbox0_cluster6 { 529 mbox_m4_0: mbox-m4-0 { 530 ti,mbox-rx = <0 0 2>; 531 ti,mbox-tx = <1 0 2>; 532 }; 533}; 534 535&mailbox0_cluster7 { 536 status = "disabled"; 537}; 538 539&main_r5fss0_core0 { 540 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core0>; 541 memory-region = <&main_r5fss0_core0_dma_memory_region>, 542 <&main_r5fss0_core0_memory_region>; 543}; 544 545&main_r5fss0_core1 { 546 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss0_core1>; 547 memory-region = <&main_r5fss0_core1_dma_memory_region>, 548 <&main_r5fss0_core1_memory_region>; 549}; 550 551&main_r5fss1_core0 { 552 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core0>; 553 memory-region = <&main_r5fss1_core0_dma_memory_region>, 554 <&main_r5fss1_core0_memory_region>; 555}; 556 557&main_r5fss1_core1 { 558 mboxes = <&mailbox0_cluster4 &mbox_main_r5fss1_core1>; 559 memory-region = <&main_r5fss1_core1_dma_memory_region>, 560 <&main_r5fss1_core1_memory_region>; 561}; 562 563&ecap0 { 564 status = "okay"; 565 /* PWM is available on Pin 1 of header J3 */ 566 pinctrl-names = "default"; 567 pinctrl-0 = <&main_ecap0_pins_default>; 568}; 569