1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	chosen {
16		stdout-path = "serial2:115200n8";
17		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
18	};
19
20	evm_12v0: fixedregulator-evm12v0 {
21		/* main supply */
22		compatible = "regulator-fixed";
23		regulator-name = "evm_12v0";
24		regulator-min-microvolt = <12000000>;
25		regulator-max-microvolt = <12000000>;
26		regulator-always-on;
27		regulator-boot-on;
28	};
29
30	vsys_3v3: fixedregulator-vsys3v3 {
31		/* Output of LM5140 */
32		compatible = "regulator-fixed";
33		regulator-name = "vsys_3v3";
34		regulator-min-microvolt = <3300000>;
35		regulator-max-microvolt = <3300000>;
36		vin-supply = <&evm_12v0>;
37		regulator-always-on;
38		regulator-boot-on;
39	};
40
41	vsys_5v0: fixedregulator-vsys5v0 {
42		/* Output of LM5140 */
43		compatible = "regulator-fixed";
44		regulator-name = "vsys_5v0";
45		regulator-min-microvolt = <5000000>;
46		regulator-max-microvolt = <5000000>;
47		vin-supply = <&evm_12v0>;
48		regulator-always-on;
49		regulator-boot-on;
50	};
51
52	vdd_mmc1: fixedregulator-sd {
53		/* Output of TPS22918 */
54		compatible = "regulator-fixed";
55		regulator-name = "vdd_mmc1";
56		regulator-min-microvolt = <3300000>;
57		regulator-max-microvolt = <3300000>;
58		regulator-boot-on;
59		enable-active-high;
60		vin-supply = <&vsys_3v3>;
61		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
62	};
63
64	vdd_sd_dv: gpio-regulator-TLV71033 {
65		/* Output of TLV71033 */
66		compatible = "regulator-gpio";
67		regulator-name = "tlv71033";
68		pinctrl-names = "default";
69		pinctrl-0 = <&vdd_sd_dv_pins_default>;
70		regulator-min-microvolt = <1800000>;
71		regulator-max-microvolt = <3300000>;
72		regulator-boot-on;
73		vin-supply = <&vsys_5v0>;
74		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
75		states = <1800000 0x0>,
76			 <3300000 0x1>;
77	};
78};
79
80&wkup_pmx0 {
81	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
82		pinctrl-single,pins = <
83			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
84			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
85			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
86			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
87			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
88			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
89			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
90			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
91			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
92			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
93			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_TXC */
94			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
95		>;
96	};
97
98	mcu_mdio_pins_default: mcu-mdio1-pins-default {
99		pinctrl-single,pins = <
100			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
101			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
102		>;
103	};
104};
105
106&main_pmx0 {
107	main_i2c0_pins_default: main-i2c0-pins-default {
108		pinctrl-single,pins = <
109			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
110			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
111		>;
112	};
113
114	main_i2c1_pins_default: main-i2c1-pins-default {
115		pinctrl-single,pins = <
116			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
117			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
118		>;
119	};
120
121	main_mmc1_pins_default: main-mmc1-pins-default {
122		pinctrl-single,pins = <
123			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
124			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
125			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
126			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
127			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
128			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
129			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
130			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
131		>;
132	};
133
134	main_usbss0_pins_default: main-usbss0-pins-default {
135		pinctrl-single,pins = <
136			J721E_IOPAD(0x120, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
137		>;
138	};
139
140	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
141		pinctrl-single,pins = <
142			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
143		>;
144	};
145};
146
147&wkup_uart0 {
148	/* Wakeup UART is used by System firmware */
149	status = "reserved";
150};
151
152&main_uart0 {
153	/* Shared with ATF on this platform */
154	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
155};
156
157&main_uart2 {
158	/* MAIN UART 2 is used by R5F firmware */
159	status = "reserved";
160};
161
162&main_uart3 {
163	/* UART not brought out */
164	status = "disabled";
165};
166
167&main_uart4 {
168	/* UART not brought out */
169	status = "disabled";
170};
171
172&main_uart5 {
173	/* UART not brought out */
174	status = "disabled";
175};
176
177&main_uart6 {
178	/* UART not brought out */
179	status = "disabled";
180};
181
182&main_uart7 {
183	/* UART not brought out */
184	status = "disabled";
185};
186
187&main_uart8 {
188	/* UART not brought out */
189	status = "disabled";
190};
191
192&main_uart9 {
193	/* UART not brought out */
194	status = "disabled";
195};
196
197&main_gpio2 {
198	status = "disabled";
199};
200
201&main_gpio4 {
202	status = "disabled";
203};
204
205&main_gpio6 {
206	status = "disabled";
207};
208
209&wkup_gpio1 {
210	status = "disabled";
211};
212
213&mcu_cpsw {
214	pinctrl-names = "default";
215	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
216};
217
218&davinci_mdio {
219	phy0: ethernet-phy@0 {
220		reg = <0>;
221		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
222		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
223	};
224};
225
226&cpsw_port1 {
227	phy-mode = "rgmii-rxid";
228	phy-handle = <&phy0>;
229};
230
231&main_i2c0 {
232	pinctrl-names = "default";
233	pinctrl-0 = <&main_i2c0_pins_default>;
234	clock-frequency = <400000>;
235
236	exp1: gpio@20 {
237		compatible = "ti,tca6416";
238		reg = <0x20>;
239		gpio-controller;
240		#gpio-cells = <2>;
241	};
242
243	exp2: gpio@22 {
244		compatible = "ti,tca6424";
245		reg = <0x22>;
246		gpio-controller;
247		#gpio-cells = <2>;
248	};
249};
250
251/*
252 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
253 * swapped on the CPB.
254 *
255 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
256 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
257 */
258&main_i2c1 {
259	pinctrl-names = "default";
260	pinctrl-0 = <&main_i2c1_pins_default>;
261	clock-frequency = <400000>;
262
263	exp3: gpio@20 {
264		compatible = "ti,tca6408";
265		reg = <0x20>;
266		gpio-controller;
267		#gpio-cells = <2>;
268		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
269				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
270				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
271	};
272};
273
274&main_sdhci0 {
275	/* eMMC */
276	non-removable;
277	ti,driver-strength-ohm = <50>;
278	disable-wp;
279};
280
281&main_sdhci1 {
282	/* SD card */
283	pinctrl-0 = <&main_mmc1_pins_default>;
284	pinctrl-names = "default";
285	vmmc-supply = <&vdd_mmc1>;
286	vqmmc-supply = <&vdd_sd_dv>;
287	ti,driver-strength-ohm = <50>;
288	disable-wp;
289};
290
291&serdes_ln_ctrl {
292	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
293		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
294};
295
296&usb_serdes_mux {
297	idle-states = <1>; /* USB0 to SERDES lane 3 */
298};
299
300&usbss0 {
301	pinctrl-names = "default";
302	pinctrl-0 = <&main_usbss0_pins_default>;
303	ti,vbus-divider;
304	ti,usb2-only;
305};
306
307&usb0 {
308	dr_mode = "otg";
309	maximum-speed = "high-speed";
310};
311
312&tscadc0 {
313	adc {
314		ti,adc-channels = <0 1 2 3 4 5 6 7>;
315	};
316};
317
318&serdes_refclk {
319	clock-frequency = <100000000>;
320};
321
322&serdes0 {
323	serdes0_pcie_link: phy@0 {
324		reg = <0>;
325		cdns,num-lanes = <2>;
326		#phy-cells = <0>;
327		cdns,phy-type = <PHY_TYPE_PCIE>;
328		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
329	};
330
331	serdes0_qsgmii_link: phy@1 {
332		reg = <2>;
333		cdns,num-lanes = <1>;
334		#phy-cells = <0>;
335		cdns,phy-type = <PHY_TYPE_QSGMII>;
336		resets = <&serdes_wiz0 3>;
337	};
338};
339
340&pcie1_rc {
341	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
342	phys = <&serdes0_pcie_link>;
343	phy-names = "pcie-phy";
344	num-lanes = <2>;
345};
346
347&pcie1_ep {
348	phys = <&serdes0_pcie_link>;
349	phy-names = "pcie-phy";
350	num-lanes = <2>;
351	status = "disabled";
352};
353