1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com/
4 */
5
6/dts-v1/;
7
8#include "k3-j7200-som-p0.dtsi"
9#include <dt-bindings/gpio/gpio.h>
10#include <dt-bindings/net/ti-dp83867.h>
11#include <dt-bindings/mux/ti-serdes.h>
12#include <dt-bindings/phy/phy.h>
13
14/ {
15	compatible = "ti,j7200-evm", "ti,j7200";
16	model = "Texas Instruments J7200 EVM";
17
18	chosen {
19		stdout-path = "serial2:115200n8";
20		bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
21	};
22
23	evm_12v0: fixedregulator-evm12v0 {
24		/* main supply */
25		compatible = "regulator-fixed";
26		regulator-name = "evm_12v0";
27		regulator-min-microvolt = <12000000>;
28		regulator-max-microvolt = <12000000>;
29		regulator-always-on;
30		regulator-boot-on;
31	};
32
33	vsys_3v3: fixedregulator-vsys3v3 {
34		/* Output of LM5140 */
35		compatible = "regulator-fixed";
36		regulator-name = "vsys_3v3";
37		regulator-min-microvolt = <3300000>;
38		regulator-max-microvolt = <3300000>;
39		vin-supply = <&evm_12v0>;
40		regulator-always-on;
41		regulator-boot-on;
42	};
43
44	vsys_5v0: fixedregulator-vsys5v0 {
45		/* Output of LM5140 */
46		compatible = "regulator-fixed";
47		regulator-name = "vsys_5v0";
48		regulator-min-microvolt = <5000000>;
49		regulator-max-microvolt = <5000000>;
50		vin-supply = <&evm_12v0>;
51		regulator-always-on;
52		regulator-boot-on;
53	};
54
55	vdd_mmc1: fixedregulator-sd {
56		/* Output of TPS22918 */
57		compatible = "regulator-fixed";
58		regulator-name = "vdd_mmc1";
59		regulator-min-microvolt = <3300000>;
60		regulator-max-microvolt = <3300000>;
61		regulator-boot-on;
62		enable-active-high;
63		vin-supply = <&vsys_3v3>;
64		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
65	};
66
67	vdd_sd_dv: gpio-regulator-TLV71033 {
68		/* Output of TLV71033 */
69		compatible = "regulator-gpio";
70		regulator-name = "tlv71033";
71		pinctrl-names = "default";
72		pinctrl-0 = <&vdd_sd_dv_pins_default>;
73		regulator-min-microvolt = <1800000>;
74		regulator-max-microvolt = <3300000>;
75		regulator-boot-on;
76		vin-supply = <&vsys_5v0>;
77		gpios = <&main_gpio0 55 GPIO_ACTIVE_HIGH>;
78		states = <1800000 0x0>,
79			 <3300000 0x1>;
80	};
81};
82
83&wkup_pmx2 {
84	mcu_cpsw_pins_default: mcu-cpsw-pins-default {
85		pinctrl-single,pins = <
86			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
87			J721E_WKUP_IOPAD(0x006c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
88			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
89			J721E_WKUP_IOPAD(0x0074, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
90			J721E_WKUP_IOPAD(0x0078, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
91			J721E_WKUP_IOPAD(0x007c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
92			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
93			J721E_WKUP_IOPAD(0x008c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
94			J721E_WKUP_IOPAD(0x0090, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
95			J721E_WKUP_IOPAD(0x0094, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
96			J721E_WKUP_IOPAD(0x0080, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
97			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
98		>;
99	};
100
101	mcu_mdio_pins_default: mcu-mdio1-pins-default {
102		pinctrl-single,pins = <
103			J721E_WKUP_IOPAD(0x009c, PIN_OUTPUT, 0) /* (L1) MCU_MDIO0_MDC */
104			J721E_WKUP_IOPAD(0x0098, PIN_INPUT, 0) /* (L4) MCU_MDIO0_MDIO */
105		>;
106	};
107};
108
109&main_pmx0 {
110	main_i2c0_pins_default: main-i2c0-pins-default {
111		pinctrl-single,pins = <
112			J721E_IOPAD(0xd4, PIN_INPUT_PULLUP, 0) /* (V3) I2C0_SCL */
113			J721E_IOPAD(0xd8, PIN_INPUT_PULLUP, 0) /* (W2) I2C0_SDA */
114		>;
115	};
116
117	main_i2c1_pins_default: main-i2c1-pins-default {
118		pinctrl-single,pins = <
119			J721E_IOPAD(0xdc, PIN_INPUT_PULLUP, 3) /* (U3) ECAP0_IN_APWM_OUT.I2C1_SCL */
120			J721E_IOPAD(0xe0, PIN_INPUT_PULLUP, 3) /* (T3) EXT_REFCLK1.I2C1_SDA */
121		>;
122	};
123
124	main_mmc1_pins_default: main-mmc1-pins-default {
125		pinctrl-single,pins = <
126			J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */
127			J721E_IOPAD(0x100, PIN_INPUT, 0) /* (P21) MMC1_CLK */
128			J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
129			J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */
130			J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */
131			J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */
132			J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */
133			J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */
134		>;
135	};
136
137	vdd_sd_dv_pins_default: vdd-sd-dv-pins-default {
138		pinctrl-single,pins = <
139			J721E_IOPAD(0xd0, PIN_OUTPUT, 7) /* (T5) SPI0_D1.GPIO0_55 */
140		>;
141	};
142};
143
144&main_pmx1 {
145	main_usbss0_pins_default: main-usbss0-pins-default {
146		pinctrl-single,pins = <
147			J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
148		>;
149	};
150};
151
152&wkup_uart0 {
153	/* Wakeup UART is used by System firmware */
154	status = "reserved";
155};
156
157&mcu_uart0 {
158	status = "okay";
159	/* Default pinmux */
160};
161
162&main_uart0 {
163	status = "okay";
164	/* Shared with ATF on this platform */
165	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
166};
167
168&main_uart1 {
169	status = "okay";
170	/* Default pinmux */
171};
172
173&main_uart2 {
174	/* MAIN UART 2 is used by R5F firmware */
175	status = "reserved";
176};
177
178&main_gpio2 {
179	status = "disabled";
180};
181
182&main_gpio4 {
183	status = "disabled";
184};
185
186&main_gpio6 {
187	status = "disabled";
188};
189
190&wkup_gpio1 {
191	status = "disabled";
192};
193
194&mcu_cpsw {
195	pinctrl-names = "default";
196	pinctrl-0 = <&mcu_cpsw_pins_default &mcu_mdio_pins_default>;
197};
198
199&davinci_mdio {
200	phy0: ethernet-phy@0 {
201		reg = <0>;
202		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
203		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
204	};
205};
206
207&cpsw_port1 {
208	phy-mode = "rgmii-rxid";
209	phy-handle = <&phy0>;
210};
211
212&main_i2c0 {
213	status = "okay";
214	pinctrl-names = "default";
215	pinctrl-0 = <&main_i2c0_pins_default>;
216	clock-frequency = <400000>;
217
218	exp1: gpio@20 {
219		compatible = "ti,tca6416";
220		reg = <0x20>;
221		gpio-controller;
222		#gpio-cells = <2>;
223	};
224
225	exp2: gpio@22 {
226		compatible = "ti,tca6424";
227		reg = <0x22>;
228		gpio-controller;
229		#gpio-cells = <2>;
230	};
231};
232
233/*
234 * The j7200 CPB board is identical to the CPB used for J721E, the SOMs can be
235 * swapped on the CPB.
236 *
237 * main_i2c1 of J7200 is connected to the CPB i2c bus labeled as i2c3.
238 * The i2c1 of the CPB (as it is labeled) is not connected to j7200.
239 */
240&main_i2c1 {
241	status = "okay";
242	pinctrl-names = "default";
243	pinctrl-0 = <&main_i2c1_pins_default>;
244	clock-frequency = <400000>;
245
246	exp3: gpio@20 {
247		compatible = "ti,tca6408";
248		reg = <0x20>;
249		gpio-controller;
250		#gpio-cells = <2>;
251		gpio-line-names = "CODEC_RSTz", "CODEC_SPARE1", "UB926_RESETn",
252				  "UB926_LOCK", "UB926_PWR_SW_CNTRL",
253				  "UB926_TUNER_RESET", "UB926_GPIO_SPARE", "";
254	};
255};
256
257&main_sdhci0 {
258	/* eMMC */
259	non-removable;
260	ti,driver-strength-ohm = <50>;
261	disable-wp;
262};
263
264&main_sdhci1 {
265	/* SD card */
266	pinctrl-0 = <&main_mmc1_pins_default>;
267	pinctrl-names = "default";
268	vmmc-supply = <&vdd_mmc1>;
269	vqmmc-supply = <&vdd_sd_dv>;
270	ti,driver-strength-ohm = <50>;
271	disable-wp;
272};
273
274&serdes_ln_ctrl {
275	idle-states = <J7200_SERDES0_LANE0_PCIE1_LANE0>, <J7200_SERDES0_LANE1_PCIE1_LANE1>,
276		      <J7200_SERDES0_LANE2_QSGMII_LANE1>, <J7200_SERDES0_LANE3_IP4_UNUSED>;
277};
278
279&usb_serdes_mux {
280	idle-states = <1>; /* USB0 to SERDES lane 3 */
281};
282
283&usbss0 {
284	pinctrl-names = "default";
285	pinctrl-0 = <&main_usbss0_pins_default>;
286	ti,vbus-divider;
287	ti,usb2-only;
288};
289
290&usb0 {
291	dr_mode = "otg";
292	maximum-speed = "high-speed";
293};
294
295&tscadc0 {
296	adc {
297		ti,adc-channels = <0 1 2 3 4 5 6 7>;
298	};
299};
300
301&serdes_refclk {
302	clock-frequency = <100000000>;
303};
304
305&serdes0 {
306	serdes0_pcie_link: phy@0 {
307		reg = <0>;
308		cdns,num-lanes = <2>;
309		#phy-cells = <0>;
310		cdns,phy-type = <PHY_TYPE_PCIE>;
311		resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>;
312	};
313
314	serdes0_qsgmii_link: phy@1 {
315		reg = <2>;
316		cdns,num-lanes = <1>;
317		#phy-cells = <0>;
318		cdns,phy-type = <PHY_TYPE_QSGMII>;
319		resets = <&serdes_wiz0 3>;
320	};
321};
322
323&pcie1_rc {
324	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
325	phys = <&serdes0_pcie_link>;
326	phy-names = "pcie-phy";
327	num-lanes = <2>;
328};
329
330&pcie1_ep {
331	phys = <&serdes0_pcie_link>;
332	phy-names = "pcie-phy";
333	num-lanes = <2>;
334	status = "disabled";
335};
336