1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * MPC8377E RDB Device Tree Source
4 *
5 * Copyright 2007, 2008 Freescale Semiconductor Inc.
6 */
7
8/dts-v1/;
9
10/ {
11	compatible = "fsl,mpc8377rdb";
12	#address-cells = <1>;
13	#size-cells = <1>;
14
15	aliases {
16		ethernet0 = &enet0;
17		ethernet1 = &enet1;
18		serial0 = &serial0;
19		serial1 = &serial1;
20		pci0 = &pci0;
21		pci1 = &pci1;
22		pci2 = &pci2;
23	};
24
25	cpus {
26		#address-cells = <1>;
27		#size-cells = <0>;
28
29		PowerPC,8377@0 {
30			device_type = "cpu";
31			reg = <0x0>;
32			d-cache-line-size = <32>;
33			i-cache-line-size = <32>;
34			d-cache-size = <32768>;
35			i-cache-size = <32768>;
36			timebase-frequency = <0>;
37			bus-frequency = <0>;
38			clock-frequency = <0>;
39		};
40	};
41
42	memory {
43		device_type = "memory";
44		reg = <0x00000000 0x10000000>;	// 256MB at 0
45	};
46
47	localbus@e0005000 {
48		#address-cells = <2>;
49		#size-cells = <1>;
50		compatible = "fsl,mpc8377-elbc", "fsl,elbc", "simple-bus";
51		reg = <0xe0005000 0x1000>;
52		interrupts = <77 0x8>;
53		interrupt-parent = <&ipic>;
54
55		// CS0 and CS1 are swapped when
56		// booting from nand, but the
57		// addresses are the same.
58		ranges = <0x0 0x0 0xfe000000 0x00800000
59		          0x1 0x0 0xe0600000 0x00008000
60		          0x2 0x0 0xf0000000 0x00020000
61		          0x3 0x0 0xfa000000 0x00008000>;
62
63		flash@0,0 {
64			#address-cells = <1>;
65			#size-cells = <1>;
66			compatible = "cfi-flash";
67			reg = <0x0 0x0 0x800000>;
68			bank-width = <2>;
69			device-width = <1>;
70		};
71
72		nand@1,0 {
73			#address-cells = <1>;
74			#size-cells = <1>;
75			compatible = "fsl,mpc8377-fcm-nand",
76			             "fsl,elbc-fcm-nand";
77			reg = <0x1 0x0 0x8000>;
78
79			u-boot@0 {
80				reg = <0x0 0x100000>;
81				read-only;
82			};
83
84			kernel@100000 {
85				reg = <0x100000 0x300000>;
86			};
87			fs@400000 {
88				reg = <0x400000 0x1c00000>;
89			};
90		};
91	};
92
93	immr@e0000000 {
94		#address-cells = <1>;
95		#size-cells = <1>;
96		device_type = "soc";
97		compatible = "simple-bus";
98		ranges = <0x0 0xe0000000 0x00100000>;
99		reg = <0xe0000000 0x00000200>;
100		bus-frequency = <0>;
101
102		wdt@200 {
103			device_type = "watchdog";
104			compatible = "mpc83xx_wdt";
105			reg = <0x200 0x100>;
106		};
107
108		gpio1: gpio-controller@c00 {
109			#gpio-cells = <2>;
110			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
111			reg = <0xc00 0x100>;
112			interrupts = <74 0x8>;
113			interrupt-parent = <&ipic>;
114			gpio-controller;
115		};
116
117		gpio2: gpio-controller@d00 {
118			#gpio-cells = <2>;
119			compatible = "fsl,mpc8377-gpio", "fsl,mpc8349-gpio";
120			reg = <0xd00 0x100>;
121			interrupts = <75 0x8>;
122			interrupt-parent = <&ipic>;
123			gpio-controller;
124		};
125
126		sleep-nexus {
127			#address-cells = <1>;
128			#size-cells = <1>;
129			compatible = "simple-bus";
130			sleep = <&pmc 0x0c000000>;
131			ranges;
132
133			i2c@3000 {
134				#address-cells = <1>;
135				#size-cells = <0>;
136				cell-index = <0>;
137				compatible = "fsl-i2c";
138				reg = <0x3000 0x100>;
139				interrupts = <14 0x8>;
140				interrupt-parent = <&ipic>;
141				dfsrr;
142
143				dtt@48 {
144					compatible = "national,lm75";
145					reg = <0x48>;
146				};
147
148				at24@50 {
149					compatible = "atmel,24c256";
150					reg = <0x50>;
151				};
152
153				rtc@68 {
154					compatible = "dallas,ds1339";
155					reg = <0x68>;
156				};
157
158				mcu_pio: mcu@a {
159					#gpio-cells = <2>;
160					compatible = "fsl,mc9s08qg8-mpc8377erdb",
161						     "fsl,mcu-mpc8349emitx";
162					reg = <0x0a>;
163					gpio-controller;
164				};
165			};
166
167			sdhci@2e000 {
168				compatible = "fsl,mpc8377-esdhc", "fsl,esdhc";
169				reg = <0x2e000 0x1000>;
170				interrupts = <42 0x8>;
171				interrupt-parent = <&ipic>;
172				sdhci,wp-inverted;
173				/* Filled in by U-Boot */
174				clock-frequency = <111111111>;
175			};
176		};
177
178		i2c@3100 {
179			#address-cells = <1>;
180			#size-cells = <0>;
181			cell-index = <1>;
182			compatible = "fsl-i2c";
183			reg = <0x3100 0x100>;
184			interrupts = <15 0x8>;
185			interrupt-parent = <&ipic>;
186			dfsrr;
187		};
188
189		spi@7000 {
190			cell-index = <0>;
191			compatible = "fsl,spi";
192			reg = <0x7000 0x1000>;
193			interrupts = <16 0x8>;
194			interrupt-parent = <&ipic>;
195			mode = "cpu";
196		};
197
198		dma@82a8 {
199			#address-cells = <1>;
200			#size-cells = <1>;
201			compatible = "fsl,mpc8377-dma", "fsl,elo-dma";
202			reg = <0x82a8 4>;
203			ranges = <0 0x8100 0x1a8>;
204			interrupt-parent = <&ipic>;
205			interrupts = <71 8>;
206			cell-index = <0>;
207			dma-channel@0 {
208				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
209				reg = <0 0x80>;
210				cell-index = <0>;
211				interrupt-parent = <&ipic>;
212				interrupts = <71 8>;
213			};
214			dma-channel@80 {
215				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
216				reg = <0x80 0x80>;
217				cell-index = <1>;
218				interrupt-parent = <&ipic>;
219				interrupts = <71 8>;
220			};
221			dma-channel@100 {
222				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
223				reg = <0x100 0x80>;
224				cell-index = <2>;
225				interrupt-parent = <&ipic>;
226				interrupts = <71 8>;
227			};
228			dma-channel@180 {
229				compatible = "fsl,mpc8377-dma-channel", "fsl,elo-dma-channel";
230				reg = <0x180 0x28>;
231				cell-index = <3>;
232				interrupt-parent = <&ipic>;
233				interrupts = <71 8>;
234			};
235		};
236
237		usb@23000 {
238			compatible = "fsl-usb2-dr";
239			reg = <0x23000 0x1000>;
240			#address-cells = <1>;
241			#size-cells = <0>;
242			interrupt-parent = <&ipic>;
243			interrupts = <38 0x8>;
244			phy_type = "ulpi";
245			sleep = <&pmc 0x00c00000>;
246		};
247
248		enet0: ethernet@24000 {
249			#address-cells = <1>;
250			#size-cells = <1>;
251			cell-index = <0>;
252			device_type = "network";
253			model = "eTSEC";
254			compatible = "gianfar";
255			reg = <0x24000 0x1000>;
256			ranges = <0x0 0x24000 0x1000>;
257			local-mac-address = [ 00 00 00 00 00 00 ];
258			interrupts = <32 0x8 33 0x8 34 0x8>;
259			phy-connection-type = "mii";
260			interrupt-parent = <&ipic>;
261			tbi-handle = <&tbi0>;
262			phy-handle = <&phy2>;
263			sleep = <&pmc 0xc0000000>;
264			fsl,magic-packet;
265
266			mdio@520 {
267				#address-cells = <1>;
268				#size-cells = <0>;
269				compatible = "fsl,gianfar-mdio";
270				reg = <0x520 0x20>;
271
272				phy2: ethernet-phy@2 {
273					interrupt-parent = <&ipic>;
274					interrupts = <17 0x8>;
275					reg = <0x2>;
276				};
277
278				tbi0: tbi-phy@11 {
279					reg = <0x11>;
280					device_type = "tbi-phy";
281				};
282			};
283		};
284
285		enet1: ethernet@25000 {
286			#address-cells = <1>;
287			#size-cells = <1>;
288			cell-index = <1>;
289			device_type = "network";
290			model = "eTSEC";
291			compatible = "gianfar";
292			reg = <0x25000 0x1000>;
293			ranges = <0x0 0x25000 0x1000>;
294			local-mac-address = [ 00 00 00 00 00 00 ];
295			interrupts = <35 0x8 36 0x8 37 0x8>;
296			phy-connection-type = "mii";
297			interrupt-parent = <&ipic>;
298			fixed-link = <1 1 1000 0 0>;
299			tbi-handle = <&tbi1>;
300			sleep = <&pmc 0x30000000>;
301			fsl,magic-packet;
302
303			mdio@520 {
304				#address-cells = <1>;
305				#size-cells = <0>;
306				compatible = "fsl,gianfar-tbi";
307				reg = <0x520 0x20>;
308
309				tbi1: tbi-phy@11 {
310					reg = <0x11>;
311					device_type = "tbi-phy";
312				};
313			};
314		};
315
316		serial0: serial@4500 {
317			cell-index = <0>;
318			device_type = "serial";
319			compatible = "fsl,ns16550", "ns16550";
320			reg = <0x4500 0x100>;
321			clock-frequency = <0>;
322			interrupts = <9 0x8>;
323			interrupt-parent = <&ipic>;
324		};
325
326		serial1: serial@4600 {
327			cell-index = <1>;
328			device_type = "serial";
329			compatible = "fsl,ns16550", "ns16550";
330			reg = <0x4600 0x100>;
331			clock-frequency = <0>;
332			interrupts = <10 0x8>;
333			interrupt-parent = <&ipic>;
334		};
335
336		crypto@30000 {
337			compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
338				     "fsl,sec2.1", "fsl,sec2.0";
339			reg = <0x30000 0x10000>;
340			interrupts = <11 0x8>;
341			interrupt-parent = <&ipic>;
342			fsl,num-channels = <4>;
343			fsl,channel-fifo-len = <24>;
344			fsl,exec-units-mask = <0x9fe>;
345			fsl,descriptor-types-mask = <0x3ab0ebf>;
346			sleep = <&pmc 0x03000000>;
347		};
348
349		sata@18000 {
350			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
351			reg = <0x18000 0x1000>;
352			interrupts = <44 0x8>;
353			interrupt-parent = <&ipic>;
354			sleep = <&pmc 0x000000c0>;
355		};
356
357		sata@19000 {
358			compatible = "fsl,mpc8377-sata", "fsl,pq-sata";
359			reg = <0x19000 0x1000>;
360			interrupts = <45 0x8>;
361			interrupt-parent = <&ipic>;
362			sleep = <&pmc 0x00000030>;
363		};
364
365		/* IPIC
366		 * interrupts cell = <intr #, sense>
367		 * sense values match linux IORESOURCE_IRQ_* defines:
368		 * sense == 8: Level, low assertion
369		 * sense == 2: Edge, high-to-low change
370		 */
371		ipic: interrupt-controller@700 {
372			compatible = "fsl,ipic";
373			interrupt-controller;
374			#address-cells = <0>;
375			#interrupt-cells = <2>;
376			reg = <0x700 0x100>;
377		};
378
379		pmc: power@b00 {
380			compatible = "fsl,mpc8377-pmc", "fsl,mpc8349-pmc";
381			reg = <0xb00 0x100 0xa00 0x100>;
382			interrupts = <80 0x8>;
383			interrupt-parent = <&ipic>;
384		};
385	};
386
387	pci0: pci@e0008500 {
388		interrupt-map-mask = <0xf800 0 0 7>;
389		interrupt-map = <
390				/* IRQ5 = 21 = 0x15, IRQ6 = 0x16, IRQ7 = 23 = 0x17 */
391
392				/* IDSEL AD14 IRQ6 inta */
393				 0x7000 0x0 0x0 0x1 &ipic 22 0x8
394
395				/* IDSEL AD15 IRQ5 inta, IRQ6 intb, IRQ7 intd */
396				 0x7800 0x0 0x0 0x1 &ipic 21 0x8
397				 0x7800 0x0 0x0 0x2 &ipic 22 0x8
398				 0x7800 0x0 0x0 0x4 &ipic 23 0x8
399
400				/* IDSEL AD28 IRQ7 inta, IRQ5 intb IRQ6 intc*/
401				 0xE000 0x0 0x0 0x1 &ipic 23 0x8
402				 0xE000 0x0 0x0 0x2 &ipic 21 0x8
403				 0xE000 0x0 0x0 0x3 &ipic 22 0x8>;
404		interrupt-parent = <&ipic>;
405		interrupts = <66 0x8>;
406		bus-range = <0 0>;
407		ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
408		          0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
409		          0x01000000 0x0 0x00000000 0xe0300000 0x0 0x00100000>;
410		sleep = <&pmc 0x00010000>;
411		clock-frequency = <66666666>;
412		#interrupt-cells = <1>;
413		#size-cells = <2>;
414		#address-cells = <3>;
415		reg = <0xe0008500 0x100		/* internal registers */
416		       0xe0008300 0x8>;		/* config space access registers */
417		compatible = "fsl,mpc8349-pci";
418		device_type = "pci";
419	};
420
421	pci1: pcie@e0009000 {
422		#address-cells = <3>;
423		#size-cells = <2>;
424		#interrupt-cells = <1>;
425		device_type = "pci";
426		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
427		reg = <0xe0009000 0x00001000>;
428		ranges = <0x02000000 0 0xa8000000 0xa8000000 0 0x10000000
429		          0x01000000 0 0x00000000 0xb8000000 0 0x00800000>;
430		bus-range = <0 255>;
431		interrupt-map-mask = <0xf800 0 0 7>;
432		interrupt-map = <0 0 0 1 &ipic 1 8
433				 0 0 0 2 &ipic 1 8
434				 0 0 0 3 &ipic 1 8
435				 0 0 0 4 &ipic 1 8>;
436		sleep = <&pmc 0x00300000>;
437		clock-frequency = <0>;
438
439		pcie@0 {
440			#address-cells = <3>;
441			#size-cells = <2>;
442			device_type = "pci";
443			reg = <0 0 0 0 0>;
444			ranges = <0x02000000 0 0xa8000000
445				  0x02000000 0 0xa8000000
446				  0 0x10000000
447				  0x01000000 0 0x00000000
448				  0x01000000 0 0x00000000
449				  0 0x00800000>;
450		};
451	};
452
453	pci2: pcie@e000a000 {
454		#address-cells = <3>;
455		#size-cells = <2>;
456		#interrupt-cells = <1>;
457		device_type = "pci";
458		compatible = "fsl,mpc8377-pcie", "fsl,mpc8314-pcie";
459		reg = <0xe000a000 0x00001000>;
460		ranges = <0x02000000 0 0xc8000000 0xc8000000 0 0x10000000
461			  0x01000000 0 0x00000000 0xd8000000 0 0x00800000>;
462		bus-range = <0 255>;
463		interrupt-map-mask = <0xf800 0 0 7>;
464		interrupt-map = <0 0 0 1 &ipic 2 8
465				 0 0 0 2 &ipic 2 8
466				 0 0 0 3 &ipic 2 8
467				 0 0 0 4 &ipic 2 8>;
468		sleep = <&pmc 0x000c0000>;
469		clock-frequency = <0>;
470
471		pcie@0 {
472			#address-cells = <3>;
473			#size-cells = <2>;
474			device_type = "pci";
475			reg = <0 0 0 0 0>;
476			ranges = <0x02000000 0 0xc8000000
477				  0x02000000 0 0xc8000000
478				  0 0x10000000
479				  0x01000000 0 0x00000000
480				  0x01000000 0 0x00000000
481				  0 0x00800000>;
482		};
483	};
484
485	leds {
486		compatible = "gpio-leds";
487
488		pwr {
489			gpios = <&mcu_pio 0 0>;
490			default-state = "on";
491		};
492
493		hdd {
494			gpios = <&mcu_pio 1 0>;
495			linux,default-trigger = "disk-activity";
496		};
497	};
498};
499