1 /*- 2 * BSD LICENSE 3 * 4 * Copyright (c) 2015-2020 Amazon.com, Inc. or its affiliates. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * * Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * * Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * * Neither the name of copyright holder nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 24 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 25 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 27 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 #ifndef _ENA_ADMIN_H_ 34 #define _ENA_ADMIN_H_ 35 36 #define ENA_ADMIN_EXTRA_PROPERTIES_STRING_LEN 32 37 #define ENA_ADMIN_EXTRA_PROPERTIES_COUNT 32 38 39 enum ena_admin_aq_opcode { 40 ENA_ADMIN_CREATE_SQ = 1, 41 ENA_ADMIN_DESTROY_SQ = 2, 42 ENA_ADMIN_CREATE_CQ = 3, 43 ENA_ADMIN_DESTROY_CQ = 4, 44 ENA_ADMIN_GET_FEATURE = 8, 45 ENA_ADMIN_SET_FEATURE = 9, 46 ENA_ADMIN_GET_STATS = 11, 47 }; 48 49 enum ena_admin_aq_completion_status { 50 ENA_ADMIN_SUCCESS = 0, 51 ENA_ADMIN_RESOURCE_ALLOCATION_FAILURE = 1, 52 ENA_ADMIN_BAD_OPCODE = 2, 53 ENA_ADMIN_UNSUPPORTED_OPCODE = 3, 54 ENA_ADMIN_MALFORMED_REQUEST = 4, 55 /* Additional status is provided in ACQ entry extended_status */ 56 ENA_ADMIN_ILLEGAL_PARAMETER = 5, 57 ENA_ADMIN_UNKNOWN_ERROR = 6, 58 ENA_ADMIN_RESOURCE_BUSY = 7, 59 }; 60 61 enum ena_admin_aq_feature_id { 62 ENA_ADMIN_DEVICE_ATTRIBUTES = 1, 63 ENA_ADMIN_MAX_QUEUES_NUM = 2, 64 ENA_ADMIN_HW_HINTS = 3, 65 ENA_ADMIN_LLQ = 4, 66 ENA_ADMIN_EXTRA_PROPERTIES_STRINGS = 5, 67 ENA_ADMIN_EXTRA_PROPERTIES_FLAGS = 6, 68 ENA_ADMIN_MAX_QUEUES_EXT = 7, 69 ENA_ADMIN_RSS_HASH_FUNCTION = 10, 70 ENA_ADMIN_STATELESS_OFFLOAD_CONFIG = 11, 71 ENA_ADMIN_RSS_REDIRECTION_TABLE_CONFIG = 12, 72 ENA_ADMIN_MTU = 14, 73 ENA_ADMIN_RSS_HASH_INPUT = 18, 74 ENA_ADMIN_INTERRUPT_MODERATION = 20, 75 ENA_ADMIN_AENQ_CONFIG = 26, 76 ENA_ADMIN_LINK_CONFIG = 27, 77 ENA_ADMIN_HOST_ATTR_CONFIG = 28, 78 ENA_ADMIN_FEATURES_OPCODE_NUM = 32, 79 }; 80 81 enum ena_admin_placement_policy_type { 82 /* descriptors and headers are in host memory */ 83 ENA_ADMIN_PLACEMENT_POLICY_HOST = 1, 84 /* descriptors and headers are in device memory (a.k.a Low Latency 85 * Queue) 86 */ 87 ENA_ADMIN_PLACEMENT_POLICY_DEV = 3, 88 }; 89 90 enum ena_admin_link_types { 91 ENA_ADMIN_LINK_SPEED_1G = 0x1, 92 ENA_ADMIN_LINK_SPEED_2_HALF_G = 0x2, 93 ENA_ADMIN_LINK_SPEED_5G = 0x4, 94 ENA_ADMIN_LINK_SPEED_10G = 0x8, 95 ENA_ADMIN_LINK_SPEED_25G = 0x10, 96 ENA_ADMIN_LINK_SPEED_40G = 0x20, 97 ENA_ADMIN_LINK_SPEED_50G = 0x40, 98 ENA_ADMIN_LINK_SPEED_100G = 0x80, 99 ENA_ADMIN_LINK_SPEED_200G = 0x100, 100 ENA_ADMIN_LINK_SPEED_400G = 0x200, 101 }; 102 103 enum ena_admin_completion_policy_type { 104 /* completion queue entry for each sq descriptor */ 105 ENA_ADMIN_COMPLETION_POLICY_DESC = 0, 106 /* completion queue entry upon request in sq descriptor */ 107 ENA_ADMIN_COMPLETION_POLICY_DESC_ON_DEMAND = 1, 108 /* current queue head pointer is updated in OS memory upon sq 109 * descriptor request 110 */ 111 ENA_ADMIN_COMPLETION_POLICY_HEAD_ON_DEMAND = 2, 112 /* current queue head pointer is updated in OS memory for each sq 113 * descriptor 114 */ 115 ENA_ADMIN_COMPLETION_POLICY_HEAD = 3, 116 }; 117 118 /* basic stats return ena_admin_basic_stats while extanded stats return a 119 * buffer (string format) with additional statistics per queue and per 120 * device id 121 */ 122 enum ena_admin_get_stats_type { 123 ENA_ADMIN_GET_STATS_TYPE_BASIC = 0, 124 ENA_ADMIN_GET_STATS_TYPE_EXTENDED = 1, 125 }; 126 127 enum ena_admin_get_stats_scope { 128 ENA_ADMIN_SPECIFIC_QUEUE = 0, 129 ENA_ADMIN_ETH_TRAFFIC = 1, 130 }; 131 132 struct ena_admin_aq_common_desc { 133 /* 11:0 : command_id 134 * 15:12 : reserved12 135 */ 136 uint16_t command_id; 137 138 /* as appears in ena_admin_aq_opcode */ 139 uint8_t opcode; 140 141 /* 0 : phase 142 * 1 : ctrl_data - control buffer address valid 143 * 2 : ctrl_data_indirect - control buffer address 144 * points to list of pages with addresses of control 145 * buffers 146 * 7:3 : reserved3 147 */ 148 uint8_t flags; 149 }; 150 151 /* used in ena_admin_aq_entry. Can point directly to control data, or to a 152 * page list chunk. Used also at the end of indirect mode page list chunks, 153 * for chaining. 154 */ 155 struct ena_admin_ctrl_buff_info { 156 uint32_t length; 157 158 struct ena_common_mem_addr address; 159 }; 160 161 struct ena_admin_sq { 162 uint16_t sq_idx; 163 164 /* 4:0 : reserved 165 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx 166 */ 167 uint8_t sq_identity; 168 169 uint8_t reserved1; 170 }; 171 172 struct ena_admin_aq_entry { 173 struct ena_admin_aq_common_desc aq_common_descriptor; 174 175 union { 176 uint32_t inline_data_w1[3]; 177 178 struct ena_admin_ctrl_buff_info control_buffer; 179 } u; 180 181 uint32_t inline_data_w4[12]; 182 }; 183 184 struct ena_admin_acq_common_desc { 185 /* command identifier to associate it with the aq descriptor 186 * 11:0 : command_id 187 * 15:12 : reserved12 188 */ 189 uint16_t command; 190 191 uint8_t status; 192 193 /* 0 : phase 194 * 7:1 : reserved1 195 */ 196 uint8_t flags; 197 198 uint16_t extended_status; 199 200 /* indicates to the driver which AQ entry has been consumed by the 201 * device and could be reused 202 */ 203 uint16_t sq_head_indx; 204 }; 205 206 struct ena_admin_acq_entry { 207 struct ena_admin_acq_common_desc acq_common_descriptor; 208 209 uint32_t response_specific_data[14]; 210 }; 211 212 struct ena_admin_aq_create_sq_cmd { 213 struct ena_admin_aq_common_desc aq_common_descriptor; 214 215 /* 4:0 : reserved0_w1 216 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx 217 */ 218 uint8_t sq_identity; 219 220 uint8_t reserved8_w1; 221 222 /* 3:0 : placement_policy - Describing where the SQ 223 * descriptor ring and the SQ packet headers reside: 224 * 0x1 - descriptors and headers are in OS memory, 225 * 0x3 - descriptors and headers in device memory 226 * (a.k.a Low Latency Queue) 227 * 6:4 : completion_policy - Describing what policy 228 * to use for generation completion entry (cqe) in 229 * the CQ associated with this SQ: 0x0 - cqe for each 230 * sq descriptor, 0x1 - cqe upon request in sq 231 * descriptor, 0x2 - current queue head pointer is 232 * updated in OS memory upon sq descriptor request 233 * 0x3 - current queue head pointer is updated in OS 234 * memory for each sq descriptor 235 * 7 : reserved15_w1 236 */ 237 uint8_t sq_caps_2; 238 239 /* 0 : is_physically_contiguous - Described if the 240 * queue ring memory is allocated in physical 241 * contiguous pages or split. 242 * 7:1 : reserved17_w1 243 */ 244 uint8_t sq_caps_3; 245 246 /* associated completion queue id. This CQ must be created prior to 247 * SQ creation 248 */ 249 uint16_t cq_idx; 250 251 /* submission queue depth in entries */ 252 uint16_t sq_depth; 253 254 /* SQ physical base address in OS memory. This field should not be 255 * used for Low Latency queues. Has to be page aligned. 256 */ 257 struct ena_common_mem_addr sq_ba; 258 259 /* specifies queue head writeback location in OS memory. Valid if 260 * completion_policy is set to completion_policy_head_on_demand or 261 * completion_policy_head. Has to be cache aligned 262 */ 263 struct ena_common_mem_addr sq_head_writeback; 264 265 uint32_t reserved0_w7; 266 267 uint32_t reserved0_w8; 268 }; 269 270 enum ena_admin_sq_direction { 271 ENA_ADMIN_SQ_DIRECTION_TX = 1, 272 ENA_ADMIN_SQ_DIRECTION_RX = 2, 273 }; 274 275 struct ena_admin_acq_create_sq_resp_desc { 276 struct ena_admin_acq_common_desc acq_common_desc; 277 278 uint16_t sq_idx; 279 280 uint16_t reserved; 281 282 /* queue doorbell address as an offset to PCIe MMIO REG BAR */ 283 uint32_t sq_doorbell_offset; 284 285 /* low latency queue ring base address as an offset to PCIe MMIO 286 * LLQ_MEM BAR 287 */ 288 uint32_t llq_descriptors_offset; 289 290 /* low latency queue headers' memory as an offset to PCIe MMIO 291 * LLQ_MEM BAR 292 */ 293 uint32_t llq_headers_offset; 294 }; 295 296 struct ena_admin_aq_destroy_sq_cmd { 297 struct ena_admin_aq_common_desc aq_common_descriptor; 298 299 struct ena_admin_sq sq; 300 }; 301 302 struct ena_admin_acq_destroy_sq_resp_desc { 303 struct ena_admin_acq_common_desc acq_common_desc; 304 }; 305 306 struct ena_admin_aq_create_cq_cmd { 307 struct ena_admin_aq_common_desc aq_common_descriptor; 308 309 /* 4:0 : reserved5 310 * 5 : interrupt_mode_enabled - if set, cq operates 311 * in interrupt mode, otherwise - polling 312 * 7:6 : reserved6 313 */ 314 uint8_t cq_caps_1; 315 316 /* 4:0 : cq_entry_size_words - size of CQ entry in 317 * 32-bit words, valid values: 4, 8. 318 * 7:5 : reserved7 319 */ 320 uint8_t cq_caps_2; 321 322 /* completion queue depth in # of entries. must be power of 2 */ 323 uint16_t cq_depth; 324 325 /* msix vector assigned to this cq */ 326 uint32_t msix_vector; 327 328 /* cq physical base address in OS memory. CQ must be physically 329 * contiguous 330 */ 331 struct ena_common_mem_addr cq_ba; 332 }; 333 334 struct ena_admin_acq_create_cq_resp_desc { 335 struct ena_admin_acq_common_desc acq_common_desc; 336 337 uint16_t cq_idx; 338 339 /* actual cq depth in number of entries */ 340 uint16_t cq_actual_depth; 341 342 uint32_t numa_node_register_offset; 343 344 uint32_t cq_head_db_register_offset; 345 346 uint32_t cq_interrupt_unmask_register_offset; 347 }; 348 349 struct ena_admin_aq_destroy_cq_cmd { 350 struct ena_admin_aq_common_desc aq_common_descriptor; 351 352 uint16_t cq_idx; 353 354 uint16_t reserved1; 355 }; 356 357 struct ena_admin_acq_destroy_cq_resp_desc { 358 struct ena_admin_acq_common_desc acq_common_desc; 359 }; 360 361 /* ENA AQ Get Statistics command. Extended statistics are placed in control 362 * buffer pointed by AQ entry 363 */ 364 struct ena_admin_aq_get_stats_cmd { 365 struct ena_admin_aq_common_desc aq_common_descriptor; 366 367 union { 368 /* command specific inline data */ 369 uint32_t inline_data_w1[3]; 370 371 struct ena_admin_ctrl_buff_info control_buffer; 372 } u; 373 374 /* stats type as defined in enum ena_admin_get_stats_type */ 375 uint8_t type; 376 377 /* stats scope defined in enum ena_admin_get_stats_scope */ 378 uint8_t scope; 379 380 uint16_t reserved3; 381 382 /* queue id. used when scope is specific_queue */ 383 uint16_t queue_idx; 384 385 /* device id, value 0xFFFF means mine. only privileged device can get 386 * stats of other device 387 */ 388 uint16_t device_id; 389 }; 390 391 /* Basic Statistics Command. */ 392 struct ena_admin_basic_stats { 393 uint32_t tx_bytes_low; 394 395 uint32_t tx_bytes_high; 396 397 uint32_t tx_pkts_low; 398 399 uint32_t tx_pkts_high; 400 401 uint32_t rx_bytes_low; 402 403 uint32_t rx_bytes_high; 404 405 uint32_t rx_pkts_low; 406 407 uint32_t rx_pkts_high; 408 409 uint32_t rx_drops_low; 410 411 uint32_t rx_drops_high; 412 413 uint32_t tx_drops_low; 414 415 uint32_t tx_drops_high; 416 }; 417 418 struct ena_admin_acq_get_stats_resp { 419 struct ena_admin_acq_common_desc acq_common_desc; 420 421 struct ena_admin_basic_stats basic_stats; 422 }; 423 424 struct ena_admin_get_set_feature_common_desc { 425 /* 1:0 : select - 0x1 - current value; 0x3 - default 426 * value 427 * 7:3 : reserved3 428 */ 429 uint8_t flags; 430 431 /* as appears in ena_admin_aq_feature_id */ 432 uint8_t feature_id; 433 434 /* The driver specifies the max feature version it supports and the 435 * device responds with the currently supported feature version. The 436 * field is zero based 437 */ 438 uint8_t feature_version; 439 440 uint8_t reserved8; 441 }; 442 443 struct ena_admin_device_attr_feature_desc { 444 uint32_t impl_id; 445 446 uint32_t device_version; 447 448 /* bitmap of ena_admin_aq_feature_id */ 449 uint32_t supported_features; 450 451 uint32_t reserved3; 452 453 /* Indicates how many bits are used physical address access. */ 454 uint32_t phys_addr_width; 455 456 /* Indicates how many bits are used virtual address access. */ 457 uint32_t virt_addr_width; 458 459 /* unicast MAC address (in Network byte order) */ 460 uint8_t mac_addr[6]; 461 462 uint8_t reserved7[2]; 463 464 uint32_t max_mtu; 465 }; 466 467 enum ena_admin_llq_header_location { 468 /* header is in descriptor list */ 469 ENA_ADMIN_INLINE_HEADER = 1, 470 /* header in a separate ring, implies 16B descriptor list entry */ 471 ENA_ADMIN_HEADER_RING = 2, 472 }; 473 474 enum ena_admin_llq_ring_entry_size { 475 ENA_ADMIN_LIST_ENTRY_SIZE_128B = 1, 476 ENA_ADMIN_LIST_ENTRY_SIZE_192B = 2, 477 ENA_ADMIN_LIST_ENTRY_SIZE_256B = 4, 478 }; 479 480 enum ena_admin_llq_num_descs_before_header { 481 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_0 = 0, 482 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_1 = 1, 483 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_2 = 2, 484 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_4 = 4, 485 ENA_ADMIN_LLQ_NUM_DESCS_BEFORE_HEADER_8 = 8, 486 }; 487 488 /* packet descriptor list entry always starts with one or more descriptors, 489 * followed by a header. The rest of the descriptors are located in the 490 * beginning of the subsequent entry. Stride refers to how the rest of the 491 * descriptors are placed. This field is relevant only for inline header 492 * mode 493 */ 494 enum ena_admin_llq_stride_ctrl { 495 ENA_ADMIN_SINGLE_DESC_PER_ENTRY = 1, 496 ENA_ADMIN_MULTIPLE_DESCS_PER_ENTRY = 2, 497 }; 498 499 enum ena_admin_accel_mode_feat { 500 ENA_ADMIN_DISABLE_META_CACHING = 0, 501 ENA_ADMIN_LIMIT_TX_BURST = 1, 502 }; 503 504 struct ena_admin_accel_mode_get { 505 /* bit field of enum ena_admin_accel_mode_feat */ 506 uint16_t supported_flags; 507 508 /* maximum burst size between two doorbells. The size is in bytes */ 509 uint16_t max_tx_burst_size; 510 }; 511 512 struct ena_admin_accel_mode_set { 513 /* bit field of enum ena_admin_accel_mode_feat */ 514 uint16_t enabled_flags; 515 516 uint16_t reserved; 517 }; 518 519 struct ena_admin_accel_mode_req { 520 union { 521 uint32_t raw[2]; 522 523 struct ena_admin_accel_mode_get get; 524 525 struct ena_admin_accel_mode_set set; 526 } u; 527 }; 528 529 struct ena_admin_feature_llq_desc { 530 uint32_t max_llq_num; 531 532 uint32_t max_llq_depth; 533 534 /* specify the header locations the device supports. bitfield of 535 * enum ena_admin_llq_header_location. 536 */ 537 uint16_t header_location_ctrl_supported; 538 539 /* the header location the driver selected to use. */ 540 uint16_t header_location_ctrl_enabled; 541 542 /* if inline header is specified - this is the size of descriptor 543 * list entry. If header in a separate ring is specified - this is 544 * the size of header ring entry. bitfield of enum 545 * ena_admin_llq_ring_entry_size. specify the entry sizes the device 546 * supports 547 */ 548 uint16_t entry_size_ctrl_supported; 549 550 /* the entry size the driver selected to use. */ 551 uint16_t entry_size_ctrl_enabled; 552 553 /* valid only if inline header is specified. First entry associated 554 * with the packet includes descriptors and header. Rest of the 555 * entries occupied by descriptors. This parameter defines the max 556 * number of descriptors precedding the header in the first entry. 557 * The field is bitfield of enum 558 * ena_admin_llq_num_descs_before_header and specify the values the 559 * device supports 560 */ 561 uint16_t desc_num_before_header_supported; 562 563 /* the desire field the driver selected to use */ 564 uint16_t desc_num_before_header_enabled; 565 566 /* valid only if inline was chosen. bitfield of enum 567 * ena_admin_llq_stride_ctrl 568 */ 569 uint16_t descriptors_stride_ctrl_supported; 570 571 /* the stride control the driver selected to use */ 572 uint16_t descriptors_stride_ctrl_enabled; 573 574 /* reserved */ 575 uint32_t reserved1; 576 577 /* accelerated low latency queues requirment. driver needs to 578 * support those requirments in order to use accelerated llq 579 */ 580 struct ena_admin_accel_mode_req accel_mode; 581 }; 582 583 struct ena_admin_queue_ext_feature_fields { 584 uint32_t max_tx_sq_num; 585 586 uint32_t max_tx_cq_num; 587 588 uint32_t max_rx_sq_num; 589 590 uint32_t max_rx_cq_num; 591 592 uint32_t max_tx_sq_depth; 593 594 uint32_t max_tx_cq_depth; 595 596 uint32_t max_rx_sq_depth; 597 598 uint32_t max_rx_cq_depth; 599 600 uint32_t max_tx_header_size; 601 602 /* Maximum Descriptors number, including meta descriptor, allowed for 603 * a single Tx packet 604 */ 605 uint16_t max_per_packet_tx_descs; 606 607 /* Maximum Descriptors number allowed for a single Rx packet */ 608 uint16_t max_per_packet_rx_descs; 609 }; 610 611 struct ena_admin_queue_feature_desc { 612 uint32_t max_sq_num; 613 614 uint32_t max_sq_depth; 615 616 uint32_t max_cq_num; 617 618 uint32_t max_cq_depth; 619 620 uint32_t max_legacy_llq_num; 621 622 uint32_t max_legacy_llq_depth; 623 624 uint32_t max_header_size; 625 626 /* Maximum Descriptors number, including meta descriptor, allowed for 627 * a single Tx packet 628 */ 629 uint16_t max_packet_tx_descs; 630 631 /* Maximum Descriptors number allowed for a single Rx packet */ 632 uint16_t max_packet_rx_descs; 633 }; 634 635 struct ena_admin_set_feature_mtu_desc { 636 /* exclude L2 */ 637 uint32_t mtu; 638 }; 639 640 struct ena_admin_get_extra_properties_strings_desc { 641 uint32_t count; 642 }; 643 644 struct ena_admin_get_extra_properties_flags_desc { 645 uint32_t flags; 646 }; 647 648 struct ena_admin_set_feature_host_attr_desc { 649 /* host OS info base address in OS memory. host info is 4KB of 650 * physically contiguous 651 */ 652 struct ena_common_mem_addr os_info_ba; 653 654 /* host debug area base address in OS memory. debug area must be 655 * physically contiguous 656 */ 657 struct ena_common_mem_addr debug_ba; 658 659 /* debug area size */ 660 uint32_t debug_area_size; 661 }; 662 663 struct ena_admin_feature_intr_moder_desc { 664 /* interrupt delay granularity in usec */ 665 uint16_t intr_delay_resolution; 666 667 uint16_t reserved; 668 }; 669 670 struct ena_admin_get_feature_link_desc { 671 /* Link speed in Mb */ 672 uint32_t speed; 673 674 /* bit field of enum ena_admin_link types */ 675 uint32_t supported; 676 677 /* 0 : autoneg 678 * 1 : duplex - Full Duplex 679 * 31:2 : reserved2 680 */ 681 uint32_t flags; 682 }; 683 684 struct ena_admin_feature_aenq_desc { 685 /* bitmask for AENQ groups the device can report */ 686 uint32_t supported_groups; 687 688 /* bitmask for AENQ groups to report */ 689 uint32_t enabled_groups; 690 }; 691 692 struct ena_admin_feature_offload_desc { 693 /* 0 : TX_L3_csum_ipv4 694 * 1 : TX_L4_ipv4_csum_part - The checksum field 695 * should be initialized with pseudo header checksum 696 * 2 : TX_L4_ipv4_csum_full 697 * 3 : TX_L4_ipv6_csum_part - The checksum field 698 * should be initialized with pseudo header checksum 699 * 4 : TX_L4_ipv6_csum_full 700 * 5 : tso_ipv4 701 * 6 : tso_ipv6 702 * 7 : tso_ecn 703 */ 704 uint32_t tx; 705 706 /* Receive side supported stateless offload 707 * 0 : RX_L3_csum_ipv4 - IPv4 checksum 708 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum 709 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum 710 * 3 : RX_hash - Hash calculation 711 */ 712 uint32_t rx_supported; 713 714 uint32_t rx_enabled; 715 }; 716 717 enum ena_admin_hash_functions { 718 ENA_ADMIN_TOEPLITZ = 1, 719 ENA_ADMIN_CRC32 = 2, 720 }; 721 722 struct ena_admin_feature_rss_flow_hash_control { 723 uint32_t keys_num; 724 725 uint32_t reserved; 726 727 uint32_t key[10]; 728 }; 729 730 struct ena_admin_feature_rss_flow_hash_function { 731 /* 7:0 : funcs - bitmask of ena_admin_hash_functions */ 732 uint32_t supported_func; 733 734 /* 7:0 : selected_func - bitmask of 735 * ena_admin_hash_functions 736 */ 737 uint32_t selected_func; 738 739 /* initial value */ 740 uint32_t init_val; 741 }; 742 743 /* RSS flow hash protocols */ 744 enum ena_admin_flow_hash_proto { 745 ENA_ADMIN_RSS_TCP4 = 0, 746 ENA_ADMIN_RSS_UDP4 = 1, 747 ENA_ADMIN_RSS_TCP6 = 2, 748 ENA_ADMIN_RSS_UDP6 = 3, 749 ENA_ADMIN_RSS_IP4 = 4, 750 ENA_ADMIN_RSS_IP6 = 5, 751 ENA_ADMIN_RSS_IP4_FRAG = 6, 752 ENA_ADMIN_RSS_NOT_IP = 7, 753 /* TCPv6 with extension header */ 754 ENA_ADMIN_RSS_TCP6_EX = 8, 755 /* IPv6 with extension header */ 756 ENA_ADMIN_RSS_IP6_EX = 9, 757 ENA_ADMIN_RSS_PROTO_NUM = 16, 758 }; 759 760 /* RSS flow hash fields */ 761 enum ena_admin_flow_hash_fields { 762 /* Ethernet Dest Addr */ 763 ENA_ADMIN_RSS_L2_DA = BIT(0), 764 /* Ethernet Src Addr */ 765 ENA_ADMIN_RSS_L2_SA = BIT(1), 766 /* ipv4/6 Dest Addr */ 767 ENA_ADMIN_RSS_L3_DA = BIT(2), 768 /* ipv4/6 Src Addr */ 769 ENA_ADMIN_RSS_L3_SA = BIT(3), 770 /* tcp/udp Dest Port */ 771 ENA_ADMIN_RSS_L4_DP = BIT(4), 772 /* tcp/udp Src Port */ 773 ENA_ADMIN_RSS_L4_SP = BIT(5), 774 }; 775 776 struct ena_admin_proto_input { 777 /* flow hash fields (bitwise according to ena_admin_flow_hash_fields) */ 778 uint16_t fields; 779 780 uint16_t reserved2; 781 }; 782 783 struct ena_admin_feature_rss_hash_control { 784 struct ena_admin_proto_input supported_fields[ENA_ADMIN_RSS_PROTO_NUM]; 785 786 struct ena_admin_proto_input selected_fields[ENA_ADMIN_RSS_PROTO_NUM]; 787 788 struct ena_admin_proto_input reserved2[ENA_ADMIN_RSS_PROTO_NUM]; 789 790 struct ena_admin_proto_input reserved3[ENA_ADMIN_RSS_PROTO_NUM]; 791 }; 792 793 struct ena_admin_feature_rss_flow_hash_input { 794 /* supported hash input sorting 795 * 1 : L3_sort - support swap L3 addresses if DA is 796 * smaller than SA 797 * 2 : L4_sort - support swap L4 ports if DP smaller 798 * SP 799 */ 800 uint16_t supported_input_sort; 801 802 /* enabled hash input sorting 803 * 1 : enable_L3_sort - enable swap L3 addresses if 804 * DA smaller than SA 805 * 2 : enable_L4_sort - enable swap L4 ports if DP 806 * smaller than SP 807 */ 808 uint16_t enabled_input_sort; 809 }; 810 811 enum ena_admin_os_type { 812 ENA_ADMIN_OS_LINUX = 1, 813 ENA_ADMIN_OS_WIN = 2, 814 ENA_ADMIN_OS_DPDK = 3, 815 ENA_ADMIN_OS_FREEBSD = 4, 816 ENA_ADMIN_OS_IPXE = 5, 817 ENA_ADMIN_OS_ESXI = 6, 818 ENA_ADMIN_OS_GROUPS_NUM = 6, 819 }; 820 821 struct ena_admin_host_info { 822 /* defined in enum ena_admin_os_type */ 823 uint32_t os_type; 824 825 /* os distribution string format */ 826 uint8_t os_dist_str[128]; 827 828 /* OS distribution numeric format */ 829 uint32_t os_dist; 830 831 /* kernel version string format */ 832 uint8_t kernel_ver_str[32]; 833 834 /* Kernel version numeric format */ 835 uint32_t kernel_ver; 836 837 /* 7:0 : major 838 * 15:8 : minor 839 * 23:16 : sub_minor 840 * 31:24 : module_type 841 */ 842 uint32_t driver_version; 843 844 /* features bitmap */ 845 uint32_t supported_network_features[2]; 846 847 /* ENA spec version of driver */ 848 uint16_t ena_spec_version; 849 850 /* ENA device's Bus, Device and Function 851 * 2:0 : function 852 * 7:3 : device 853 * 15:8 : bus 854 */ 855 uint16_t bdf; 856 857 /* Number of CPUs */ 858 uint16_t num_cpus; 859 860 uint16_t reserved; 861 862 /* 0 : mutable_rss_table_size 863 * 1 : rx_offset 864 * 2 : interrupt_moderation 865 * 3 : map_rx_buf_bidirectional 866 * 31:4 : reserved 867 */ 868 uint32_t driver_supported_features; 869 }; 870 871 struct ena_admin_rss_ind_table_entry { 872 uint16_t cq_idx; 873 874 uint16_t reserved; 875 }; 876 877 struct ena_admin_feature_rss_ind_table { 878 /* min supported table size (2^min_size) */ 879 uint16_t min_size; 880 881 /* max supported table size (2^max_size) */ 882 uint16_t max_size; 883 884 /* table size (2^size) */ 885 uint16_t size; 886 887 /* 0 : one_entry_update - The ENA device supports 888 * setting a single RSS table entry 889 */ 890 uint8_t flags; 891 892 uint8_t reserved; 893 894 /* index of the inline entry. 0xFFFFFFFF means invalid */ 895 uint32_t inline_index; 896 897 /* used for updating single entry, ignored when setting the entire 898 * table through the control buffer. 899 */ 900 struct ena_admin_rss_ind_table_entry inline_entry; 901 }; 902 903 /* When hint value is 0, driver should use it's own predefined value */ 904 struct ena_admin_ena_hw_hints { 905 /* value in ms */ 906 uint16_t mmio_read_timeout; 907 908 /* value in ms */ 909 uint16_t driver_watchdog_timeout; 910 911 /* Per packet tx completion timeout. value in ms */ 912 uint16_t missing_tx_completion_timeout; 913 914 uint16_t missed_tx_completion_count_threshold_to_reset; 915 916 /* value in ms */ 917 uint16_t admin_completion_tx_timeout; 918 919 uint16_t netdev_wd_timeout; 920 921 uint16_t max_tx_sgl_size; 922 923 uint16_t max_rx_sgl_size; 924 925 uint16_t reserved[8]; 926 }; 927 928 struct ena_admin_get_feat_cmd { 929 struct ena_admin_aq_common_desc aq_common_descriptor; 930 931 struct ena_admin_ctrl_buff_info control_buffer; 932 933 struct ena_admin_get_set_feature_common_desc feat_common; 934 935 uint32_t raw[11]; 936 }; 937 938 struct ena_admin_queue_ext_feature_desc { 939 /* version */ 940 uint8_t version; 941 942 uint8_t reserved1[3]; 943 944 union { 945 struct ena_admin_queue_ext_feature_fields max_queue_ext; 946 947 uint32_t raw[10]; 948 } ; 949 }; 950 951 struct ena_admin_get_feat_resp { 952 struct ena_admin_acq_common_desc acq_common_desc; 953 954 union { 955 uint32_t raw[14]; 956 957 struct ena_admin_device_attr_feature_desc dev_attr; 958 959 struct ena_admin_feature_llq_desc llq; 960 961 struct ena_admin_queue_feature_desc max_queue; 962 963 struct ena_admin_queue_ext_feature_desc max_queue_ext; 964 965 struct ena_admin_feature_aenq_desc aenq; 966 967 struct ena_admin_get_feature_link_desc link; 968 969 struct ena_admin_feature_offload_desc offload; 970 971 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 972 973 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 974 975 struct ena_admin_feature_rss_ind_table ind_table; 976 977 struct ena_admin_feature_intr_moder_desc intr_moderation; 978 979 struct ena_admin_ena_hw_hints hw_hints; 980 981 struct ena_admin_get_extra_properties_strings_desc extra_properties_strings; 982 983 struct ena_admin_get_extra_properties_flags_desc extra_properties_flags; 984 } u; 985 }; 986 987 struct ena_admin_set_feat_cmd { 988 struct ena_admin_aq_common_desc aq_common_descriptor; 989 990 struct ena_admin_ctrl_buff_info control_buffer; 991 992 struct ena_admin_get_set_feature_common_desc feat_common; 993 994 union { 995 uint32_t raw[11]; 996 997 /* mtu size */ 998 struct ena_admin_set_feature_mtu_desc mtu; 999 1000 /* host attributes */ 1001 struct ena_admin_set_feature_host_attr_desc host_attr; 1002 1003 /* AENQ configuration */ 1004 struct ena_admin_feature_aenq_desc aenq; 1005 1006 /* rss flow hash function */ 1007 struct ena_admin_feature_rss_flow_hash_function flow_hash_func; 1008 1009 /* rss flow hash input */ 1010 struct ena_admin_feature_rss_flow_hash_input flow_hash_input; 1011 1012 /* rss indirection table */ 1013 struct ena_admin_feature_rss_ind_table ind_table; 1014 1015 /* LLQ configuration */ 1016 struct ena_admin_feature_llq_desc llq; 1017 } u; 1018 }; 1019 1020 struct ena_admin_set_feat_resp { 1021 struct ena_admin_acq_common_desc acq_common_desc; 1022 1023 union { 1024 uint32_t raw[14]; 1025 } u; 1026 }; 1027 1028 struct ena_admin_aenq_common_desc { 1029 uint16_t group; 1030 1031 uint16_t syndrom; 1032 1033 /* 0 : phase 1034 * 7:1 : reserved - MBZ 1035 */ 1036 uint8_t flags; 1037 1038 uint8_t reserved1[3]; 1039 1040 uint32_t timestamp_low; 1041 1042 uint32_t timestamp_high; 1043 }; 1044 1045 /* asynchronous event notification groups */ 1046 enum ena_admin_aenq_group { 1047 ENA_ADMIN_LINK_CHANGE = 0, 1048 ENA_ADMIN_FATAL_ERROR = 1, 1049 ENA_ADMIN_WARNING = 2, 1050 ENA_ADMIN_NOTIFICATION = 3, 1051 ENA_ADMIN_KEEP_ALIVE = 4, 1052 ENA_ADMIN_AENQ_GROUPS_NUM = 5, 1053 }; 1054 1055 enum ena_admin_aenq_notification_syndrom { 1056 ENA_ADMIN_SUSPEND = 0, 1057 ENA_ADMIN_RESUME = 1, 1058 ENA_ADMIN_UPDATE_HINTS = 2, 1059 }; 1060 1061 struct ena_admin_aenq_entry { 1062 struct ena_admin_aenq_common_desc aenq_common_desc; 1063 1064 /* command specific inline data */ 1065 uint32_t inline_data_w4[12]; 1066 }; 1067 1068 struct ena_admin_aenq_link_change_desc { 1069 struct ena_admin_aenq_common_desc aenq_common_desc; 1070 1071 /* 0 : link_status */ 1072 uint32_t flags; 1073 }; 1074 1075 struct ena_admin_aenq_keep_alive_desc { 1076 struct ena_admin_aenq_common_desc aenq_common_desc; 1077 1078 uint32_t rx_drops_low; 1079 1080 uint32_t rx_drops_high; 1081 1082 uint32_t tx_drops_low; 1083 1084 uint32_t tx_drops_high; 1085 }; 1086 1087 struct ena_admin_ena_mmio_req_read_less_resp { 1088 uint16_t req_id; 1089 1090 uint16_t reg_off; 1091 1092 /* value is valid when poll is cleared */ 1093 uint32_t reg_val; 1094 }; 1095 1096 /* aq_common_desc */ 1097 #define ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1098 #define ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK BIT(0) 1099 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT 1 1100 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK BIT(1) 1101 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT 2 1102 #define ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK BIT(2) 1103 1104 /* sq */ 1105 #define ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT 5 1106 #define ENA_ADMIN_SQ_SQ_DIRECTION_MASK GENMASK(7, 5) 1107 1108 /* acq_common_desc */ 1109 #define ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK GENMASK(11, 0) 1110 #define ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK BIT(0) 1111 1112 /* aq_create_sq_cmd */ 1113 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT 5 1114 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK GENMASK(7, 5) 1115 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK GENMASK(3, 0) 1116 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT 4 1117 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK GENMASK(6, 4) 1118 #define ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK BIT(0) 1119 1120 /* aq_create_cq_cmd */ 1121 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT 5 1122 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK BIT(5) 1123 #define ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK GENMASK(4, 0) 1124 1125 /* get_set_feature_common_desc */ 1126 #define ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK GENMASK(1, 0) 1127 1128 /* get_feature_link_desc */ 1129 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK BIT(0) 1130 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT 1 1131 #define ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK BIT(1) 1132 1133 /* feature_offload_desc */ 1134 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK BIT(0) 1135 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT 1 1136 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK BIT(1) 1137 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT 2 1138 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK BIT(2) 1139 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT 3 1140 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK BIT(3) 1141 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT 4 1142 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK BIT(4) 1143 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT 5 1144 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK BIT(5) 1145 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT 6 1146 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK BIT(6) 1147 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT 7 1148 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK BIT(7) 1149 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK BIT(0) 1150 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT 1 1151 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK BIT(1) 1152 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT 2 1153 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK BIT(2) 1154 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT 3 1155 #define ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK BIT(3) 1156 1157 /* feature_rss_flow_hash_function */ 1158 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK GENMASK(7, 0) 1159 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK GENMASK(7, 0) 1160 1161 /* feature_rss_flow_hash_input */ 1162 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT 1 1163 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK BIT(1) 1164 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT 2 1165 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK BIT(2) 1166 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT 1 1167 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK BIT(1) 1168 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT 2 1169 #define ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK BIT(2) 1170 1171 /* host_info */ 1172 #define ENA_ADMIN_HOST_INFO_MAJOR_MASK GENMASK(7, 0) 1173 #define ENA_ADMIN_HOST_INFO_MINOR_SHIFT 8 1174 #define ENA_ADMIN_HOST_INFO_MINOR_MASK GENMASK(15, 8) 1175 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT 16 1176 #define ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK GENMASK(23, 16) 1177 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT 24 1178 #define ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK GENMASK(31, 24) 1179 #define ENA_ADMIN_HOST_INFO_FUNCTION_MASK GENMASK(2, 0) 1180 #define ENA_ADMIN_HOST_INFO_DEVICE_SHIFT 3 1181 #define ENA_ADMIN_HOST_INFO_DEVICE_MASK GENMASK(7, 3) 1182 #define ENA_ADMIN_HOST_INFO_BUS_SHIFT 8 1183 #define ENA_ADMIN_HOST_INFO_BUS_MASK GENMASK(15, 8) 1184 #define ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK BIT(0) 1185 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT 1 1186 #define ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK BIT(1) 1187 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT 2 1188 #define ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK BIT(2) 1189 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT 3 1190 #define ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK BIT(3) 1191 1192 /* feature_rss_ind_table */ 1193 #define ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK BIT(0) 1194 1195 /* aenq_common_desc */ 1196 #define ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK BIT(0) 1197 1198 /* aenq_link_change_desc */ 1199 #define ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK BIT(0) 1200 1201 #if !defined(DEFS_LINUX_MAINLINE) 1202 static inline uint16_t get_ena_admin_aq_common_desc_command_id(const struct ena_admin_aq_common_desc *p) 1203 { 1204 return p->command_id & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1205 } 1206 1207 static inline void set_ena_admin_aq_common_desc_command_id(struct ena_admin_aq_common_desc *p, uint16_t val) 1208 { 1209 p->command_id |= val & ENA_ADMIN_AQ_COMMON_DESC_COMMAND_ID_MASK; 1210 } 1211 1212 static inline uint8_t get_ena_admin_aq_common_desc_phase(const struct ena_admin_aq_common_desc *p) 1213 { 1214 return p->flags & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1215 } 1216 1217 static inline void set_ena_admin_aq_common_desc_phase(struct ena_admin_aq_common_desc *p, uint8_t val) 1218 { 1219 p->flags |= val & ENA_ADMIN_AQ_COMMON_DESC_PHASE_MASK; 1220 } 1221 1222 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data(const struct ena_admin_aq_common_desc *p) 1223 { 1224 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT; 1225 } 1226 1227 static inline void set_ena_admin_aq_common_desc_ctrl_data(struct ena_admin_aq_common_desc *p, uint8_t val) 1228 { 1229 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_MASK; 1230 } 1231 1232 static inline uint8_t get_ena_admin_aq_common_desc_ctrl_data_indirect(const struct ena_admin_aq_common_desc *p) 1233 { 1234 return (p->flags & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK) >> ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT; 1235 } 1236 1237 static inline void set_ena_admin_aq_common_desc_ctrl_data_indirect(struct ena_admin_aq_common_desc *p, uint8_t val) 1238 { 1239 p->flags |= (val << ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_SHIFT) & ENA_ADMIN_AQ_COMMON_DESC_CTRL_DATA_INDIRECT_MASK; 1240 } 1241 1242 static inline uint8_t get_ena_admin_sq_sq_direction(const struct ena_admin_sq *p) 1243 { 1244 return (p->sq_identity & ENA_ADMIN_SQ_SQ_DIRECTION_MASK) >> ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT; 1245 } 1246 1247 static inline void set_ena_admin_sq_sq_direction(struct ena_admin_sq *p, uint8_t val) 1248 { 1249 p->sq_identity |= (val << ENA_ADMIN_SQ_SQ_DIRECTION_SHIFT) & ENA_ADMIN_SQ_SQ_DIRECTION_MASK; 1250 } 1251 1252 static inline uint16_t get_ena_admin_acq_common_desc_command_id(const struct ena_admin_acq_common_desc *p) 1253 { 1254 return p->command & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1255 } 1256 1257 static inline void set_ena_admin_acq_common_desc_command_id(struct ena_admin_acq_common_desc *p, uint16_t val) 1258 { 1259 p->command |= val & ENA_ADMIN_ACQ_COMMON_DESC_COMMAND_ID_MASK; 1260 } 1261 1262 static inline uint8_t get_ena_admin_acq_common_desc_phase(const struct ena_admin_acq_common_desc *p) 1263 { 1264 return p->flags & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1265 } 1266 1267 static inline void set_ena_admin_acq_common_desc_phase(struct ena_admin_acq_common_desc *p, uint8_t val) 1268 { 1269 p->flags |= val & ENA_ADMIN_ACQ_COMMON_DESC_PHASE_MASK; 1270 } 1271 1272 static inline uint8_t get_ena_admin_aq_create_sq_cmd_sq_direction(const struct ena_admin_aq_create_sq_cmd *p) 1273 { 1274 return (p->sq_identity & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT; 1275 } 1276 1277 static inline void set_ena_admin_aq_create_sq_cmd_sq_direction(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1278 { 1279 p->sq_identity |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_SQ_DIRECTION_MASK; 1280 } 1281 1282 static inline uint8_t get_ena_admin_aq_create_sq_cmd_placement_policy(const struct ena_admin_aq_create_sq_cmd *p) 1283 { 1284 return p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1285 } 1286 1287 static inline void set_ena_admin_aq_create_sq_cmd_placement_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1288 { 1289 p->sq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_PLACEMENT_POLICY_MASK; 1290 } 1291 1292 static inline uint8_t get_ena_admin_aq_create_sq_cmd_completion_policy(const struct ena_admin_aq_create_sq_cmd *p) 1293 { 1294 return (p->sq_caps_2 & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK) >> ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT; 1295 } 1296 1297 static inline void set_ena_admin_aq_create_sq_cmd_completion_policy(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1298 { 1299 p->sq_caps_2 |= (val << ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_SHIFT) & ENA_ADMIN_AQ_CREATE_SQ_CMD_COMPLETION_POLICY_MASK; 1300 } 1301 1302 static inline uint8_t get_ena_admin_aq_create_sq_cmd_is_physically_contiguous(const struct ena_admin_aq_create_sq_cmd *p) 1303 { 1304 return p->sq_caps_3 & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1305 } 1306 1307 static inline void set_ena_admin_aq_create_sq_cmd_is_physically_contiguous(struct ena_admin_aq_create_sq_cmd *p, uint8_t val) 1308 { 1309 p->sq_caps_3 |= val & ENA_ADMIN_AQ_CREATE_SQ_CMD_IS_PHYSICALLY_CONTIGUOUS_MASK; 1310 } 1311 1312 static inline uint8_t get_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(const struct ena_admin_aq_create_cq_cmd *p) 1313 { 1314 return (p->cq_caps_1 & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK) >> ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT; 1315 } 1316 1317 static inline void set_ena_admin_aq_create_cq_cmd_interrupt_mode_enabled(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1318 { 1319 p->cq_caps_1 |= (val << ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_SHIFT) & ENA_ADMIN_AQ_CREATE_CQ_CMD_INTERRUPT_MODE_ENABLED_MASK; 1320 } 1321 1322 static inline uint8_t get_ena_admin_aq_create_cq_cmd_cq_entry_size_words(const struct ena_admin_aq_create_cq_cmd *p) 1323 { 1324 return p->cq_caps_2 & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1325 } 1326 1327 static inline void set_ena_admin_aq_create_cq_cmd_cq_entry_size_words(struct ena_admin_aq_create_cq_cmd *p, uint8_t val) 1328 { 1329 p->cq_caps_2 |= val & ENA_ADMIN_AQ_CREATE_CQ_CMD_CQ_ENTRY_SIZE_WORDS_MASK; 1330 } 1331 1332 static inline uint8_t get_ena_admin_get_set_feature_common_desc_select(const struct ena_admin_get_set_feature_common_desc *p) 1333 { 1334 return p->flags & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1335 } 1336 1337 static inline void set_ena_admin_get_set_feature_common_desc_select(struct ena_admin_get_set_feature_common_desc *p, uint8_t val) 1338 { 1339 p->flags |= val & ENA_ADMIN_GET_SET_FEATURE_COMMON_DESC_SELECT_MASK; 1340 } 1341 1342 static inline uint32_t get_ena_admin_get_feature_link_desc_autoneg(const struct ena_admin_get_feature_link_desc *p) 1343 { 1344 return p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1345 } 1346 1347 static inline void set_ena_admin_get_feature_link_desc_autoneg(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1348 { 1349 p->flags |= val & ENA_ADMIN_GET_FEATURE_LINK_DESC_AUTONEG_MASK; 1350 } 1351 1352 static inline uint32_t get_ena_admin_get_feature_link_desc_duplex(const struct ena_admin_get_feature_link_desc *p) 1353 { 1354 return (p->flags & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK) >> ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT; 1355 } 1356 1357 static inline void set_ena_admin_get_feature_link_desc_duplex(struct ena_admin_get_feature_link_desc *p, uint32_t val) 1358 { 1359 p->flags |= (val << ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_SHIFT) & ENA_ADMIN_GET_FEATURE_LINK_DESC_DUPLEX_MASK; 1360 } 1361 1362 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1363 { 1364 return p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1365 } 1366 1367 static inline void set_ena_admin_feature_offload_desc_TX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1368 { 1369 p->tx |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L3_CSUM_IPV4_MASK; 1370 } 1371 1372 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(const struct ena_admin_feature_offload_desc *p) 1373 { 1374 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT; 1375 } 1376 1377 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1378 { 1379 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_PART_MASK; 1380 } 1381 1382 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(const struct ena_admin_feature_offload_desc *p) 1383 { 1384 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT; 1385 } 1386 1387 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv4_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1388 { 1389 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV4_CSUM_FULL_MASK; 1390 } 1391 1392 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(const struct ena_admin_feature_offload_desc *p) 1393 { 1394 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT; 1395 } 1396 1397 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_part(struct ena_admin_feature_offload_desc *p, uint32_t val) 1398 { 1399 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_PART_MASK; 1400 } 1401 1402 static inline uint32_t get_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(const struct ena_admin_feature_offload_desc *p) 1403 { 1404 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT; 1405 } 1406 1407 static inline void set_ena_admin_feature_offload_desc_TX_L4_ipv6_csum_full(struct ena_admin_feature_offload_desc *p, uint32_t val) 1408 { 1409 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TX_L4_IPV6_CSUM_FULL_MASK; 1410 } 1411 1412 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv4(const struct ena_admin_feature_offload_desc *p) 1413 { 1414 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT; 1415 } 1416 1417 static inline void set_ena_admin_feature_offload_desc_tso_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1418 { 1419 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV4_MASK; 1420 } 1421 1422 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ipv6(const struct ena_admin_feature_offload_desc *p) 1423 { 1424 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT; 1425 } 1426 1427 static inline void set_ena_admin_feature_offload_desc_tso_ipv6(struct ena_admin_feature_offload_desc *p, uint32_t val) 1428 { 1429 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_IPV6_MASK; 1430 } 1431 1432 static inline uint32_t get_ena_admin_feature_offload_desc_tso_ecn(const struct ena_admin_feature_offload_desc *p) 1433 { 1434 return (p->tx & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT; 1435 } 1436 1437 static inline void set_ena_admin_feature_offload_desc_tso_ecn(struct ena_admin_feature_offload_desc *p, uint32_t val) 1438 { 1439 p->tx |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_TSO_ECN_MASK; 1440 } 1441 1442 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(const struct ena_admin_feature_offload_desc *p) 1443 { 1444 return p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1445 } 1446 1447 static inline void set_ena_admin_feature_offload_desc_RX_L3_csum_ipv4(struct ena_admin_feature_offload_desc *p, uint32_t val) 1448 { 1449 p->rx_supported |= val & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L3_CSUM_IPV4_MASK; 1450 } 1451 1452 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(const struct ena_admin_feature_offload_desc *p) 1453 { 1454 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT; 1455 } 1456 1457 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv4_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1458 { 1459 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV4_CSUM_MASK; 1460 } 1461 1462 static inline uint32_t get_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(const struct ena_admin_feature_offload_desc *p) 1463 { 1464 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT; 1465 } 1466 1467 static inline void set_ena_admin_feature_offload_desc_RX_L4_ipv6_csum(struct ena_admin_feature_offload_desc *p, uint32_t val) 1468 { 1469 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_L4_IPV6_CSUM_MASK; 1470 } 1471 1472 static inline uint32_t get_ena_admin_feature_offload_desc_RX_hash(const struct ena_admin_feature_offload_desc *p) 1473 { 1474 return (p->rx_supported & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK) >> ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT; 1475 } 1476 1477 static inline void set_ena_admin_feature_offload_desc_RX_hash(struct ena_admin_feature_offload_desc *p, uint32_t val) 1478 { 1479 p->rx_supported |= (val << ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_SHIFT) & ENA_ADMIN_FEATURE_OFFLOAD_DESC_RX_HASH_MASK; 1480 } 1481 1482 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_funcs(const struct ena_admin_feature_rss_flow_hash_function *p) 1483 { 1484 return p->supported_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1485 } 1486 1487 static inline void set_ena_admin_feature_rss_flow_hash_function_funcs(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1488 { 1489 p->supported_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_FUNCS_MASK; 1490 } 1491 1492 static inline uint32_t get_ena_admin_feature_rss_flow_hash_function_selected_func(const struct ena_admin_feature_rss_flow_hash_function *p) 1493 { 1494 return p->selected_func & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1495 } 1496 1497 static inline void set_ena_admin_feature_rss_flow_hash_function_selected_func(struct ena_admin_feature_rss_flow_hash_function *p, uint32_t val) 1498 { 1499 p->selected_func |= val & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_FUNCTION_SELECTED_FUNC_MASK; 1500 } 1501 1502 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1503 { 1504 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT; 1505 } 1506 1507 static inline void set_ena_admin_feature_rss_flow_hash_input_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1508 { 1509 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L3_SORT_MASK; 1510 } 1511 1512 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1513 { 1514 return (p->supported_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT; 1515 } 1516 1517 static inline void set_ena_admin_feature_rss_flow_hash_input_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1518 { 1519 p->supported_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_L4_SORT_MASK; 1520 } 1521 1522 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1523 { 1524 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT; 1525 } 1526 1527 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L3_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1528 { 1529 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L3_SORT_MASK; 1530 } 1531 1532 static inline uint16_t get_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(const struct ena_admin_feature_rss_flow_hash_input *p) 1533 { 1534 return (p->enabled_input_sort & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK) >> ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT; 1535 } 1536 1537 static inline void set_ena_admin_feature_rss_flow_hash_input_enable_L4_sort(struct ena_admin_feature_rss_flow_hash_input *p, uint16_t val) 1538 { 1539 p->enabled_input_sort |= (val << ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_SHIFT) & ENA_ADMIN_FEATURE_RSS_FLOW_HASH_INPUT_ENABLE_L4_SORT_MASK; 1540 } 1541 1542 static inline uint32_t get_ena_admin_host_info_major(const struct ena_admin_host_info *p) 1543 { 1544 return p->driver_version & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1545 } 1546 1547 static inline void set_ena_admin_host_info_major(struct ena_admin_host_info *p, uint32_t val) 1548 { 1549 p->driver_version |= val & ENA_ADMIN_HOST_INFO_MAJOR_MASK; 1550 } 1551 1552 static inline uint32_t get_ena_admin_host_info_minor(const struct ena_admin_host_info *p) 1553 { 1554 return (p->driver_version & ENA_ADMIN_HOST_INFO_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_MINOR_SHIFT; 1555 } 1556 1557 static inline void set_ena_admin_host_info_minor(struct ena_admin_host_info *p, uint32_t val) 1558 { 1559 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_MINOR_MASK; 1560 } 1561 1562 static inline uint32_t get_ena_admin_host_info_sub_minor(const struct ena_admin_host_info *p) 1563 { 1564 return (p->driver_version & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK) >> ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT; 1565 } 1566 1567 static inline void set_ena_admin_host_info_sub_minor(struct ena_admin_host_info *p, uint32_t val) 1568 { 1569 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_SUB_MINOR_SHIFT) & ENA_ADMIN_HOST_INFO_SUB_MINOR_MASK; 1570 } 1571 1572 static inline uint32_t get_ena_admin_host_info_module_type(const struct ena_admin_host_info *p) 1573 { 1574 return (p->driver_version & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK) >> ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT; 1575 } 1576 1577 static inline void set_ena_admin_host_info_module_type(struct ena_admin_host_info *p, uint32_t val) 1578 { 1579 p->driver_version |= (val << ENA_ADMIN_HOST_INFO_MODULE_TYPE_SHIFT) & ENA_ADMIN_HOST_INFO_MODULE_TYPE_MASK; 1580 } 1581 1582 static inline uint16_t get_ena_admin_host_info_function(const struct ena_admin_host_info *p) 1583 { 1584 return p->bdf & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; 1585 } 1586 1587 static inline void set_ena_admin_host_info_function(struct ena_admin_host_info *p, uint16_t val) 1588 { 1589 p->bdf |= val & ENA_ADMIN_HOST_INFO_FUNCTION_MASK; 1590 } 1591 1592 static inline uint16_t get_ena_admin_host_info_device(const struct ena_admin_host_info *p) 1593 { 1594 return (p->bdf & ENA_ADMIN_HOST_INFO_DEVICE_MASK) >> ENA_ADMIN_HOST_INFO_DEVICE_SHIFT; 1595 } 1596 1597 static inline void set_ena_admin_host_info_device(struct ena_admin_host_info *p, uint16_t val) 1598 { 1599 p->bdf |= (val << ENA_ADMIN_HOST_INFO_DEVICE_SHIFT) & ENA_ADMIN_HOST_INFO_DEVICE_MASK; 1600 } 1601 1602 static inline uint16_t get_ena_admin_host_info_bus(const struct ena_admin_host_info *p) 1603 { 1604 return (p->bdf & ENA_ADMIN_HOST_INFO_BUS_MASK) >> ENA_ADMIN_HOST_INFO_BUS_SHIFT; 1605 } 1606 1607 static inline void set_ena_admin_host_info_bus(struct ena_admin_host_info *p, uint16_t val) 1608 { 1609 p->bdf |= (val << ENA_ADMIN_HOST_INFO_BUS_SHIFT) & ENA_ADMIN_HOST_INFO_BUS_MASK; 1610 } 1611 1612 static inline uint32_t get_ena_admin_host_info_mutable_rss_table_size(const struct ena_admin_host_info *p) 1613 { 1614 return p->driver_supported_features & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK; 1615 } 1616 1617 static inline void set_ena_admin_host_info_mutable_rss_table_size(struct ena_admin_host_info *p, uint32_t val) 1618 { 1619 p->driver_supported_features |= val & ENA_ADMIN_HOST_INFO_MUTABLE_RSS_TABLE_SIZE_MASK; 1620 } 1621 1622 static inline uint32_t get_ena_admin_host_info_rx_offset(const struct ena_admin_host_info *p) 1623 { 1624 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK) >> ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT; 1625 } 1626 1627 static inline void set_ena_admin_host_info_rx_offset(struct ena_admin_host_info *p, uint32_t val) 1628 { 1629 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_RX_OFFSET_SHIFT) & ENA_ADMIN_HOST_INFO_RX_OFFSET_MASK; 1630 } 1631 1632 static inline uint32_t get_ena_admin_host_info_interrupt_moderation(const struct ena_admin_host_info *p) 1633 { 1634 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK) >> ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT; 1635 } 1636 1637 static inline void set_ena_admin_host_info_interrupt_moderation(struct ena_admin_host_info *p, uint32_t val) 1638 { 1639 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_SHIFT) & ENA_ADMIN_HOST_INFO_INTERRUPT_MODERATION_MASK; 1640 } 1641 1642 static inline uint32_t get_ena_admin_host_info_map_rx_buf_bidirectional(const struct ena_admin_host_info *p) 1643 { 1644 return (p->driver_supported_features & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK) >> ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT; 1645 } 1646 1647 static inline void set_ena_admin_host_info_map_rx_buf_bidirectional(struct ena_admin_host_info *p, uint32_t val) 1648 { 1649 p->driver_supported_features |= (val << ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_SHIFT) & ENA_ADMIN_HOST_INFO_MAP_RX_BUF_BIDIRECTIONAL_MASK; 1650 } 1651 1652 static inline uint8_t get_ena_admin_feature_rss_ind_table_one_entry_update(const struct ena_admin_feature_rss_ind_table *p) 1653 { 1654 return p->flags & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; 1655 } 1656 1657 static inline void set_ena_admin_feature_rss_ind_table_one_entry_update(struct ena_admin_feature_rss_ind_table *p, uint8_t val) 1658 { 1659 p->flags |= val & ENA_ADMIN_FEATURE_RSS_IND_TABLE_ONE_ENTRY_UPDATE_MASK; 1660 } 1661 1662 static inline uint8_t get_ena_admin_aenq_common_desc_phase(const struct ena_admin_aenq_common_desc *p) 1663 { 1664 return p->flags & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1665 } 1666 1667 static inline void set_ena_admin_aenq_common_desc_phase(struct ena_admin_aenq_common_desc *p, uint8_t val) 1668 { 1669 p->flags |= val & ENA_ADMIN_AENQ_COMMON_DESC_PHASE_MASK; 1670 } 1671 1672 static inline uint32_t get_ena_admin_aenq_link_change_desc_link_status(const struct ena_admin_aenq_link_change_desc *p) 1673 { 1674 return p->flags & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1675 } 1676 1677 static inline void set_ena_admin_aenq_link_change_desc_link_status(struct ena_admin_aenq_link_change_desc *p, uint32_t val) 1678 { 1679 p->flags |= val & ENA_ADMIN_AENQ_LINK_CHANGE_DESC_LINK_STATUS_MASK; 1680 } 1681 1682 #endif /* !defined(DEFS_LINUX_MAINLINE) */ 1683 #endif /* _ENA_ADMIN_H_ */ 1684