1 /* 2 * Copyright 2008-2012 Freescale Semiconductor Inc. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are met: 6 * * Redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer. 8 * * Redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution. 11 * * Neither the name of Freescale Semiconductor nor the 12 * names of its contributors may be used to endorse or promote products 13 * derived from this software without specific prior written permission. 14 * 15 * 16 * ALTERNATIVELY, this software may be distributed under the terms of the 17 * GNU General Public License ("GPL") as published by the Free Software 18 * Foundation, either version 2 of that License or (at your option) any 19 * later version. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY 22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY 25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 34 /**************************************************************************//** 35 @File e500v2_ext.h 36 37 @Description E500 external definitions prototypes 38 This file is not included by the E500 39 source file as it is an assembly file. It is used 40 only for prototypes exposure, for inclusion 41 by user and other modules. 42 *//***************************************************************************/ 43 44 #ifndef __E500V2_EXT_H 45 #define __E500V2_EXT_H 46 47 #include "std_ext.h" 48 49 50 /* Layer 1 Cache Manipulations 51 *============================== 52 * Should not be called directly by the user. 53 */ 54 void L1DCache_Invalidate (void); 55 void L1ICache_Invalidate(void); 56 void L1DCache_Enable(void); 57 void L1ICache_Enable(void); 58 void L1DCache_Disable(void); 59 void L1ICache_Disable(void); 60 void L1DCache_Flush(void); 61 void L1ICache_Flush(void); 62 uint32_t L1ICache_IsEnabled(void); 63 uint32_t L1DCache_IsEnabled(void); 64 /* 65 * 66 */ 67 uint32_t L1DCache_LineLock(uint32_t addr); 68 uint32_t L1ICache_LineLock(uint32_t addr); 69 void L1Cache_BroadCastEnable(void); 70 void L1Cache_BroadCastDisable(void); 71 72 73 #define CORE_DCacheEnable E500_DCacheEnable 74 #define CORE_ICacheEnable E500_ICacheEnable 75 #define CORE_DCacheDisable E500_DCacheDisable 76 #define CORE_ICacheDisable E500_ICacheDisable 77 #define CORE_GetId E500_GetId 78 #define CORE_TestAndSet E500_TestAndSet 79 #define CORE_MemoryBarrier E500_MemoryBarrier 80 #define CORE_InstructionSync E500_InstructionSync 81 82 #define CORE_SetDozeMode E500_SetDozeMode 83 #define CORE_SetNapMode E500_SetNapMode 84 #define CORE_SetSleepMode E500_SetSleepMode 85 #define CORE_SetJogMode E500_SetJogMode 86 #define CORE_SetDeepSleepMode E500_SetDeepSleepMode 87 88 #define CORE_RecoverDozeMode E500_RecoverDozeMode 89 #define CORE_RecoverNapMode E500_RecoverNapMode 90 #define CORE_RecoverSleepMode E500_RecoverSleepMode 91 #define CORE_RecoverJogMode E500_RecoverJogMode 92 93 void E500_SetDozeMode(void); 94 void E500_SetNapMode(void); 95 void E500_SetSleepMode(void); 96 void E500_SetJogMode(void); 97 t_Error E500_SetDeepSleepMode(uint32_t bptrAddress); 98 99 void E500_RecoverDozeMode(void); 100 void E500_RecoverNapMode(void); 101 void E500_RecoverSleepMode(void); 102 void E500_RecoverJogMode(void); 103 104 105 /**************************************************************************//** 106 @Group E500_id E500 Application Programming Interface 107 108 @Description E500 API functions, definitions and enums 109 110 @{ 111 *//***************************************************************************/ 112 113 /**************************************************************************//** 114 @Group E500_init_grp E500 Initialization Unit 115 116 @Description E500 initialization unit API functions, definitions and enums 117 118 @{ 119 *//***************************************************************************/ 120 121 122 /**************************************************************************//** 123 @Function E500_DCacheEnable 124 125 @Description Enables the data cache for memory pages that are 126 not cache inhibited. 127 128 @Return None. 129 *//***************************************************************************/ 130 void E500_DCacheEnable(void); 131 132 /**************************************************************************//** 133 @Function E500_ICacheEnable 134 135 @Description Enables the instruction cache for memory pages that are 136 not cache inhibited. 137 138 @Return None. 139 *//***************************************************************************/ 140 void E500_ICacheEnable(void); 141 142 /**************************************************************************//** 143 @Function E500_DCacheDisable 144 145 @Description Disables the data cache. 146 147 @Return None. 148 *//***************************************************************************/ 149 void E500_DCacheDisable(void); 150 151 /**************************************************************************//** 152 @Function E500_ICacheDisable 153 154 @Description Disables the instruction cache. 155 156 @Return None. 157 *//***************************************************************************/ 158 void E500_ICacheDisable(void); 159 160 /**************************************************************************//** 161 @Function E500_DCacheFlush 162 163 @Description Flushes the data cache 164 165 @Return None. 166 *//***************************************************************************/ 167 void E500_DCacheFlush(void); 168 169 /**************************************************************************//** 170 @Function E500_ICacheFlush 171 172 @Description Flushes the instruction cache. 173 174 @Return None. 175 *//***************************************************************************/ 176 void E500_ICacheFlush(void); 177 178 /**************************************************************************//** 179 @Function E500_DCacheSetStashId 180 181 @Description Set Stash Id for data cache 182 183 @Param[in] stashId the stash id to be set. 184 185 @Return None. 186 *//***************************************************************************/ 187 void E500_DCacheSetStashId(uint8_t stashId); 188 189 /**************************************************************************//** 190 @Description E500mc L2 Cache Operation Mode 191 *//***************************************************************************/ 192 typedef enum e_E500mcL2CacheMode 193 { 194 e_L2_CACHE_MODE_DATA_ONLY = 0x00000001, /**< Cache data only */ 195 e_L2_CACHE_MODE_INST_ONLY = 0x00000002, /**< Cache instructions only */ 196 e_L2_CACHE_MODE_DATA_AND_INST = 0x00000003 /**< Cache data and instructions */ 197 } e_E500mcL2CacheMode; 198 199 #if defined(CORE_E500MC) || defined(CORE_E5500) 200 /**************************************************************************//** 201 @Function E500_L2CacheEnable 202 203 @Description Enables the cache for memory pages that are not cache inhibited. 204 205 @param[in] mode - L2 cache mode: data only, instruction only or instruction and data. 206 207 @Return None. 208 209 @Cautions This routine must be call only ONCE for both caches. I.e. it is 210 not possible to call this routine for i-cache and than to call 211 again for d-cache; The second call will override the first one. 212 *//***************************************************************************/ 213 void E500_L2CacheEnable(e_E500mcL2CacheMode mode); 214 215 /**************************************************************************//** 216 @Function E500_L2CacheDisable 217 218 @Description Disables the cache (data instruction or both). 219 220 @Return None. 221 222 *//***************************************************************************/ 223 void E500_L2CacheDisable(void); 224 225 /**************************************************************************//** 226 @Function E500_L2CacheFlush 227 228 @Description Flushes the cache. 229 230 @Return None. 231 *//***************************************************************************/ 232 void E500_L2CacheFlush(void); 233 234 /**************************************************************************//** 235 @Function E500_L2SetStashId 236 237 @Description Set Stash Id 238 239 @Param[in] stashId the stash id to be set. 240 241 @Return None. 242 *//***************************************************************************/ 243 void E500_L2SetStashId(uint8_t stashId); 244 #endif /* defined(CORE_E500MC) || defined(CORE_E5500) */ 245 246 #ifdef CORE_E6500 247 /**************************************************************************//** 248 @Function E6500_L2CacheEnable 249 250 @Description Enables the cache for memory pages that are not cache inhibited. 251 252 @param[in] mode - L2 cache mode: support data & instruction only. 253 254 @Return None. 255 256 @Cautions This routine must be call only ONCE for both caches. I.e. it is 257 not possible to call this routine for i-cache and than to call 258 again for d-cache; The second call will override the first one. 259 *//***************************************************************************/ 260 void E6500_L2CacheEnable(uintptr_t clusterBase); 261 262 /**************************************************************************//** 263 @Function E6500_L2CacheDisable 264 265 @Description Disables the cache (data instruction or both). 266 267 @Return None. 268 269 *//***************************************************************************/ 270 void E6500_L2CacheDisable(uintptr_t clusterBase); 271 272 /**************************************************************************//** 273 @Function E6500_L2CacheFlush 274 275 @Description Flushes the cache. 276 277 @Return None. 278 *//***************************************************************************/ 279 void E6500_L2CacheFlush(uintptr_t clusterBase); 280 281 /**************************************************************************//** 282 @Function E6500_L2SetStashId 283 284 @Description Set Stash Id 285 286 @Param[in] stashId the stash id to be set. 287 288 @Return None. 289 *//***************************************************************************/ 290 void E6500_L2SetStashId(uintptr_t clusterBase, uint8_t stashId); 291 292 /**************************************************************************//** 293 @Function E6500_GetCcsrBase 294 295 @Description Obtain SoC CCSR base address 296 297 @Param[in] None. 298 299 @Return Physical CCSR base address. 300 *//***************************************************************************/ 301 physAddress_t E6500_GetCcsrBase(void); 302 #endif /* CORE_E6500 */ 303 304 /**************************************************************************//** 305 @Function E500_AddressBusStreamingEnable 306 307 @Description Enables address bus streaming on the CCB. 308 309 This setting, along with the ECM streaming configuration 310 parameters, enables address bus streaming on the CCB. 311 312 @Return None. 313 *//***************************************************************************/ 314 void E500_AddressBusStreamingEnable(void); 315 316 /**************************************************************************//** 317 @Function E500_AddressBusStreamingDisable 318 319 @Description Disables address bus streaming on the CCB. 320 321 @Return None. 322 *//***************************************************************************/ 323 void E500_AddressBusStreamingDisable(void); 324 325 /**************************************************************************//** 326 @Function E500_AddressBroadcastEnable 327 328 @Description Enables address broadcast. 329 330 The e500 broadcasts cache management instructions (dcbst, dcblc 331 (CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) 332 based on ABE. ABE must be set to allow management of external 333 L2 caches. 334 335 @Return None. 336 *//***************************************************************************/ 337 void E500_AddressBroadcastEnable(void); 338 339 /**************************************************************************//** 340 @Function E500_AddressBroadcastDisable 341 342 @Description Disables address broadcast. 343 344 The e500 broadcasts cache management instructions (dcbst, dcblc 345 (CT = 1), icblc (CT = 1), dcbf, dcbi, mbar, msync, tlbsync, icbi) 346 based on ABE. ABE must be set to allow management of external 347 L2 caches. 348 349 @Return None. 350 *//***************************************************************************/ 351 void E500_AddressBroadcastDisable(void); 352 353 /**************************************************************************//** 354 @Function E500_IsTaskletSupported 355 356 @Description Checks if tasklets are supported by the e500 interrupt handler. 357 358 @Retval TRUE - Tasklets are supported. 359 @Retval FALSE - Tasklets are not supported. 360 *//***************************************************************************/ 361 bool E500_IsTaskletSupported(void); 362 363 void E500_EnableTimeBase(void); 364 void E500_DisableTimeBase(void); 365 366 uint64_t E500_GetTimeBaseTime(void); 367 368 void E500_GenericIntrInit(void); 369 370 t_Error E500_SetIntr(int ppcIntrSrc, 371 void (* Isr)(t_Handle handle), 372 t_Handle handle); 373 374 t_Error E500_ClearIntr(int ppcIntrSrc); 375 376 /**************************************************************************//** 377 @Function E500_GenericIntrHandler 378 379 @Description This is the general e500 interrupt handler. 380 381 It is called by the main assembly interrupt handler 382 when an exception occurs and no other function has been 383 assigned to this exception. 384 385 @Param intrEntry - (In) The exception interrupt vector entry. 386 *//***************************************************************************/ 387 void E500_GenericIntrHandler(uint32_t intrEntry); 388 389 /**************************************************************************//** 390 @Function CriticalIntr 391 392 @Description This is the specific critical e500 interrupt handler. 393 394 It is called by the main assembly interrupt handler 395 when an critical interrupt. 396 397 @Param intrEntry - (In) The exception interrupt vector entry. 398 *//***************************************************************************/ 399 void CriticalIntr(uint32_t intrEntry); 400 401 402 /**************************************************************************//** 403 @Function E500_GetId 404 405 @Description Returns the core ID in the system. 406 407 @Return Core ID. 408 *//***************************************************************************/ 409 uint32_t E500_GetId(void); 410 411 /**************************************************************************//** 412 @Function E500_TestAndSet 413 414 @Description This routine tries to atomically test-and-set an integer 415 in memory to a non-zero value. 416 417 The memory will be set only if it is tested as zero, in which 418 case the routine returns the new non-zero value; otherwise the 419 routine returns zero. 420 421 @Param[in] p - pointer to a volatile int in memory, on which test-and-set 422 operation should be made. 423 424 @Retval Zero - Operation failed - memory was already set. 425 @Retval Non-zero - Operation succeeded - memory has been set. 426 *//***************************************************************************/ 427 int E500_TestAndSet(volatile int *p); 428 429 /**************************************************************************//** 430 @Function E500_MemoryBarrier 431 432 @Description This routine will cause the core to stop executing any commands 433 until all previous memory read/write commands are completely out 434 of the core's pipeline. 435 436 @Return None. 437 *//***************************************************************************/ 438 static __inline__ void E500_MemoryBarrier(void) 439 { 440 #ifndef CORE_E500V2 441 __asm__ ("mbar 1"); 442 #else /* CORE_E500V2 */ 443 /**** ERRATA WORK AROUND START ****/ 444 /* ERRATA num: CPU1 */ 445 /* Description: "mbar MO = 1" instruction fails to order caching-inhibited 446 guarded loads and stores. */ 447 448 /* "msync" instruction is used instead */ 449 450 __asm__ ("msync"); 451 452 /**** ERRATA WORK AROUND END ****/ 453 #endif /* CORE_E500V2 */ 454 } 455 456 /**************************************************************************//** 457 @Function E500_InstructionSync 458 459 @Description This routine will cause the core to wait for previous instructions 460 (including any interrupts they generate) to complete before the 461 synchronization command executes, which purges all instructions 462 from the processor's pipeline and refetches the next instruction. 463 464 @Return None. 465 *//***************************************************************************/ 466 static __inline__ void E500_InstructionSync(void) 467 { 468 __asm__ ("isync"); 469 } 470 471 472 /** @} */ /* end of E500_init_grp group */ 473 /** @} */ /* end of E500_grp group */ 474 475 476 #endif /* __E500V2_EXT_H */ 477