1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/mbuf.h> 42 #include <sys/rman.h> 43 #include <sys/module.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_media.h> 57 #include <net/if_types.h> 58 #include <net/if_vlan_var.h> 59 60 #include <netinet/in.h> 61 #include <netinet/in_systm.h> 62 #include <netinet/ip.h> 63 #include <netinet/tcp.h> 64 65 #include <dev/mii/mii.h> 66 #include <dev/mii/miivar.h> 67 68 #include <dev/pci/pcireg.h> 69 #include <dev/pci/pcivar.h> 70 71 #include <machine/bus.h> 72 #include <machine/in_cksum.h> 73 74 #include <dev/age/if_agereg.h> 75 #include <dev/age/if_agevar.h> 76 77 /* "device miibus" required. See GENERIC if you get errors here. */ 78 #include "miibus_if.h" 79 80 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(age, pci, 1, 1, 1); 83 MODULE_DEPEND(age, ether, 1, 1, 1); 84 MODULE_DEPEND(age, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static struct age_dev { 96 uint16_t age_vendorid; 97 uint16_t age_deviceid; 98 const char *age_name; 99 } age_devs[] = { 100 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 101 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 102 }; 103 104 static int age_miibus_readreg(device_t, int, int); 105 static int age_miibus_writereg(device_t, int, int, int); 106 static void age_miibus_statchg(device_t); 107 static void age_mediastatus(if_t, struct ifmediareq *); 108 static int age_mediachange(if_t); 109 static int age_probe(device_t); 110 static void age_get_macaddr(struct age_softc *); 111 static void age_phy_reset(struct age_softc *); 112 static int age_attach(device_t); 113 static int age_detach(device_t); 114 static void age_sysctl_node(struct age_softc *); 115 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 116 static int age_check_boundary(struct age_softc *); 117 static int age_dma_alloc(struct age_softc *); 118 static void age_dma_free(struct age_softc *); 119 static int age_shutdown(device_t); 120 static void age_setwol(struct age_softc *); 121 static int age_suspend(device_t); 122 static int age_resume(device_t); 123 static int age_encap(struct age_softc *, struct mbuf **); 124 static void age_start(if_t); 125 static void age_start_locked(if_t); 126 static void age_watchdog(struct age_softc *); 127 static int age_ioctl(if_t, u_long, caddr_t); 128 static void age_mac_config(struct age_softc *); 129 static void age_link_task(void *, int); 130 static void age_stats_update(struct age_softc *); 131 static int age_intr(void *); 132 static void age_int_task(void *, int); 133 static void age_txintr(struct age_softc *, int); 134 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 135 static int age_rxintr(struct age_softc *, int, int); 136 static void age_tick(void *); 137 static void age_reset(struct age_softc *); 138 static void age_init(void *); 139 static void age_init_locked(struct age_softc *); 140 static void age_stop(struct age_softc *); 141 static void age_stop_txmac(struct age_softc *); 142 static void age_stop_rxmac(struct age_softc *); 143 static void age_init_tx_ring(struct age_softc *); 144 static int age_init_rx_ring(struct age_softc *); 145 static void age_init_rr_ring(struct age_softc *); 146 static void age_init_cmb_block(struct age_softc *); 147 static void age_init_smb_block(struct age_softc *); 148 #ifndef __NO_STRICT_ALIGNMENT 149 static struct mbuf *age_fixup_rx(if_t, struct mbuf *); 150 #endif 151 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 152 static void age_rxvlan(struct age_softc *); 153 static void age_rxfilter(struct age_softc *); 154 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 155 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 156 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 157 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 158 159 static device_method_t age_methods[] = { 160 /* Device interface. */ 161 DEVMETHOD(device_probe, age_probe), 162 DEVMETHOD(device_attach, age_attach), 163 DEVMETHOD(device_detach, age_detach), 164 DEVMETHOD(device_shutdown, age_shutdown), 165 DEVMETHOD(device_suspend, age_suspend), 166 DEVMETHOD(device_resume, age_resume), 167 168 /* MII interface. */ 169 DEVMETHOD(miibus_readreg, age_miibus_readreg), 170 DEVMETHOD(miibus_writereg, age_miibus_writereg), 171 DEVMETHOD(miibus_statchg, age_miibus_statchg), 172 { NULL, NULL } 173 }; 174 175 static driver_t age_driver = { 176 "age", 177 age_methods, 178 sizeof(struct age_softc) 179 }; 180 181 DRIVER_MODULE(age, pci, age_driver, 0, 0); 182 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, age, age_devs, 183 nitems(age_devs)); 184 DRIVER_MODULE(miibus, age, miibus_driver, 0, 0); 185 186 static struct resource_spec age_res_spec_mem[] = { 187 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 188 { -1, 0, 0 } 189 }; 190 191 static struct resource_spec age_irq_spec_legacy[] = { 192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 193 { -1, 0, 0 } 194 }; 195 196 static struct resource_spec age_irq_spec_msi[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static struct resource_spec age_irq_spec_msix[] = { 202 { SYS_RES_IRQ, 1, RF_ACTIVE }, 203 { -1, 0, 0 } 204 }; 205 206 /* 207 * Read a PHY register on the MII of the L1. 208 */ 209 static int 210 age_miibus_readreg(device_t dev, int phy, int reg) 211 { 212 struct age_softc *sc; 213 uint32_t v; 214 int i; 215 216 sc = device_get_softc(dev); 217 218 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 219 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 220 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 221 DELAY(1); 222 v = CSR_READ_4(sc, AGE_MDIO); 223 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 224 break; 225 } 226 227 if (i == 0) { 228 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 229 return (0); 230 } 231 232 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 233 } 234 235 /* 236 * Write a PHY register on the MII of the L1. 237 */ 238 static int 239 age_miibus_writereg(device_t dev, int phy, int reg, int val) 240 { 241 struct age_softc *sc; 242 uint32_t v; 243 int i; 244 245 sc = device_get_softc(dev); 246 247 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 248 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 249 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 250 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 251 DELAY(1); 252 v = CSR_READ_4(sc, AGE_MDIO); 253 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 254 break; 255 } 256 257 if (i == 0) 258 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 259 260 return (0); 261 } 262 263 /* 264 * Callback from MII layer when media changes. 265 */ 266 static void 267 age_miibus_statchg(device_t dev) 268 { 269 struct age_softc *sc; 270 271 sc = device_get_softc(dev); 272 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 273 } 274 275 /* 276 * Get the current interface media status. 277 */ 278 static void 279 age_mediastatus(if_t ifp, struct ifmediareq *ifmr) 280 { 281 struct age_softc *sc; 282 struct mii_data *mii; 283 284 sc = if_getsoftc(ifp); 285 AGE_LOCK(sc); 286 mii = device_get_softc(sc->age_miibus); 287 288 mii_pollstat(mii); 289 ifmr->ifm_status = mii->mii_media_status; 290 ifmr->ifm_active = mii->mii_media_active; 291 AGE_UNLOCK(sc); 292 } 293 294 /* 295 * Set hardware to newly-selected media. 296 */ 297 static int 298 age_mediachange(if_t ifp) 299 { 300 struct age_softc *sc; 301 struct mii_data *mii; 302 struct mii_softc *miisc; 303 int error; 304 305 sc = if_getsoftc(ifp); 306 AGE_LOCK(sc); 307 mii = device_get_softc(sc->age_miibus); 308 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 309 PHY_RESET(miisc); 310 error = mii_mediachg(mii); 311 AGE_UNLOCK(sc); 312 313 return (error); 314 } 315 316 static int 317 age_probe(device_t dev) 318 { 319 struct age_dev *sp; 320 int i; 321 uint16_t vendor, devid; 322 323 vendor = pci_get_vendor(dev); 324 devid = pci_get_device(dev); 325 sp = age_devs; 326 for (i = 0; i < nitems(age_devs); i++, sp++) { 327 if (vendor == sp->age_vendorid && 328 devid == sp->age_deviceid) { 329 device_set_desc(dev, sp->age_name); 330 return (BUS_PROBE_DEFAULT); 331 } 332 } 333 334 return (ENXIO); 335 } 336 337 static void 338 age_get_macaddr(struct age_softc *sc) 339 { 340 uint32_t ea[2], reg; 341 int i, vpdc; 342 343 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 344 if ((reg & SPI_VPD_ENB) != 0) { 345 /* Get VPD stored in TWSI EEPROM. */ 346 reg &= ~SPI_VPD_ENB; 347 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 348 } 349 350 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 351 /* 352 * PCI VPD capability found, let TWSI reload EEPROM. 353 * This will set ethernet address of controller. 354 */ 355 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 356 TWSI_CTRL_SW_LD_START); 357 for (i = 100; i > 0; i--) { 358 DELAY(1000); 359 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 360 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 361 break; 362 } 363 if (i == 0) 364 device_printf(sc->age_dev, 365 "reloading EEPROM timeout!\n"); 366 } else { 367 if (bootverbose) 368 device_printf(sc->age_dev, 369 "PCI VPD capability not found!\n"); 370 } 371 372 ea[0] = CSR_READ_4(sc, AGE_PAR0); 373 ea[1] = CSR_READ_4(sc, AGE_PAR1); 374 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 375 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 376 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 377 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 378 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 379 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 380 } 381 382 static void 383 age_phy_reset(struct age_softc *sc) 384 { 385 uint16_t reg, pn; 386 int i, linkup; 387 388 /* Reset PHY. */ 389 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 390 DELAY(2000); 391 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 392 DELAY(2000); 393 394 #define ATPHY_DBG_ADDR 0x1D 395 #define ATPHY_DBG_DATA 0x1E 396 #define ATPHY_CDTC 0x16 397 #define PHY_CDTC_ENB 0x0001 398 #define PHY_CDTC_POFF 8 399 #define ATPHY_CDTS 0x1C 400 #define PHY_CDTS_STAT_OK 0x0000 401 #define PHY_CDTS_STAT_SHORT 0x0100 402 #define PHY_CDTS_STAT_OPEN 0x0200 403 #define PHY_CDTS_STAT_INVAL 0x0300 404 #define PHY_CDTS_STAT_MASK 0x0300 405 406 /* Check power saving mode. Magic from Linux. */ 407 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 408 for (linkup = 0, pn = 0; pn < 4; pn++) { 409 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 410 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 411 for (i = 200; i > 0; i--) { 412 DELAY(1000); 413 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 414 ATPHY_CDTC); 415 if ((reg & PHY_CDTC_ENB) == 0) 416 break; 417 } 418 DELAY(1000); 419 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 420 ATPHY_CDTS); 421 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 422 linkup++; 423 break; 424 } 425 } 426 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 427 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 428 if (linkup == 0) { 429 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 430 ATPHY_DBG_ADDR, 0); 431 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 432 ATPHY_DBG_DATA, 0x124E); 433 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 434 ATPHY_DBG_ADDR, 1); 435 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 436 ATPHY_DBG_DATA); 437 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 438 ATPHY_DBG_DATA, reg | 0x03); 439 /* XXX */ 440 DELAY(1500 * 1000); 441 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 442 ATPHY_DBG_ADDR, 0); 443 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 444 ATPHY_DBG_DATA, 0x024E); 445 } 446 447 #undef ATPHY_DBG_ADDR 448 #undef ATPHY_DBG_DATA 449 #undef ATPHY_CDTC 450 #undef PHY_CDTC_ENB 451 #undef PHY_CDTC_POFF 452 #undef ATPHY_CDTS 453 #undef PHY_CDTS_STAT_OK 454 #undef PHY_CDTS_STAT_SHORT 455 #undef PHY_CDTS_STAT_OPEN 456 #undef PHY_CDTS_STAT_INVAL 457 #undef PHY_CDTS_STAT_MASK 458 } 459 460 static int 461 age_attach(device_t dev) 462 { 463 struct age_softc *sc; 464 if_t ifp; 465 uint16_t burst; 466 int error, i, msic, msixc, pmc; 467 468 error = 0; 469 sc = device_get_softc(dev); 470 sc->age_dev = dev; 471 472 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 473 MTX_DEF); 474 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 475 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 476 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 477 478 /* Map the device. */ 479 pci_enable_busmaster(dev); 480 sc->age_res_spec = age_res_spec_mem; 481 sc->age_irq_spec = age_irq_spec_legacy; 482 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 483 if (error != 0) { 484 device_printf(dev, "cannot allocate memory resources.\n"); 485 goto fail; 486 } 487 488 /* Set PHY address. */ 489 sc->age_phyaddr = AGE_PHY_ADDR; 490 491 /* Reset PHY. */ 492 age_phy_reset(sc); 493 494 /* Reset the ethernet controller. */ 495 age_reset(sc); 496 497 /* Get PCI and chip id/revision. */ 498 sc->age_rev = pci_get_revid(dev); 499 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 500 MASTER_CHIP_REV_SHIFT; 501 if (bootverbose) { 502 device_printf(dev, "PCI device revision : 0x%04x\n", 503 sc->age_rev); 504 device_printf(dev, "Chip id/revision : 0x%04x\n", 505 sc->age_chip_rev); 506 } 507 508 /* 509 * XXX 510 * Unintialized hardware returns an invalid chip id/revision 511 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 512 * unplugged cable results in putting hardware into automatic 513 * power down mode which in turn returns invalld chip revision. 514 */ 515 if (sc->age_chip_rev == 0xFFFF) { 516 device_printf(dev,"invalid chip revision : 0x%04x -- " 517 "not initialized?\n", sc->age_chip_rev); 518 error = ENXIO; 519 goto fail; 520 } 521 522 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 523 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 524 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 525 526 /* Allocate IRQ resources. */ 527 msixc = pci_msix_count(dev); 528 msic = pci_msi_count(dev); 529 if (bootverbose) { 530 device_printf(dev, "MSIX count : %d\n", msixc); 531 device_printf(dev, "MSI count : %d\n", msic); 532 } 533 534 /* Prefer MSIX over MSI. */ 535 if (msix_disable == 0 || msi_disable == 0) { 536 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 537 pci_alloc_msix(dev, &msixc) == 0) { 538 if (msic == AGE_MSIX_MESSAGES) { 539 device_printf(dev, "Using %d MSIX messages.\n", 540 msixc); 541 sc->age_flags |= AGE_FLAG_MSIX; 542 sc->age_irq_spec = age_irq_spec_msix; 543 } else 544 pci_release_msi(dev); 545 } 546 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 547 msic == AGE_MSI_MESSAGES && 548 pci_alloc_msi(dev, &msic) == 0) { 549 if (msic == AGE_MSI_MESSAGES) { 550 device_printf(dev, "Using %d MSI messages.\n", 551 msic); 552 sc->age_flags |= AGE_FLAG_MSI; 553 sc->age_irq_spec = age_irq_spec_msi; 554 } else 555 pci_release_msi(dev); 556 } 557 } 558 559 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 560 if (error != 0) { 561 device_printf(dev, "cannot allocate IRQ resources.\n"); 562 goto fail; 563 } 564 565 /* Get DMA parameters from PCIe device control register. */ 566 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 567 sc->age_flags |= AGE_FLAG_PCIE; 568 burst = pci_read_config(dev, i + 0x08, 2); 569 /* Max read request size. */ 570 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 571 DMA_CFG_RD_BURST_SHIFT; 572 /* Max payload size. */ 573 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 574 DMA_CFG_WR_BURST_SHIFT; 575 if (bootverbose) { 576 device_printf(dev, "Read request size : %d bytes.\n", 577 128 << ((burst >> 12) & 0x07)); 578 device_printf(dev, "TLP payload size : %d bytes.\n", 579 128 << ((burst >> 5) & 0x07)); 580 } 581 } else { 582 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 583 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 584 } 585 586 /* Create device sysctl node. */ 587 age_sysctl_node(sc); 588 589 if ((error = age_dma_alloc(sc)) != 0) 590 goto fail; 591 592 /* Load station address. */ 593 age_get_macaddr(sc); 594 595 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 596 if (ifp == NULL) { 597 device_printf(dev, "cannot allocate ifnet structure.\n"); 598 error = ENXIO; 599 goto fail; 600 } 601 602 if_setsoftc(ifp, sc); 603 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 604 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 605 if_setioctlfn(ifp, age_ioctl); 606 if_setstartfn(ifp, age_start); 607 if_setinitfn(ifp, age_init); 608 if_setsendqlen(ifp, AGE_TX_RING_CNT - 1); 609 if_setsendqready(ifp); 610 if_setcapabilities(ifp, IFCAP_HWCSUM | IFCAP_TSO4); 611 if_sethwassist(ifp, AGE_CSUM_FEATURES | CSUM_TSO); 612 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 613 sc->age_flags |= AGE_FLAG_PMCAP; 614 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 615 } 616 if_setcapenable(ifp, if_getcapabilities(ifp)); 617 618 /* Set up MII bus. */ 619 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 620 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 621 0); 622 if (error != 0) { 623 device_printf(dev, "attaching PHYs failed\n"); 624 goto fail; 625 } 626 627 ether_ifattach(ifp, sc->age_eaddr); 628 629 /* VLAN capability setup. */ 630 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 631 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 632 if_setcapenable(ifp, if_getcapabilities(ifp)); 633 634 /* Tell the upper layer(s) we support long frames. */ 635 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 636 637 /* Create local taskq. */ 638 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 639 taskqueue_thread_enqueue, &sc->age_tq); 640 if (sc->age_tq == NULL) { 641 device_printf(dev, "could not create taskqueue.\n"); 642 ether_ifdetach(ifp); 643 error = ENXIO; 644 goto fail; 645 } 646 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 647 device_get_nameunit(sc->age_dev)); 648 649 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 650 msic = AGE_MSIX_MESSAGES; 651 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 652 msic = AGE_MSI_MESSAGES; 653 else 654 msic = 1; 655 for (i = 0; i < msic; i++) { 656 error = bus_setup_intr(dev, sc->age_irq[i], 657 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 658 &sc->age_intrhand[i]); 659 if (error != 0) 660 break; 661 } 662 if (error != 0) { 663 device_printf(dev, "could not set up interrupt handler.\n"); 664 taskqueue_free(sc->age_tq); 665 sc->age_tq = NULL; 666 ether_ifdetach(ifp); 667 goto fail; 668 } 669 670 fail: 671 if (error != 0) 672 age_detach(dev); 673 674 return (error); 675 } 676 677 static int 678 age_detach(device_t dev) 679 { 680 struct age_softc *sc; 681 if_t ifp; 682 int i, msic; 683 684 sc = device_get_softc(dev); 685 686 ifp = sc->age_ifp; 687 if (device_is_attached(dev)) { 688 AGE_LOCK(sc); 689 sc->age_flags |= AGE_FLAG_DETACH; 690 age_stop(sc); 691 AGE_UNLOCK(sc); 692 callout_drain(&sc->age_tick_ch); 693 taskqueue_drain(sc->age_tq, &sc->age_int_task); 694 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 695 ether_ifdetach(ifp); 696 } 697 698 if (sc->age_tq != NULL) { 699 taskqueue_drain(sc->age_tq, &sc->age_int_task); 700 taskqueue_free(sc->age_tq); 701 sc->age_tq = NULL; 702 } 703 704 if (sc->age_miibus != NULL) { 705 device_delete_child(dev, sc->age_miibus); 706 sc->age_miibus = NULL; 707 } 708 bus_generic_detach(dev); 709 age_dma_free(sc); 710 711 if (ifp != NULL) { 712 if_free(ifp); 713 sc->age_ifp = NULL; 714 } 715 716 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 717 msic = AGE_MSIX_MESSAGES; 718 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 719 msic = AGE_MSI_MESSAGES; 720 else 721 msic = 1; 722 for (i = 0; i < msic; i++) { 723 if (sc->age_intrhand[i] != NULL) { 724 bus_teardown_intr(dev, sc->age_irq[i], 725 sc->age_intrhand[i]); 726 sc->age_intrhand[i] = NULL; 727 } 728 } 729 730 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 731 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 732 pci_release_msi(dev); 733 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 734 mtx_destroy(&sc->age_mtx); 735 736 return (0); 737 } 738 739 static void 740 age_sysctl_node(struct age_softc *sc) 741 { 742 int error; 743 744 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 745 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 746 "stats", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 747 sc, 0, sysctl_age_stats, "I", "Statistics"); 748 749 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 750 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 751 "int_mod", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 752 &sc->age_int_mod, 0, sysctl_hw_age_int_mod, "I", 753 "age interrupt moderation"); 754 755 /* Pull in device tunables. */ 756 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 757 error = resource_int_value(device_get_name(sc->age_dev), 758 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 759 if (error == 0) { 760 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 761 sc->age_int_mod > AGE_IM_TIMER_MAX) { 762 device_printf(sc->age_dev, 763 "int_mod value out of range; using default: %d\n", 764 AGE_IM_TIMER_DEFAULT); 765 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 766 } 767 } 768 769 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 770 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 771 "process_limit", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 772 &sc->age_process_limit, 0, sysctl_hw_age_proc_limit, "I", 773 "max number of Rx events to process"); 774 775 /* Pull in device tunables. */ 776 sc->age_process_limit = AGE_PROC_DEFAULT; 777 error = resource_int_value(device_get_name(sc->age_dev), 778 device_get_unit(sc->age_dev), "process_limit", 779 &sc->age_process_limit); 780 if (error == 0) { 781 if (sc->age_process_limit < AGE_PROC_MIN || 782 sc->age_process_limit > AGE_PROC_MAX) { 783 device_printf(sc->age_dev, 784 "process_limit value out of range; " 785 "using default: %d\n", AGE_PROC_DEFAULT); 786 sc->age_process_limit = AGE_PROC_DEFAULT; 787 } 788 } 789 } 790 791 struct age_dmamap_arg { 792 bus_addr_t age_busaddr; 793 }; 794 795 static void 796 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 797 { 798 struct age_dmamap_arg *ctx; 799 800 if (error != 0) 801 return; 802 803 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 804 805 ctx = (struct age_dmamap_arg *)arg; 806 ctx->age_busaddr = segs[0].ds_addr; 807 } 808 809 /* 810 * Attansic L1 controller have single register to specify high 811 * address part of DMA blocks. So all descriptor structures and 812 * DMA memory blocks should have the same high address of given 813 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 814 */ 815 static int 816 age_check_boundary(struct age_softc *sc) 817 { 818 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 819 bus_addr_t cmb_block_end, smb_block_end; 820 821 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 822 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 823 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 824 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 825 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 826 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 827 828 if ((AGE_ADDR_HI(tx_ring_end) != 829 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 830 (AGE_ADDR_HI(rx_ring_end) != 831 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 832 (AGE_ADDR_HI(rr_ring_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 834 (AGE_ADDR_HI(cmb_block_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 836 (AGE_ADDR_HI(smb_block_end) != 837 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 838 return (EFBIG); 839 840 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 841 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 842 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 843 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 844 return (EFBIG); 845 846 return (0); 847 } 848 849 static int 850 age_dma_alloc(struct age_softc *sc) 851 { 852 struct age_txdesc *txd; 853 struct age_rxdesc *rxd; 854 bus_addr_t lowaddr; 855 struct age_dmamap_arg ctx; 856 int error, i; 857 858 lowaddr = BUS_SPACE_MAXADDR; 859 860 again: 861 /* Create parent ring/DMA block tag. */ 862 error = bus_dma_tag_create( 863 bus_get_dma_tag(sc->age_dev), /* parent */ 864 1, 0, /* alignment, boundary */ 865 lowaddr, /* lowaddr */ 866 BUS_SPACE_MAXADDR, /* highaddr */ 867 NULL, NULL, /* filter, filterarg */ 868 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 869 0, /* nsegments */ 870 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 871 0, /* flags */ 872 NULL, NULL, /* lockfunc, lockarg */ 873 &sc->age_cdata.age_parent_tag); 874 if (error != 0) { 875 device_printf(sc->age_dev, 876 "could not create parent DMA tag.\n"); 877 goto fail; 878 } 879 880 /* Create tag for Tx ring. */ 881 error = bus_dma_tag_create( 882 sc->age_cdata.age_parent_tag, /* parent */ 883 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 884 BUS_SPACE_MAXADDR, /* lowaddr */ 885 BUS_SPACE_MAXADDR, /* highaddr */ 886 NULL, NULL, /* filter, filterarg */ 887 AGE_TX_RING_SZ, /* maxsize */ 888 1, /* nsegments */ 889 AGE_TX_RING_SZ, /* maxsegsize */ 890 0, /* flags */ 891 NULL, NULL, /* lockfunc, lockarg */ 892 &sc->age_cdata.age_tx_ring_tag); 893 if (error != 0) { 894 device_printf(sc->age_dev, 895 "could not create Tx ring DMA tag.\n"); 896 goto fail; 897 } 898 899 /* Create tag for Rx ring. */ 900 error = bus_dma_tag_create( 901 sc->age_cdata.age_parent_tag, /* parent */ 902 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 903 BUS_SPACE_MAXADDR, /* lowaddr */ 904 BUS_SPACE_MAXADDR, /* highaddr */ 905 NULL, NULL, /* filter, filterarg */ 906 AGE_RX_RING_SZ, /* maxsize */ 907 1, /* nsegments */ 908 AGE_RX_RING_SZ, /* maxsegsize */ 909 0, /* flags */ 910 NULL, NULL, /* lockfunc, lockarg */ 911 &sc->age_cdata.age_rx_ring_tag); 912 if (error != 0) { 913 device_printf(sc->age_dev, 914 "could not create Rx ring DMA tag.\n"); 915 goto fail; 916 } 917 918 /* Create tag for Rx return ring. */ 919 error = bus_dma_tag_create( 920 sc->age_cdata.age_parent_tag, /* parent */ 921 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 922 BUS_SPACE_MAXADDR, /* lowaddr */ 923 BUS_SPACE_MAXADDR, /* highaddr */ 924 NULL, NULL, /* filter, filterarg */ 925 AGE_RR_RING_SZ, /* maxsize */ 926 1, /* nsegments */ 927 AGE_RR_RING_SZ, /* maxsegsize */ 928 0, /* flags */ 929 NULL, NULL, /* lockfunc, lockarg */ 930 &sc->age_cdata.age_rr_ring_tag); 931 if (error != 0) { 932 device_printf(sc->age_dev, 933 "could not create Rx return ring DMA tag.\n"); 934 goto fail; 935 } 936 937 /* Create tag for coalesing message block. */ 938 error = bus_dma_tag_create( 939 sc->age_cdata.age_parent_tag, /* parent */ 940 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 941 BUS_SPACE_MAXADDR, /* lowaddr */ 942 BUS_SPACE_MAXADDR, /* highaddr */ 943 NULL, NULL, /* filter, filterarg */ 944 AGE_CMB_BLOCK_SZ, /* maxsize */ 945 1, /* nsegments */ 946 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 947 0, /* flags */ 948 NULL, NULL, /* lockfunc, lockarg */ 949 &sc->age_cdata.age_cmb_block_tag); 950 if (error != 0) { 951 device_printf(sc->age_dev, 952 "could not create CMB DMA tag.\n"); 953 goto fail; 954 } 955 956 /* Create tag for statistics message block. */ 957 error = bus_dma_tag_create( 958 sc->age_cdata.age_parent_tag, /* parent */ 959 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 960 BUS_SPACE_MAXADDR, /* lowaddr */ 961 BUS_SPACE_MAXADDR, /* highaddr */ 962 NULL, NULL, /* filter, filterarg */ 963 AGE_SMB_BLOCK_SZ, /* maxsize */ 964 1, /* nsegments */ 965 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 966 0, /* flags */ 967 NULL, NULL, /* lockfunc, lockarg */ 968 &sc->age_cdata.age_smb_block_tag); 969 if (error != 0) { 970 device_printf(sc->age_dev, 971 "could not create SMB DMA tag.\n"); 972 goto fail; 973 } 974 975 /* Allocate DMA'able memory and load the DMA map. */ 976 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 977 (void **)&sc->age_rdata.age_tx_ring, 978 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 979 &sc->age_cdata.age_tx_ring_map); 980 if (error != 0) { 981 device_printf(sc->age_dev, 982 "could not allocate DMA'able memory for Tx ring.\n"); 983 goto fail; 984 } 985 ctx.age_busaddr = 0; 986 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 987 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 988 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 989 if (error != 0 || ctx.age_busaddr == 0) { 990 device_printf(sc->age_dev, 991 "could not load DMA'able memory for Tx ring.\n"); 992 goto fail; 993 } 994 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 995 /* Rx ring */ 996 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 997 (void **)&sc->age_rdata.age_rx_ring, 998 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 999 &sc->age_cdata.age_rx_ring_map); 1000 if (error != 0) { 1001 device_printf(sc->age_dev, 1002 "could not allocate DMA'able memory for Rx ring.\n"); 1003 goto fail; 1004 } 1005 ctx.age_busaddr = 0; 1006 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1007 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1008 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1009 if (error != 0 || ctx.age_busaddr == 0) { 1010 device_printf(sc->age_dev, 1011 "could not load DMA'able memory for Rx ring.\n"); 1012 goto fail; 1013 } 1014 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1015 /* Rx return ring */ 1016 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1017 (void **)&sc->age_rdata.age_rr_ring, 1018 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1019 &sc->age_cdata.age_rr_ring_map); 1020 if (error != 0) { 1021 device_printf(sc->age_dev, 1022 "could not allocate DMA'able memory for Rx return ring.\n"); 1023 goto fail; 1024 } 1025 ctx.age_busaddr = 0; 1026 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1027 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1028 AGE_RR_RING_SZ, age_dmamap_cb, 1029 &ctx, 0); 1030 if (error != 0 || ctx.age_busaddr == 0) { 1031 device_printf(sc->age_dev, 1032 "could not load DMA'able memory for Rx return ring.\n"); 1033 goto fail; 1034 } 1035 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1036 /* CMB block */ 1037 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1038 (void **)&sc->age_rdata.age_cmb_block, 1039 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1040 &sc->age_cdata.age_cmb_block_map); 1041 if (error != 0) { 1042 device_printf(sc->age_dev, 1043 "could not allocate DMA'able memory for CMB block.\n"); 1044 goto fail; 1045 } 1046 ctx.age_busaddr = 0; 1047 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1048 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1049 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1050 if (error != 0 || ctx.age_busaddr == 0) { 1051 device_printf(sc->age_dev, 1052 "could not load DMA'able memory for CMB block.\n"); 1053 goto fail; 1054 } 1055 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1056 /* SMB block */ 1057 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1058 (void **)&sc->age_rdata.age_smb_block, 1059 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1060 &sc->age_cdata.age_smb_block_map); 1061 if (error != 0) { 1062 device_printf(sc->age_dev, 1063 "could not allocate DMA'able memory for SMB block.\n"); 1064 goto fail; 1065 } 1066 ctx.age_busaddr = 0; 1067 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1068 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1069 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1070 if (error != 0 || ctx.age_busaddr == 0) { 1071 device_printf(sc->age_dev, 1072 "could not load DMA'able memory for SMB block.\n"); 1073 goto fail; 1074 } 1075 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1076 1077 /* 1078 * All ring buffer and DMA blocks should have the same 1079 * high address part of 64bit DMA address space. 1080 */ 1081 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1082 (error = age_check_boundary(sc)) != 0) { 1083 device_printf(sc->age_dev, "4GB boundary crossed, " 1084 "switching to 32bit DMA addressing mode.\n"); 1085 age_dma_free(sc); 1086 /* Limit DMA address space to 32bit and try again. */ 1087 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1088 goto again; 1089 } 1090 1091 /* 1092 * Create Tx/Rx buffer parent tag. 1093 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1094 * so it needs separate parent DMA tag. 1095 * XXX 1096 * It seems enabling 64bit DMA causes data corruption. Limit 1097 * DMA address space to 32bit. 1098 */ 1099 error = bus_dma_tag_create( 1100 bus_get_dma_tag(sc->age_dev), /* parent */ 1101 1, 0, /* alignment, boundary */ 1102 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1103 BUS_SPACE_MAXADDR, /* highaddr */ 1104 NULL, NULL, /* filter, filterarg */ 1105 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1106 0, /* nsegments */ 1107 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1108 0, /* flags */ 1109 NULL, NULL, /* lockfunc, lockarg */ 1110 &sc->age_cdata.age_buffer_tag); 1111 if (error != 0) { 1112 device_printf(sc->age_dev, 1113 "could not create parent buffer DMA tag.\n"); 1114 goto fail; 1115 } 1116 1117 /* Create tag for Tx buffers. */ 1118 error = bus_dma_tag_create( 1119 sc->age_cdata.age_buffer_tag, /* parent */ 1120 1, 0, /* alignment, boundary */ 1121 BUS_SPACE_MAXADDR, /* lowaddr */ 1122 BUS_SPACE_MAXADDR, /* highaddr */ 1123 NULL, NULL, /* filter, filterarg */ 1124 AGE_TSO_MAXSIZE, /* maxsize */ 1125 AGE_MAXTXSEGS, /* nsegments */ 1126 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1127 0, /* flags */ 1128 NULL, NULL, /* lockfunc, lockarg */ 1129 &sc->age_cdata.age_tx_tag); 1130 if (error != 0) { 1131 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1132 goto fail; 1133 } 1134 1135 /* Create tag for Rx buffers. */ 1136 error = bus_dma_tag_create( 1137 sc->age_cdata.age_buffer_tag, /* parent */ 1138 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1139 BUS_SPACE_MAXADDR, /* lowaddr */ 1140 BUS_SPACE_MAXADDR, /* highaddr */ 1141 NULL, NULL, /* filter, filterarg */ 1142 MCLBYTES, /* maxsize */ 1143 1, /* nsegments */ 1144 MCLBYTES, /* maxsegsize */ 1145 0, /* flags */ 1146 NULL, NULL, /* lockfunc, lockarg */ 1147 &sc->age_cdata.age_rx_tag); 1148 if (error != 0) { 1149 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1150 goto fail; 1151 } 1152 1153 /* Create DMA maps for Tx buffers. */ 1154 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1155 txd = &sc->age_cdata.age_txdesc[i]; 1156 txd->tx_m = NULL; 1157 txd->tx_dmamap = NULL; 1158 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1159 &txd->tx_dmamap); 1160 if (error != 0) { 1161 device_printf(sc->age_dev, 1162 "could not create Tx dmamap.\n"); 1163 goto fail; 1164 } 1165 } 1166 /* Create DMA maps for Rx buffers. */ 1167 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1168 &sc->age_cdata.age_rx_sparemap)) != 0) { 1169 device_printf(sc->age_dev, 1170 "could not create spare Rx dmamap.\n"); 1171 goto fail; 1172 } 1173 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1174 rxd = &sc->age_cdata.age_rxdesc[i]; 1175 rxd->rx_m = NULL; 1176 rxd->rx_dmamap = NULL; 1177 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1178 &rxd->rx_dmamap); 1179 if (error != 0) { 1180 device_printf(sc->age_dev, 1181 "could not create Rx dmamap.\n"); 1182 goto fail; 1183 } 1184 } 1185 1186 fail: 1187 return (error); 1188 } 1189 1190 static void 1191 age_dma_free(struct age_softc *sc) 1192 { 1193 struct age_txdesc *txd; 1194 struct age_rxdesc *rxd; 1195 int i; 1196 1197 /* Tx buffers */ 1198 if (sc->age_cdata.age_tx_tag != NULL) { 1199 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1200 txd = &sc->age_cdata.age_txdesc[i]; 1201 if (txd->tx_dmamap != NULL) { 1202 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1203 txd->tx_dmamap); 1204 txd->tx_dmamap = NULL; 1205 } 1206 } 1207 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1208 sc->age_cdata.age_tx_tag = NULL; 1209 } 1210 /* Rx buffers */ 1211 if (sc->age_cdata.age_rx_tag != NULL) { 1212 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1213 rxd = &sc->age_cdata.age_rxdesc[i]; 1214 if (rxd->rx_dmamap != NULL) { 1215 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1216 rxd->rx_dmamap); 1217 rxd->rx_dmamap = NULL; 1218 } 1219 } 1220 if (sc->age_cdata.age_rx_sparemap != NULL) { 1221 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1222 sc->age_cdata.age_rx_sparemap); 1223 sc->age_cdata.age_rx_sparemap = NULL; 1224 } 1225 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1226 sc->age_cdata.age_rx_tag = NULL; 1227 } 1228 /* Tx ring. */ 1229 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1230 if (sc->age_rdata.age_tx_ring_paddr != 0) 1231 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1232 sc->age_cdata.age_tx_ring_map); 1233 if (sc->age_rdata.age_tx_ring != NULL) 1234 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1235 sc->age_rdata.age_tx_ring, 1236 sc->age_cdata.age_tx_ring_map); 1237 sc->age_rdata.age_tx_ring_paddr = 0; 1238 sc->age_rdata.age_tx_ring = NULL; 1239 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1240 sc->age_cdata.age_tx_ring_tag = NULL; 1241 } 1242 /* Rx ring. */ 1243 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1244 if (sc->age_rdata.age_rx_ring_paddr != 0) 1245 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1246 sc->age_cdata.age_rx_ring_map); 1247 if (sc->age_rdata.age_rx_ring != NULL) 1248 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1249 sc->age_rdata.age_rx_ring, 1250 sc->age_cdata.age_rx_ring_map); 1251 sc->age_rdata.age_rx_ring_paddr = 0; 1252 sc->age_rdata.age_rx_ring = NULL; 1253 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1254 sc->age_cdata.age_rx_ring_tag = NULL; 1255 } 1256 /* Rx return ring. */ 1257 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1258 if (sc->age_rdata.age_rr_ring_paddr != 0) 1259 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1260 sc->age_cdata.age_rr_ring_map); 1261 if (sc->age_rdata.age_rr_ring != NULL) 1262 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1263 sc->age_rdata.age_rr_ring, 1264 sc->age_cdata.age_rr_ring_map); 1265 sc->age_rdata.age_rr_ring_paddr = 0; 1266 sc->age_rdata.age_rr_ring = NULL; 1267 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1268 sc->age_cdata.age_rr_ring_tag = NULL; 1269 } 1270 /* CMB block */ 1271 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1272 if (sc->age_rdata.age_cmb_block_paddr != 0) 1273 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1274 sc->age_cdata.age_cmb_block_map); 1275 if (sc->age_rdata.age_cmb_block != NULL) 1276 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1277 sc->age_rdata.age_cmb_block, 1278 sc->age_cdata.age_cmb_block_map); 1279 sc->age_rdata.age_cmb_block_paddr = 0; 1280 sc->age_rdata.age_cmb_block = NULL; 1281 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1282 sc->age_cdata.age_cmb_block_tag = NULL; 1283 } 1284 /* SMB block */ 1285 if (sc->age_cdata.age_smb_block_tag != NULL) { 1286 if (sc->age_rdata.age_smb_block_paddr != 0) 1287 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1288 sc->age_cdata.age_smb_block_map); 1289 if (sc->age_rdata.age_smb_block != NULL) 1290 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1291 sc->age_rdata.age_smb_block, 1292 sc->age_cdata.age_smb_block_map); 1293 sc->age_rdata.age_smb_block_paddr = 0; 1294 sc->age_rdata.age_smb_block = NULL; 1295 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1296 sc->age_cdata.age_smb_block_tag = NULL; 1297 } 1298 1299 if (sc->age_cdata.age_buffer_tag != NULL) { 1300 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1301 sc->age_cdata.age_buffer_tag = NULL; 1302 } 1303 if (sc->age_cdata.age_parent_tag != NULL) { 1304 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1305 sc->age_cdata.age_parent_tag = NULL; 1306 } 1307 } 1308 1309 /* 1310 * Make sure the interface is stopped at reboot time. 1311 */ 1312 static int 1313 age_shutdown(device_t dev) 1314 { 1315 1316 return (age_suspend(dev)); 1317 } 1318 1319 static void 1320 age_setwol(struct age_softc *sc) 1321 { 1322 if_t ifp; 1323 struct mii_data *mii; 1324 uint32_t reg, pmcs; 1325 uint16_t pmstat; 1326 int aneg, i, pmc; 1327 1328 AGE_LOCK_ASSERT(sc); 1329 1330 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1331 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1332 /* 1333 * No PME capability, PHY power down. 1334 * XXX 1335 * Due to an unknown reason powering down PHY resulted 1336 * in unexpected results such as inaccessbility of 1337 * hardware of freshly rebooted system. Disable 1338 * powering down PHY until I got more information for 1339 * Attansic/Atheros PHY hardwares. 1340 */ 1341 #ifdef notyet 1342 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1343 MII_BMCR, BMCR_PDOWN); 1344 #endif 1345 return; 1346 } 1347 1348 ifp = sc->age_ifp; 1349 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1350 /* 1351 * Note, this driver resets the link speed to 10/100Mbps with 1352 * auto-negotiation but we don't know whether that operation 1353 * would succeed or not as it have no control after powering 1354 * off. If the renegotiation fail WOL may not work. Running 1355 * at 1Gbps will draw more power than 375mA at 3.3V which is 1356 * specified in PCI specification and that would result in 1357 * complete shutdowning power to ethernet controller. 1358 * 1359 * TODO 1360 * Save current negotiated media speed/duplex/flow-control 1361 * to softc and restore the same link again after resuming. 1362 * PHY handling such as power down/resetting to 100Mbps 1363 * may be better handled in suspend method in phy driver. 1364 */ 1365 mii = device_get_softc(sc->age_miibus); 1366 mii_pollstat(mii); 1367 aneg = 0; 1368 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1369 switch IFM_SUBTYPE(mii->mii_media_active) { 1370 case IFM_10_T: 1371 case IFM_100_TX: 1372 goto got_link; 1373 case IFM_1000_T: 1374 aneg++; 1375 default: 1376 break; 1377 } 1378 } 1379 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1380 MII_100T2CR, 0); 1381 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1382 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1383 ANAR_10 | ANAR_CSMA); 1384 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1385 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1386 DELAY(1000); 1387 if (aneg != 0) { 1388 /* Poll link state until age(4) get a 10/100 link. */ 1389 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1390 mii_pollstat(mii); 1391 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1392 switch (IFM_SUBTYPE( 1393 mii->mii_media_active)) { 1394 case IFM_10_T: 1395 case IFM_100_TX: 1396 age_mac_config(sc); 1397 goto got_link; 1398 default: 1399 break; 1400 } 1401 } 1402 AGE_UNLOCK(sc); 1403 pause("agelnk", hz); 1404 AGE_LOCK(sc); 1405 } 1406 if (i == MII_ANEGTICKS_GIGE) 1407 device_printf(sc->age_dev, 1408 "establishing link failed, " 1409 "WOL may not work!"); 1410 } 1411 /* 1412 * No link, force MAC to have 100Mbps, full-duplex link. 1413 * This is the last resort and may/may not work. 1414 */ 1415 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1416 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1417 age_mac_config(sc); 1418 } 1419 1420 got_link: 1421 pmcs = 0; 1422 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1423 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1424 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1425 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1426 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1427 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1428 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1429 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1430 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1431 reg |= MAC_CFG_RX_ENB; 1432 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1433 } 1434 1435 /* Request PME. */ 1436 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1437 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1438 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1439 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1440 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1441 #ifdef notyet 1442 /* See above for powering down PHY issues. */ 1443 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1444 /* No WOL, PHY power down. */ 1445 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1446 MII_BMCR, BMCR_PDOWN); 1447 } 1448 #endif 1449 } 1450 1451 static int 1452 age_suspend(device_t dev) 1453 { 1454 struct age_softc *sc; 1455 1456 sc = device_get_softc(dev); 1457 1458 AGE_LOCK(sc); 1459 age_stop(sc); 1460 age_setwol(sc); 1461 AGE_UNLOCK(sc); 1462 1463 return (0); 1464 } 1465 1466 static int 1467 age_resume(device_t dev) 1468 { 1469 struct age_softc *sc; 1470 if_t ifp; 1471 1472 sc = device_get_softc(dev); 1473 1474 AGE_LOCK(sc); 1475 age_phy_reset(sc); 1476 ifp = sc->age_ifp; 1477 if ((if_getflags(ifp) & IFF_UP) != 0) 1478 age_init_locked(sc); 1479 1480 AGE_UNLOCK(sc); 1481 1482 return (0); 1483 } 1484 1485 static int 1486 age_encap(struct age_softc *sc, struct mbuf **m_head) 1487 { 1488 struct age_txdesc *txd, *txd_last; 1489 struct tx_desc *desc; 1490 struct mbuf *m; 1491 struct ip *ip; 1492 struct tcphdr *tcp; 1493 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1494 bus_dmamap_t map; 1495 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1496 int error, i, nsegs, prod, si; 1497 1498 AGE_LOCK_ASSERT(sc); 1499 1500 M_ASSERTPKTHDR((*m_head)); 1501 1502 m = *m_head; 1503 ip = NULL; 1504 tcp = NULL; 1505 cflags = vtag = 0; 1506 ip_off = poff = 0; 1507 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1508 /* 1509 * L1 requires offset of TCP/UDP payload in its Tx 1510 * descriptor to perform hardware Tx checksum offload. 1511 * Additionally, TSO requires IP/TCP header size and 1512 * modification of IP/TCP header in order to make TSO 1513 * engine work. This kind of operation takes many CPU 1514 * cycles on FreeBSD so fast host CPU is needed to get 1515 * smooth TSO performance. 1516 */ 1517 struct ether_header *eh; 1518 1519 if (M_WRITABLE(m) == 0) { 1520 /* Get a writable copy. */ 1521 m = m_dup(*m_head, M_NOWAIT); 1522 /* Release original mbufs. */ 1523 m_freem(*m_head); 1524 if (m == NULL) { 1525 *m_head = NULL; 1526 return (ENOBUFS); 1527 } 1528 *m_head = m; 1529 } 1530 ip_off = sizeof(struct ether_header); 1531 m = m_pullup(m, ip_off); 1532 if (m == NULL) { 1533 *m_head = NULL; 1534 return (ENOBUFS); 1535 } 1536 eh = mtod(m, struct ether_header *); 1537 /* 1538 * Check if hardware VLAN insertion is off. 1539 * Additional check for LLC/SNAP frame? 1540 */ 1541 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1542 ip_off = sizeof(struct ether_vlan_header); 1543 m = m_pullup(m, ip_off); 1544 if (m == NULL) { 1545 *m_head = NULL; 1546 return (ENOBUFS); 1547 } 1548 } 1549 m = m_pullup(m, ip_off + sizeof(struct ip)); 1550 if (m == NULL) { 1551 *m_head = NULL; 1552 return (ENOBUFS); 1553 } 1554 ip = (struct ip *)(mtod(m, char *) + ip_off); 1555 poff = ip_off + (ip->ip_hl << 2); 1556 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1557 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1558 if (m == NULL) { 1559 *m_head = NULL; 1560 return (ENOBUFS); 1561 } 1562 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1563 m = m_pullup(m, poff + (tcp->th_off << 2)); 1564 if (m == NULL) { 1565 *m_head = NULL; 1566 return (ENOBUFS); 1567 } 1568 /* 1569 * L1 requires IP/TCP header size and offset as 1570 * well as TCP pseudo checksum which complicates 1571 * TSO configuration. I guess this comes from the 1572 * adherence to Microsoft NDIS Large Send 1573 * specification which requires insertion of 1574 * pseudo checksum by upper stack. The pseudo 1575 * checksum that NDIS refers to doesn't include 1576 * TCP payload length so age(4) should recompute 1577 * the pseudo checksum here. Hopefully this wouldn't 1578 * be much burden on modern CPUs. 1579 * Reset IP checksum and recompute TCP pseudo 1580 * checksum as NDIS specification said. 1581 */ 1582 ip = (struct ip *)(mtod(m, char *) + ip_off); 1583 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1584 ip->ip_sum = 0; 1585 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1586 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1587 } 1588 *m_head = m; 1589 } 1590 1591 si = prod = sc->age_cdata.age_tx_prod; 1592 txd = &sc->age_cdata.age_txdesc[prod]; 1593 txd_last = txd; 1594 map = txd->tx_dmamap; 1595 1596 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1597 *m_head, txsegs, &nsegs, 0); 1598 if (error == EFBIG) { 1599 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1600 if (m == NULL) { 1601 m_freem(*m_head); 1602 *m_head = NULL; 1603 return (ENOMEM); 1604 } 1605 *m_head = m; 1606 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1607 *m_head, txsegs, &nsegs, 0); 1608 if (error != 0) { 1609 m_freem(*m_head); 1610 *m_head = NULL; 1611 return (error); 1612 } 1613 } else if (error != 0) 1614 return (error); 1615 if (nsegs == 0) { 1616 m_freem(*m_head); 1617 *m_head = NULL; 1618 return (EIO); 1619 } 1620 1621 /* Check descriptor overrun. */ 1622 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1623 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1624 return (ENOBUFS); 1625 } 1626 1627 m = *m_head; 1628 /* Configure VLAN hardware tag insertion. */ 1629 if ((m->m_flags & M_VLANTAG) != 0) { 1630 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1631 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1632 cflags |= AGE_TD_INSERT_VLAN_TAG; 1633 } 1634 1635 desc = NULL; 1636 i = 0; 1637 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1638 /* Request TSO and set MSS. */ 1639 cflags |= AGE_TD_TSO_IPV4; 1640 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1641 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1642 AGE_TD_TSO_MSS_SHIFT); 1643 /* Set IP/TCP header size. */ 1644 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1645 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1646 /* 1647 * L1 requires the first buffer should only hold IP/TCP 1648 * header data. TCP payload should be handled in other 1649 * descriptors. 1650 */ 1651 hdrlen = poff + (tcp->th_off << 2); 1652 desc = &sc->age_rdata.age_tx_ring[prod]; 1653 desc->addr = htole64(txsegs[0].ds_addr); 1654 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1655 desc->flags = htole32(cflags); 1656 sc->age_cdata.age_tx_cnt++; 1657 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1658 if (m->m_len - hdrlen > 0) { 1659 /* Handle remaining payload of the 1st fragment. */ 1660 desc = &sc->age_rdata.age_tx_ring[prod]; 1661 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1662 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1663 vtag); 1664 desc->flags = htole32(cflags); 1665 sc->age_cdata.age_tx_cnt++; 1666 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1667 } 1668 /* Handle remaining fragments. */ 1669 i = 1; 1670 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1671 /* Configure Tx IP/TCP/UDP checksum offload. */ 1672 cflags |= AGE_TD_CSUM; 1673 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1674 cflags |= AGE_TD_TCPCSUM; 1675 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1676 cflags |= AGE_TD_UDPCSUM; 1677 /* Set checksum start offset. */ 1678 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1679 /* Set checksum insertion position of TCP/UDP. */ 1680 cflags |= ((poff + m->m_pkthdr.csum_data) << 1681 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1682 } 1683 for (; i < nsegs; i++) { 1684 desc = &sc->age_rdata.age_tx_ring[prod]; 1685 desc->addr = htole64(txsegs[i].ds_addr); 1686 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1687 desc->flags = htole32(cflags); 1688 sc->age_cdata.age_tx_cnt++; 1689 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1690 } 1691 /* Update producer index. */ 1692 sc->age_cdata.age_tx_prod = prod; 1693 1694 /* Set EOP on the last descriptor. */ 1695 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1696 desc = &sc->age_rdata.age_tx_ring[prod]; 1697 desc->flags |= htole32(AGE_TD_EOP); 1698 1699 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1700 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1701 desc = &sc->age_rdata.age_tx_ring[si]; 1702 desc->flags |= htole32(AGE_TD_TSO_HDR); 1703 } 1704 1705 /* Swap dmamap of the first and the last. */ 1706 txd = &sc->age_cdata.age_txdesc[prod]; 1707 map = txd_last->tx_dmamap; 1708 txd_last->tx_dmamap = txd->tx_dmamap; 1709 txd->tx_dmamap = map; 1710 txd->tx_m = m; 1711 1712 /* Sync descriptors. */ 1713 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1714 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1715 sc->age_cdata.age_tx_ring_map, 1716 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1717 1718 return (0); 1719 } 1720 1721 static void 1722 age_start(if_t ifp) 1723 { 1724 struct age_softc *sc; 1725 1726 sc = if_getsoftc(ifp); 1727 AGE_LOCK(sc); 1728 age_start_locked(ifp); 1729 AGE_UNLOCK(sc); 1730 } 1731 1732 static void 1733 age_start_locked(if_t ifp) 1734 { 1735 struct age_softc *sc; 1736 struct mbuf *m_head; 1737 int enq; 1738 1739 sc = if_getsoftc(ifp); 1740 1741 AGE_LOCK_ASSERT(sc); 1742 1743 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1744 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1745 return; 1746 1747 for (enq = 0; !if_sendq_empty(ifp); ) { 1748 m_head = if_dequeue(ifp); 1749 if (m_head == NULL) 1750 break; 1751 /* 1752 * Pack the data into the transmit ring. If we 1753 * don't have room, set the OACTIVE flag and wait 1754 * for the NIC to drain the ring. 1755 */ 1756 if (age_encap(sc, &m_head)) { 1757 if (m_head == NULL) 1758 break; 1759 if_sendq_prepend(ifp, m_head); 1760 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1761 break; 1762 } 1763 1764 enq++; 1765 /* 1766 * If there's a BPF listener, bounce a copy of this frame 1767 * to him. 1768 */ 1769 ETHER_BPF_MTAP(ifp, m_head); 1770 } 1771 1772 if (enq > 0) { 1773 /* Update mbox. */ 1774 AGE_COMMIT_MBOX(sc); 1775 /* Set a timeout in case the chip goes out to lunch. */ 1776 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1777 } 1778 } 1779 1780 static void 1781 age_watchdog(struct age_softc *sc) 1782 { 1783 if_t ifp; 1784 1785 AGE_LOCK_ASSERT(sc); 1786 1787 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1788 return; 1789 1790 ifp = sc->age_ifp; 1791 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1792 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1793 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1794 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1795 age_init_locked(sc); 1796 return; 1797 } 1798 if (sc->age_cdata.age_tx_cnt == 0) { 1799 if_printf(sc->age_ifp, 1800 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1801 if (!if_sendq_empty(ifp)) 1802 age_start_locked(ifp); 1803 return; 1804 } 1805 if_printf(sc->age_ifp, "watchdog timeout\n"); 1806 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1807 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1808 age_init_locked(sc); 1809 if (!if_sendq_empty(ifp)) 1810 age_start_locked(ifp); 1811 } 1812 1813 static int 1814 age_ioctl(if_t ifp, u_long cmd, caddr_t data) 1815 { 1816 struct age_softc *sc; 1817 struct ifreq *ifr; 1818 struct mii_data *mii; 1819 uint32_t reg; 1820 int error, mask; 1821 1822 sc = if_getsoftc(ifp); 1823 ifr = (struct ifreq *)data; 1824 error = 0; 1825 switch (cmd) { 1826 case SIOCSIFMTU: 1827 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1828 error = EINVAL; 1829 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1830 AGE_LOCK(sc); 1831 if_setmtu(ifp, ifr->ifr_mtu); 1832 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1833 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1834 age_init_locked(sc); 1835 } 1836 AGE_UNLOCK(sc); 1837 } 1838 break; 1839 case SIOCSIFFLAGS: 1840 AGE_LOCK(sc); 1841 if ((if_getflags(ifp) & IFF_UP) != 0) { 1842 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1843 if (((if_getflags(ifp) ^ sc->age_if_flags) 1844 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1845 age_rxfilter(sc); 1846 } else { 1847 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1848 age_init_locked(sc); 1849 } 1850 } else { 1851 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1852 age_stop(sc); 1853 } 1854 sc->age_if_flags = if_getflags(ifp); 1855 AGE_UNLOCK(sc); 1856 break; 1857 case SIOCADDMULTI: 1858 case SIOCDELMULTI: 1859 AGE_LOCK(sc); 1860 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1861 age_rxfilter(sc); 1862 AGE_UNLOCK(sc); 1863 break; 1864 case SIOCSIFMEDIA: 1865 case SIOCGIFMEDIA: 1866 mii = device_get_softc(sc->age_miibus); 1867 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1868 break; 1869 case SIOCSIFCAP: 1870 AGE_LOCK(sc); 1871 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1872 if ((mask & IFCAP_TXCSUM) != 0 && 1873 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1874 if_togglecapenable(ifp, IFCAP_TXCSUM); 1875 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1876 if_sethwassistbits(ifp, AGE_CSUM_FEATURES, 0); 1877 else 1878 if_sethwassistbits(ifp, 0, AGE_CSUM_FEATURES); 1879 } 1880 if ((mask & IFCAP_RXCSUM) != 0 && 1881 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) { 1882 if_togglecapenable(ifp, IFCAP_RXCSUM); 1883 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1884 reg &= ~MAC_CFG_RXCSUM_ENB; 1885 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1886 reg |= MAC_CFG_RXCSUM_ENB; 1887 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1888 } 1889 if ((mask & IFCAP_TSO4) != 0 && 1890 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1891 if_togglecapenable(ifp, IFCAP_TSO4); 1892 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 1893 if_sethwassistbits(ifp, CSUM_TSO, 0); 1894 else 1895 if_sethwassistbits(ifp, 0, CSUM_TSO); 1896 } 1897 1898 if ((mask & IFCAP_WOL_MCAST) != 0 && 1899 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 1900 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 1901 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1902 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 1903 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 1904 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1905 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 1906 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 1907 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1908 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 1909 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 1910 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1911 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 1912 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 1913 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 1914 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 1915 age_rxvlan(sc); 1916 } 1917 AGE_UNLOCK(sc); 1918 VLAN_CAPABILITIES(ifp); 1919 break; 1920 default: 1921 error = ether_ioctl(ifp, cmd, data); 1922 break; 1923 } 1924 1925 return (error); 1926 } 1927 1928 static void 1929 age_mac_config(struct age_softc *sc) 1930 { 1931 struct mii_data *mii; 1932 uint32_t reg; 1933 1934 AGE_LOCK_ASSERT(sc); 1935 1936 mii = device_get_softc(sc->age_miibus); 1937 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1938 reg &= ~MAC_CFG_FULL_DUPLEX; 1939 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1940 reg &= ~MAC_CFG_SPEED_MASK; 1941 /* Reprogram MAC with resolved speed/duplex. */ 1942 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1943 case IFM_10_T: 1944 case IFM_100_TX: 1945 reg |= MAC_CFG_SPEED_10_100; 1946 break; 1947 case IFM_1000_T: 1948 reg |= MAC_CFG_SPEED_1000; 1949 break; 1950 } 1951 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1952 reg |= MAC_CFG_FULL_DUPLEX; 1953 #ifdef notyet 1954 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1955 reg |= MAC_CFG_TX_FC; 1956 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1957 reg |= MAC_CFG_RX_FC; 1958 #endif 1959 } 1960 1961 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1962 } 1963 1964 static void 1965 age_link_task(void *arg, int pending) 1966 { 1967 struct age_softc *sc; 1968 struct mii_data *mii; 1969 if_t ifp; 1970 uint32_t reg; 1971 1972 sc = (struct age_softc *)arg; 1973 1974 AGE_LOCK(sc); 1975 mii = device_get_softc(sc->age_miibus); 1976 ifp = sc->age_ifp; 1977 if (mii == NULL || ifp == NULL || 1978 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 1979 AGE_UNLOCK(sc); 1980 return; 1981 } 1982 1983 sc->age_flags &= ~AGE_FLAG_LINK; 1984 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1985 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1986 case IFM_10_T: 1987 case IFM_100_TX: 1988 case IFM_1000_T: 1989 sc->age_flags |= AGE_FLAG_LINK; 1990 break; 1991 default: 1992 break; 1993 } 1994 } 1995 1996 /* Stop Rx/Tx MACs. */ 1997 age_stop_rxmac(sc); 1998 age_stop_txmac(sc); 1999 2000 /* Program MACs with resolved speed/duplex/flow-control. */ 2001 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2002 age_mac_config(sc); 2003 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2004 /* Restart DMA engine and Tx/Rx MAC. */ 2005 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2006 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2007 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2008 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2009 } 2010 2011 AGE_UNLOCK(sc); 2012 } 2013 2014 static void 2015 age_stats_update(struct age_softc *sc) 2016 { 2017 struct age_stats *stat; 2018 struct smb *smb; 2019 if_t ifp; 2020 2021 AGE_LOCK_ASSERT(sc); 2022 2023 stat = &sc->age_stat; 2024 2025 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2026 sc->age_cdata.age_smb_block_map, 2027 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2028 2029 smb = sc->age_rdata.age_smb_block; 2030 if (smb->updated == 0) 2031 return; 2032 2033 ifp = sc->age_ifp; 2034 /* Rx stats. */ 2035 stat->rx_frames += smb->rx_frames; 2036 stat->rx_bcast_frames += smb->rx_bcast_frames; 2037 stat->rx_mcast_frames += smb->rx_mcast_frames; 2038 stat->rx_pause_frames += smb->rx_pause_frames; 2039 stat->rx_control_frames += smb->rx_control_frames; 2040 stat->rx_crcerrs += smb->rx_crcerrs; 2041 stat->rx_lenerrs += smb->rx_lenerrs; 2042 stat->rx_bytes += smb->rx_bytes; 2043 stat->rx_runts += smb->rx_runts; 2044 stat->rx_fragments += smb->rx_fragments; 2045 stat->rx_pkts_64 += smb->rx_pkts_64; 2046 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2047 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2048 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2049 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2050 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2051 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2052 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2053 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2054 stat->rx_desc_oflows += smb->rx_desc_oflows; 2055 stat->rx_alignerrs += smb->rx_alignerrs; 2056 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2057 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2058 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2059 2060 /* Tx stats. */ 2061 stat->tx_frames += smb->tx_frames; 2062 stat->tx_bcast_frames += smb->tx_bcast_frames; 2063 stat->tx_mcast_frames += smb->tx_mcast_frames; 2064 stat->tx_pause_frames += smb->tx_pause_frames; 2065 stat->tx_excess_defer += smb->tx_excess_defer; 2066 stat->tx_control_frames += smb->tx_control_frames; 2067 stat->tx_deferred += smb->tx_deferred; 2068 stat->tx_bytes += smb->tx_bytes; 2069 stat->tx_pkts_64 += smb->tx_pkts_64; 2070 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2071 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2072 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2073 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2074 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2075 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2076 stat->tx_single_colls += smb->tx_single_colls; 2077 stat->tx_multi_colls += smb->tx_multi_colls; 2078 stat->tx_late_colls += smb->tx_late_colls; 2079 stat->tx_excess_colls += smb->tx_excess_colls; 2080 stat->tx_underrun += smb->tx_underrun; 2081 stat->tx_desc_underrun += smb->tx_desc_underrun; 2082 stat->tx_lenerrs += smb->tx_lenerrs; 2083 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2084 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2085 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2086 2087 /* Update counters in ifnet. */ 2088 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2089 2090 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2091 smb->tx_multi_colls + smb->tx_late_colls + 2092 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2093 2094 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2095 smb->tx_late_colls + smb->tx_underrun + 2096 smb->tx_pkts_truncated); 2097 2098 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2099 2100 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2101 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2102 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2103 smb->rx_alignerrs); 2104 2105 /* Update done, clear. */ 2106 smb->updated = 0; 2107 2108 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2109 sc->age_cdata.age_smb_block_map, 2110 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2111 } 2112 2113 static int 2114 age_intr(void *arg) 2115 { 2116 struct age_softc *sc; 2117 uint32_t status; 2118 2119 sc = (struct age_softc *)arg; 2120 2121 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2122 if (status == 0 || (status & AGE_INTRS) == 0) 2123 return (FILTER_STRAY); 2124 /* Disable interrupts. */ 2125 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2126 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2127 2128 return (FILTER_HANDLED); 2129 } 2130 2131 static void 2132 age_int_task(void *arg, int pending) 2133 { 2134 struct age_softc *sc; 2135 if_t ifp; 2136 struct cmb *cmb; 2137 uint32_t status; 2138 2139 sc = (struct age_softc *)arg; 2140 2141 AGE_LOCK(sc); 2142 2143 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2144 sc->age_cdata.age_cmb_block_map, 2145 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2146 cmb = sc->age_rdata.age_cmb_block; 2147 status = le32toh(cmb->intr_status); 2148 if (sc->age_morework != 0) 2149 status |= INTR_CMB_RX; 2150 if ((status & AGE_INTRS) == 0) 2151 goto done; 2152 2153 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2154 TPD_CONS_SHIFT; 2155 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2156 RRD_PROD_SHIFT; 2157 /* Let hardware know CMB was served. */ 2158 cmb->intr_status = 0; 2159 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2160 sc->age_cdata.age_cmb_block_map, 2161 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2162 2163 ifp = sc->age_ifp; 2164 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2165 if ((status & INTR_CMB_RX) != 0) 2166 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2167 sc->age_process_limit); 2168 if ((status & INTR_CMB_TX) != 0) 2169 age_txintr(sc, sc->age_tpd_cons); 2170 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2171 if ((status & INTR_DMA_RD_TO_RST) != 0) 2172 device_printf(sc->age_dev, 2173 "DMA read error! -- resetting\n"); 2174 if ((status & INTR_DMA_WR_TO_RST) != 0) 2175 device_printf(sc->age_dev, 2176 "DMA write error! -- resetting\n"); 2177 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2178 age_init_locked(sc); 2179 } 2180 if (!if_sendq_empty(ifp)) 2181 age_start_locked(ifp); 2182 if ((status & INTR_SMB) != 0) 2183 age_stats_update(sc); 2184 } 2185 2186 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2187 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2188 sc->age_cdata.age_cmb_block_map, 2189 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2190 status = le32toh(cmb->intr_status); 2191 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2192 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2193 AGE_UNLOCK(sc); 2194 return; 2195 } 2196 2197 done: 2198 /* Re-enable interrupts. */ 2199 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2200 AGE_UNLOCK(sc); 2201 } 2202 2203 static void 2204 age_txintr(struct age_softc *sc, int tpd_cons) 2205 { 2206 if_t ifp; 2207 struct age_txdesc *txd; 2208 int cons, prog; 2209 2210 AGE_LOCK_ASSERT(sc); 2211 2212 ifp = sc->age_ifp; 2213 2214 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2215 sc->age_cdata.age_tx_ring_map, 2216 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2217 2218 /* 2219 * Go through our Tx list and free mbufs for those 2220 * frames which have been transmitted. 2221 */ 2222 cons = sc->age_cdata.age_tx_cons; 2223 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2224 if (sc->age_cdata.age_tx_cnt <= 0) 2225 break; 2226 prog++; 2227 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2228 sc->age_cdata.age_tx_cnt--; 2229 txd = &sc->age_cdata.age_txdesc[cons]; 2230 /* 2231 * Clear Tx descriptors, it's not required but would 2232 * help debugging in case of Tx issues. 2233 */ 2234 txd->tx_desc->addr = 0; 2235 txd->tx_desc->len = 0; 2236 txd->tx_desc->flags = 0; 2237 2238 if (txd->tx_m == NULL) 2239 continue; 2240 /* Reclaim transmitted mbufs. */ 2241 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2242 BUS_DMASYNC_POSTWRITE); 2243 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2244 m_freem(txd->tx_m); 2245 txd->tx_m = NULL; 2246 } 2247 2248 if (prog > 0) { 2249 sc->age_cdata.age_tx_cons = cons; 2250 2251 /* 2252 * Unarm watchdog timer only when there are no pending 2253 * Tx descriptors in queue. 2254 */ 2255 if (sc->age_cdata.age_tx_cnt == 0) 2256 sc->age_watchdog_timer = 0; 2257 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2258 sc->age_cdata.age_tx_ring_map, 2259 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2260 } 2261 } 2262 2263 #ifndef __NO_STRICT_ALIGNMENT 2264 static struct mbuf * 2265 age_fixup_rx(if_t ifp, struct mbuf *m) 2266 { 2267 struct mbuf *n; 2268 int i; 2269 uint16_t *src, *dst; 2270 2271 src = mtod(m, uint16_t *); 2272 dst = src - 3; 2273 2274 if (m->m_next == NULL) { 2275 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2276 *dst++ = *src++; 2277 m->m_data -= 6; 2278 return (m); 2279 } 2280 /* 2281 * Append a new mbuf to received mbuf chain and copy ethernet 2282 * header from the mbuf chain. This can save lots of CPU 2283 * cycles for jumbo frame. 2284 */ 2285 MGETHDR(n, M_NOWAIT, MT_DATA); 2286 if (n == NULL) { 2287 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2288 m_freem(m); 2289 return (NULL); 2290 } 2291 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2292 m->m_data += ETHER_HDR_LEN; 2293 m->m_len -= ETHER_HDR_LEN; 2294 n->m_len = ETHER_HDR_LEN; 2295 M_MOVE_PKTHDR(n, m); 2296 n->m_next = m; 2297 return (n); 2298 } 2299 #endif 2300 2301 /* Receive a frame. */ 2302 static void 2303 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2304 { 2305 struct age_rxdesc *rxd; 2306 if_t ifp; 2307 struct mbuf *mp, *m; 2308 uint32_t status, index, vtag; 2309 int count, nsegs; 2310 int rx_cons; 2311 2312 AGE_LOCK_ASSERT(sc); 2313 2314 ifp = sc->age_ifp; 2315 status = le32toh(rxrd->flags); 2316 index = le32toh(rxrd->index); 2317 rx_cons = AGE_RX_CONS(index); 2318 nsegs = AGE_RX_NSEGS(index); 2319 2320 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2321 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2322 /* 2323 * We want to pass the following frames to upper 2324 * layer regardless of error status of Rx return 2325 * ring. 2326 * 2327 * o IP/TCP/UDP checksum is bad. 2328 * o frame length and protocol specific length 2329 * does not match. 2330 */ 2331 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2332 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2333 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2334 return; 2335 } 2336 2337 for (count = 0; count < nsegs; count++, 2338 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2339 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2340 mp = rxd->rx_m; 2341 /* Add a new receive buffer to the ring. */ 2342 if (age_newbuf(sc, rxd) != 0) { 2343 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2344 /* Reuse Rx buffers. */ 2345 if (sc->age_cdata.age_rxhead != NULL) 2346 m_freem(sc->age_cdata.age_rxhead); 2347 break; 2348 } 2349 2350 /* 2351 * Assume we've received a full sized frame. 2352 * Actual size is fixed when we encounter the end of 2353 * multi-segmented frame. 2354 */ 2355 mp->m_len = AGE_RX_BUF_SIZE; 2356 2357 /* Chain received mbufs. */ 2358 if (sc->age_cdata.age_rxhead == NULL) { 2359 sc->age_cdata.age_rxhead = mp; 2360 sc->age_cdata.age_rxtail = mp; 2361 } else { 2362 mp->m_flags &= ~M_PKTHDR; 2363 sc->age_cdata.age_rxprev_tail = 2364 sc->age_cdata.age_rxtail; 2365 sc->age_cdata.age_rxtail->m_next = mp; 2366 sc->age_cdata.age_rxtail = mp; 2367 } 2368 2369 if (count == nsegs - 1) { 2370 /* Last desc. for this frame. */ 2371 m = sc->age_cdata.age_rxhead; 2372 m->m_flags |= M_PKTHDR; 2373 /* 2374 * It seems that L1 controller has no way 2375 * to tell hardware to strip CRC bytes. 2376 */ 2377 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2378 ETHER_CRC_LEN; 2379 if (nsegs > 1) { 2380 /* Set last mbuf size. */ 2381 mp->m_len = sc->age_cdata.age_rxlen - 2382 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2383 /* Remove the CRC bytes in chained mbufs. */ 2384 if (mp->m_len <= ETHER_CRC_LEN) { 2385 sc->age_cdata.age_rxtail = 2386 sc->age_cdata.age_rxprev_tail; 2387 sc->age_cdata.age_rxtail->m_len -= 2388 (ETHER_CRC_LEN - mp->m_len); 2389 sc->age_cdata.age_rxtail->m_next = NULL; 2390 m_freem(mp); 2391 } else { 2392 mp->m_len -= ETHER_CRC_LEN; 2393 } 2394 } else 2395 m->m_len = m->m_pkthdr.len; 2396 m->m_pkthdr.rcvif = ifp; 2397 /* 2398 * Set checksum information. 2399 * It seems that L1 controller can compute partial 2400 * checksum. The partial checksum value can be used 2401 * to accelerate checksum computation for fragmented 2402 * TCP/UDP packets. Upper network stack already 2403 * takes advantage of the partial checksum value in 2404 * IP reassembly stage. But I'm not sure the 2405 * correctness of the partial hardware checksum 2406 * assistance due to lack of data sheet. If it is 2407 * proven to work on L1 I'll enable it. 2408 */ 2409 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2410 (status & AGE_RRD_IPV4) != 0) { 2411 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2412 m->m_pkthdr.csum_flags |= 2413 CSUM_IP_CHECKED | CSUM_IP_VALID; 2414 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2415 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2416 m->m_pkthdr.csum_flags |= 2417 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2418 m->m_pkthdr.csum_data = 0xffff; 2419 } 2420 /* 2421 * Don't mark bad checksum for TCP/UDP frames 2422 * as fragmented frames may always have set 2423 * bad checksummed bit of descriptor status. 2424 */ 2425 } 2426 2427 /* Check for VLAN tagged frames. */ 2428 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2429 (status & AGE_RRD_VLAN) != 0) { 2430 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2431 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2432 m->m_flags |= M_VLANTAG; 2433 } 2434 #ifndef __NO_STRICT_ALIGNMENT 2435 m = age_fixup_rx(ifp, m); 2436 if (m != NULL) 2437 #endif 2438 { 2439 /* Pass it on. */ 2440 AGE_UNLOCK(sc); 2441 if_input(ifp, m); 2442 AGE_LOCK(sc); 2443 } 2444 } 2445 } 2446 2447 /* Reset mbuf chains. */ 2448 AGE_RXCHAIN_RESET(sc); 2449 } 2450 2451 static int 2452 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2453 { 2454 struct rx_rdesc *rxrd; 2455 int rr_cons, nsegs, pktlen, prog; 2456 2457 AGE_LOCK_ASSERT(sc); 2458 2459 rr_cons = sc->age_cdata.age_rr_cons; 2460 if (rr_cons == rr_prod) 2461 return (0); 2462 2463 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2464 sc->age_cdata.age_rr_ring_map, 2465 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2466 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2467 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2468 2469 for (prog = 0; rr_cons != rr_prod; prog++) { 2470 if (count-- <= 0) 2471 break; 2472 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2473 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2474 if (nsegs == 0) 2475 break; 2476 /* 2477 * Check number of segments against received bytes. 2478 * Non-matching value would indicate that hardware 2479 * is still trying to update Rx return descriptors. 2480 * I'm not sure whether this check is really needed. 2481 */ 2482 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2483 if (nsegs != howmany(pktlen, AGE_RX_BUF_SIZE)) 2484 break; 2485 2486 /* Received a frame. */ 2487 age_rxeof(sc, rxrd); 2488 /* Clear return ring. */ 2489 rxrd->index = 0; 2490 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2491 sc->age_cdata.age_rx_cons += nsegs; 2492 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2493 } 2494 2495 if (prog > 0) { 2496 /* Update the consumer index. */ 2497 sc->age_cdata.age_rr_cons = rr_cons; 2498 2499 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2500 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2501 /* Sync descriptors. */ 2502 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2503 sc->age_cdata.age_rr_ring_map, 2504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2505 2506 /* Notify hardware availability of new Rx buffers. */ 2507 AGE_COMMIT_MBOX(sc); 2508 } 2509 2510 return (count > 0 ? 0 : EAGAIN); 2511 } 2512 2513 static void 2514 age_tick(void *arg) 2515 { 2516 struct age_softc *sc; 2517 struct mii_data *mii; 2518 2519 sc = (struct age_softc *)arg; 2520 2521 AGE_LOCK_ASSERT(sc); 2522 2523 mii = device_get_softc(sc->age_miibus); 2524 mii_tick(mii); 2525 age_watchdog(sc); 2526 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2527 } 2528 2529 static void 2530 age_reset(struct age_softc *sc) 2531 { 2532 uint32_t reg; 2533 int i; 2534 2535 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2536 CSR_READ_4(sc, AGE_MASTER_CFG); 2537 DELAY(1000); 2538 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2539 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2540 break; 2541 DELAY(10); 2542 } 2543 2544 if (i == 0) 2545 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2546 /* Initialize PCIe module. From Linux. */ 2547 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2548 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2549 } 2550 2551 static void 2552 age_init(void *xsc) 2553 { 2554 struct age_softc *sc; 2555 2556 sc = (struct age_softc *)xsc; 2557 AGE_LOCK(sc); 2558 age_init_locked(sc); 2559 AGE_UNLOCK(sc); 2560 } 2561 2562 static void 2563 age_init_locked(struct age_softc *sc) 2564 { 2565 if_t ifp; 2566 struct mii_data *mii; 2567 uint8_t eaddr[ETHER_ADDR_LEN]; 2568 bus_addr_t paddr; 2569 uint32_t reg, fsize; 2570 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2571 int error; 2572 2573 AGE_LOCK_ASSERT(sc); 2574 2575 ifp = sc->age_ifp; 2576 mii = device_get_softc(sc->age_miibus); 2577 2578 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2579 return; 2580 2581 /* 2582 * Cancel any pending I/O. 2583 */ 2584 age_stop(sc); 2585 2586 /* 2587 * Reset the chip to a known state. 2588 */ 2589 age_reset(sc); 2590 2591 /* Initialize descriptors. */ 2592 error = age_init_rx_ring(sc); 2593 if (error != 0) { 2594 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2595 age_stop(sc); 2596 return; 2597 } 2598 age_init_rr_ring(sc); 2599 age_init_tx_ring(sc); 2600 age_init_cmb_block(sc); 2601 age_init_smb_block(sc); 2602 2603 /* Reprogram the station address. */ 2604 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2605 CSR_WRITE_4(sc, AGE_PAR0, 2606 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2607 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2608 2609 /* Set descriptor base addresses. */ 2610 paddr = sc->age_rdata.age_tx_ring_paddr; 2611 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2612 paddr = sc->age_rdata.age_rx_ring_paddr; 2613 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2614 paddr = sc->age_rdata.age_rr_ring_paddr; 2615 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2616 paddr = sc->age_rdata.age_tx_ring_paddr; 2617 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2618 paddr = sc->age_rdata.age_cmb_block_paddr; 2619 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2620 paddr = sc->age_rdata.age_smb_block_paddr; 2621 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2622 /* Set Rx/Rx return descriptor counter. */ 2623 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2624 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2625 DESC_RRD_CNT_MASK) | 2626 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2627 /* Set Tx descriptor counter. */ 2628 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2629 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2630 2631 /* Tell hardware that we're ready to load descriptors. */ 2632 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2633 2634 /* 2635 * Initialize mailbox register. 2636 * Updated producer/consumer index information is exchanged 2637 * through this mailbox register. However Tx producer and 2638 * Rx return consumer/Rx producer are all shared such that 2639 * it's hard to separate code path between Tx and Rx without 2640 * locking. If L1 hardware have a separate mail box register 2641 * for Tx and Rx consumer/producer management we could have 2642 * independent Tx/Rx handler which in turn Rx handler could have 2643 * been run without any locking. 2644 */ 2645 AGE_COMMIT_MBOX(sc); 2646 2647 /* Configure IPG/IFG parameters. */ 2648 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2649 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2650 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2651 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2652 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2653 2654 /* Set parameters for half-duplex media. */ 2655 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2656 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2657 HDPX_CFG_LCOL_MASK) | 2658 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2659 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2660 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2661 HDPX_CFG_ABEBT_MASK) | 2662 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2663 HDPX_CFG_JAMIPG_MASK)); 2664 2665 /* Configure interrupt moderation timer. */ 2666 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2667 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2668 reg &= ~MASTER_MTIMER_ENB; 2669 if (AGE_USECS(sc->age_int_mod) == 0) 2670 reg &= ~MASTER_ITIMER_ENB; 2671 else 2672 reg |= MASTER_ITIMER_ENB; 2673 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2674 if (bootverbose) 2675 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2676 sc->age_int_mod); 2677 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2678 2679 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2680 if (if_getmtu(ifp) < ETHERMTU) 2681 sc->age_max_frame_size = ETHERMTU; 2682 else 2683 sc->age_max_frame_size = if_getmtu(ifp); 2684 sc->age_max_frame_size += ETHER_HDR_LEN + 2685 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2686 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2687 /* Configure jumbo frame. */ 2688 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2689 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2690 (((fsize / sizeof(uint64_t)) << 2691 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2692 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2693 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2694 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2695 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2696 2697 /* Configure flow-control parameters. From Linux. */ 2698 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2699 /* 2700 * Magic workaround for old-L1. 2701 * Don't know which hw revision requires this magic. 2702 */ 2703 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2704 /* 2705 * Another magic workaround for flow-control mode 2706 * change. From Linux. 2707 */ 2708 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2709 } 2710 /* 2711 * TODO 2712 * Should understand pause parameter relationships between FIFO 2713 * size and number of Rx descriptors and Rx return descriptors. 2714 * 2715 * Magic parameters came from Linux. 2716 */ 2717 switch (sc->age_chip_rev) { 2718 case 0x8001: 2719 case 0x9001: 2720 case 0x9002: 2721 case 0x9003: 2722 rxf_hi = AGE_RX_RING_CNT / 16; 2723 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2724 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2725 rrd_lo = AGE_RR_RING_CNT / 16; 2726 break; 2727 default: 2728 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2729 rxf_lo = reg / 16; 2730 if (rxf_lo < 192) 2731 rxf_lo = 192; 2732 rxf_hi = (reg * 7) / 8; 2733 if (rxf_hi < rxf_lo) 2734 rxf_hi = rxf_lo + 16; 2735 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2736 rrd_lo = reg / 8; 2737 rrd_hi = (reg * 7) / 8; 2738 if (rrd_lo < 2) 2739 rrd_lo = 2; 2740 if (rrd_hi < rrd_lo) 2741 rrd_hi = rrd_lo + 3; 2742 break; 2743 } 2744 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2745 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2746 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2747 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2748 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2749 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2750 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2751 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2752 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2753 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2754 2755 /* Configure RxQ. */ 2756 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2757 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2758 RXQ_CFG_RD_BURST_MASK) | 2759 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2760 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2761 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2762 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2763 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2764 2765 /* Configure TxQ. */ 2766 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2767 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2768 TXQ_CFG_TPD_BURST_MASK) | 2769 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2770 TXQ_CFG_TX_FIFO_BURST_MASK) | 2771 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2772 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2773 TXQ_CFG_ENB); 2774 2775 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2776 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2777 TX_JUMBO_TPD_TH_MASK) | 2778 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2779 TX_JUMBO_TPD_IPG_MASK)); 2780 /* Configure DMA parameters. */ 2781 CSR_WRITE_4(sc, AGE_DMA_CFG, 2782 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2783 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2784 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2785 2786 /* Configure CMB DMA write threshold. */ 2787 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2788 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2789 CMB_WR_THRESH_RRD_MASK) | 2790 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2791 CMB_WR_THRESH_TPD_MASK)); 2792 2793 /* Set CMB/SMB timer and enable them. */ 2794 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2795 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2796 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2797 /* Request SMB updates for every seconds. */ 2798 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2799 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2800 2801 /* 2802 * Disable all WOL bits as WOL can interfere normal Rx 2803 * operation. 2804 */ 2805 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2806 2807 /* 2808 * Configure Tx/Rx MACs. 2809 * - Auto-padding for short frames. 2810 * - Enable CRC generation. 2811 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2812 * of MAC is followed after link establishment. 2813 */ 2814 CSR_WRITE_4(sc, AGE_MAC_CFG, 2815 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2816 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2817 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2818 MAC_CFG_PREAMBLE_MASK)); 2819 /* Set up the receive filter. */ 2820 age_rxfilter(sc); 2821 age_rxvlan(sc); 2822 2823 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2824 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 2825 reg |= MAC_CFG_RXCSUM_ENB; 2826 2827 /* Ack all pending interrupts and clear it. */ 2828 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2829 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2830 2831 /* Finally enable Tx/Rx MAC. */ 2832 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2833 2834 sc->age_flags &= ~AGE_FLAG_LINK; 2835 /* Switch to the current media. */ 2836 mii_mediachg(mii); 2837 2838 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2839 2840 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2841 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2842 } 2843 2844 static void 2845 age_stop(struct age_softc *sc) 2846 { 2847 if_t ifp; 2848 struct age_txdesc *txd; 2849 struct age_rxdesc *rxd; 2850 uint32_t reg; 2851 int i; 2852 2853 AGE_LOCK_ASSERT(sc); 2854 /* 2855 * Mark the interface down and cancel the watchdog timer. 2856 */ 2857 ifp = sc->age_ifp; 2858 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2859 sc->age_flags &= ~AGE_FLAG_LINK; 2860 callout_stop(&sc->age_tick_ch); 2861 sc->age_watchdog_timer = 0; 2862 2863 /* 2864 * Disable interrupts. 2865 */ 2866 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2867 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2868 /* Stop CMB/SMB updates. */ 2869 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2870 /* Stop Rx/Tx MAC. */ 2871 age_stop_rxmac(sc); 2872 age_stop_txmac(sc); 2873 /* Stop DMA. */ 2874 CSR_WRITE_4(sc, AGE_DMA_CFG, 2875 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2876 /* Stop TxQ/RxQ. */ 2877 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2878 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2879 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2880 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2881 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2882 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2883 break; 2884 DELAY(10); 2885 } 2886 if (i == 0) 2887 device_printf(sc->age_dev, 2888 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2889 2890 /* Reclaim Rx buffers that have been processed. */ 2891 if (sc->age_cdata.age_rxhead != NULL) 2892 m_freem(sc->age_cdata.age_rxhead); 2893 AGE_RXCHAIN_RESET(sc); 2894 /* 2895 * Free RX and TX mbufs still in the queues. 2896 */ 2897 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2898 rxd = &sc->age_cdata.age_rxdesc[i]; 2899 if (rxd->rx_m != NULL) { 2900 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2901 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2902 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2903 rxd->rx_dmamap); 2904 m_freem(rxd->rx_m); 2905 rxd->rx_m = NULL; 2906 } 2907 } 2908 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2909 txd = &sc->age_cdata.age_txdesc[i]; 2910 if (txd->tx_m != NULL) { 2911 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2912 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2913 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2914 txd->tx_dmamap); 2915 m_freem(txd->tx_m); 2916 txd->tx_m = NULL; 2917 } 2918 } 2919 } 2920 2921 static void 2922 age_stop_txmac(struct age_softc *sc) 2923 { 2924 uint32_t reg; 2925 int i; 2926 2927 AGE_LOCK_ASSERT(sc); 2928 2929 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2930 if ((reg & MAC_CFG_TX_ENB) != 0) { 2931 reg &= ~MAC_CFG_TX_ENB; 2932 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2933 } 2934 /* Stop Tx DMA engine. */ 2935 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2936 if ((reg & DMA_CFG_RD_ENB) != 0) { 2937 reg &= ~DMA_CFG_RD_ENB; 2938 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2939 } 2940 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2941 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2942 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2943 break; 2944 DELAY(10); 2945 } 2946 if (i == 0) 2947 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2948 } 2949 2950 static void 2951 age_stop_rxmac(struct age_softc *sc) 2952 { 2953 uint32_t reg; 2954 int i; 2955 2956 AGE_LOCK_ASSERT(sc); 2957 2958 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2959 if ((reg & MAC_CFG_RX_ENB) != 0) { 2960 reg &= ~MAC_CFG_RX_ENB; 2961 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2962 } 2963 /* Stop Rx DMA engine. */ 2964 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2965 if ((reg & DMA_CFG_WR_ENB) != 0) { 2966 reg &= ~DMA_CFG_WR_ENB; 2967 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2968 } 2969 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2970 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2971 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2972 break; 2973 DELAY(10); 2974 } 2975 if (i == 0) 2976 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2977 } 2978 2979 static void 2980 age_init_tx_ring(struct age_softc *sc) 2981 { 2982 struct age_ring_data *rd; 2983 struct age_txdesc *txd; 2984 int i; 2985 2986 AGE_LOCK_ASSERT(sc); 2987 2988 sc->age_cdata.age_tx_prod = 0; 2989 sc->age_cdata.age_tx_cons = 0; 2990 sc->age_cdata.age_tx_cnt = 0; 2991 2992 rd = &sc->age_rdata; 2993 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 2994 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2995 txd = &sc->age_cdata.age_txdesc[i]; 2996 txd->tx_desc = &rd->age_tx_ring[i]; 2997 txd->tx_m = NULL; 2998 } 2999 3000 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 3001 sc->age_cdata.age_tx_ring_map, 3002 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3003 } 3004 3005 static int 3006 age_init_rx_ring(struct age_softc *sc) 3007 { 3008 struct age_ring_data *rd; 3009 struct age_rxdesc *rxd; 3010 int i; 3011 3012 AGE_LOCK_ASSERT(sc); 3013 3014 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3015 sc->age_morework = 0; 3016 rd = &sc->age_rdata; 3017 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3018 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3019 rxd = &sc->age_cdata.age_rxdesc[i]; 3020 rxd->rx_m = NULL; 3021 rxd->rx_desc = &rd->age_rx_ring[i]; 3022 if (age_newbuf(sc, rxd) != 0) 3023 return (ENOBUFS); 3024 } 3025 3026 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3027 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3028 3029 return (0); 3030 } 3031 3032 static void 3033 age_init_rr_ring(struct age_softc *sc) 3034 { 3035 struct age_ring_data *rd; 3036 3037 AGE_LOCK_ASSERT(sc); 3038 3039 sc->age_cdata.age_rr_cons = 0; 3040 AGE_RXCHAIN_RESET(sc); 3041 3042 rd = &sc->age_rdata; 3043 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3044 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3045 sc->age_cdata.age_rr_ring_map, 3046 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3047 } 3048 3049 static void 3050 age_init_cmb_block(struct age_softc *sc) 3051 { 3052 struct age_ring_data *rd; 3053 3054 AGE_LOCK_ASSERT(sc); 3055 3056 rd = &sc->age_rdata; 3057 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3058 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3059 sc->age_cdata.age_cmb_block_map, 3060 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3061 } 3062 3063 static void 3064 age_init_smb_block(struct age_softc *sc) 3065 { 3066 struct age_ring_data *rd; 3067 3068 AGE_LOCK_ASSERT(sc); 3069 3070 rd = &sc->age_rdata; 3071 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3072 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3073 sc->age_cdata.age_smb_block_map, 3074 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3075 } 3076 3077 static int 3078 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3079 { 3080 struct rx_desc *desc; 3081 struct mbuf *m; 3082 bus_dma_segment_t segs[1]; 3083 bus_dmamap_t map; 3084 int nsegs; 3085 3086 AGE_LOCK_ASSERT(sc); 3087 3088 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3089 if (m == NULL) 3090 return (ENOBUFS); 3091 m->m_len = m->m_pkthdr.len = MCLBYTES; 3092 #ifndef __NO_STRICT_ALIGNMENT 3093 m_adj(m, AGE_RX_BUF_ALIGN); 3094 #endif 3095 3096 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3097 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3098 m_freem(m); 3099 return (ENOBUFS); 3100 } 3101 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3102 3103 if (rxd->rx_m != NULL) { 3104 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3105 BUS_DMASYNC_POSTREAD); 3106 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3107 } 3108 map = rxd->rx_dmamap; 3109 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3110 sc->age_cdata.age_rx_sparemap = map; 3111 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3112 BUS_DMASYNC_PREREAD); 3113 rxd->rx_m = m; 3114 3115 desc = rxd->rx_desc; 3116 desc->addr = htole64(segs[0].ds_addr); 3117 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3118 AGE_RD_LEN_SHIFT); 3119 return (0); 3120 } 3121 3122 static void 3123 age_rxvlan(struct age_softc *sc) 3124 { 3125 if_t ifp; 3126 uint32_t reg; 3127 3128 AGE_LOCK_ASSERT(sc); 3129 3130 ifp = sc->age_ifp; 3131 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3132 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3133 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 3134 reg |= MAC_CFG_VLAN_TAG_STRIP; 3135 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3136 } 3137 3138 static u_int 3139 age_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3140 { 3141 uint32_t *mchash = arg; 3142 uint32_t crc; 3143 3144 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3145 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3146 3147 return (1); 3148 } 3149 3150 static void 3151 age_rxfilter(struct age_softc *sc) 3152 { 3153 if_t ifp; 3154 uint32_t mchash[2]; 3155 uint32_t rxcfg; 3156 3157 AGE_LOCK_ASSERT(sc); 3158 3159 ifp = sc->age_ifp; 3160 3161 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3162 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3163 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3164 rxcfg |= MAC_CFG_BCAST; 3165 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3166 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3167 rxcfg |= MAC_CFG_PROMISC; 3168 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3169 rxcfg |= MAC_CFG_ALLMULTI; 3170 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3171 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3172 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3173 return; 3174 } 3175 3176 /* Program new filter. */ 3177 bzero(mchash, sizeof(mchash)); 3178 if_foreach_llmaddr(ifp, age_hash_maddr, mchash); 3179 3180 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3181 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3182 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3183 } 3184 3185 static int 3186 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3187 { 3188 struct age_softc *sc; 3189 struct age_stats *stats; 3190 int error, result; 3191 3192 result = -1; 3193 error = sysctl_handle_int(oidp, &result, 0, req); 3194 3195 if (error != 0 || req->newptr == NULL) 3196 return (error); 3197 3198 if (result != 1) 3199 return (error); 3200 3201 sc = (struct age_softc *)arg1; 3202 stats = &sc->age_stat; 3203 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3204 printf("Transmit good frames : %ju\n", 3205 (uintmax_t)stats->tx_frames); 3206 printf("Transmit good broadcast frames : %ju\n", 3207 (uintmax_t)stats->tx_bcast_frames); 3208 printf("Transmit good multicast frames : %ju\n", 3209 (uintmax_t)stats->tx_mcast_frames); 3210 printf("Transmit pause control frames : %u\n", 3211 stats->tx_pause_frames); 3212 printf("Transmit control frames : %u\n", 3213 stats->tx_control_frames); 3214 printf("Transmit frames with excessive deferrals : %u\n", 3215 stats->tx_excess_defer); 3216 printf("Transmit deferrals : %u\n", 3217 stats->tx_deferred); 3218 printf("Transmit good octets : %ju\n", 3219 (uintmax_t)stats->tx_bytes); 3220 printf("Transmit good broadcast octets : %ju\n", 3221 (uintmax_t)stats->tx_bcast_bytes); 3222 printf("Transmit good multicast octets : %ju\n", 3223 (uintmax_t)stats->tx_mcast_bytes); 3224 printf("Transmit frames 64 bytes : %ju\n", 3225 (uintmax_t)stats->tx_pkts_64); 3226 printf("Transmit frames 65 to 127 bytes : %ju\n", 3227 (uintmax_t)stats->tx_pkts_65_127); 3228 printf("Transmit frames 128 to 255 bytes : %ju\n", 3229 (uintmax_t)stats->tx_pkts_128_255); 3230 printf("Transmit frames 256 to 511 bytes : %ju\n", 3231 (uintmax_t)stats->tx_pkts_256_511); 3232 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3233 (uintmax_t)stats->tx_pkts_512_1023); 3234 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3235 (uintmax_t)stats->tx_pkts_1024_1518); 3236 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3237 (uintmax_t)stats->tx_pkts_1519_max); 3238 printf("Transmit single collisions : %u\n", 3239 stats->tx_single_colls); 3240 printf("Transmit multiple collisions : %u\n", 3241 stats->tx_multi_colls); 3242 printf("Transmit late collisions : %u\n", 3243 stats->tx_late_colls); 3244 printf("Transmit abort due to excessive collisions : %u\n", 3245 stats->tx_excess_colls); 3246 printf("Transmit underruns due to FIFO underruns : %u\n", 3247 stats->tx_underrun); 3248 printf("Transmit descriptor write-back errors : %u\n", 3249 stats->tx_desc_underrun); 3250 printf("Transmit frames with length mismatched frame size : %u\n", 3251 stats->tx_lenerrs); 3252 printf("Transmit frames with truncated due to MTU size : %u\n", 3253 stats->tx_lenerrs); 3254 3255 printf("Receive good frames : %ju\n", 3256 (uintmax_t)stats->rx_frames); 3257 printf("Receive good broadcast frames : %ju\n", 3258 (uintmax_t)stats->rx_bcast_frames); 3259 printf("Receive good multicast frames : %ju\n", 3260 (uintmax_t)stats->rx_mcast_frames); 3261 printf("Receive pause control frames : %u\n", 3262 stats->rx_pause_frames); 3263 printf("Receive control frames : %u\n", 3264 stats->rx_control_frames); 3265 printf("Receive CRC errors : %u\n", 3266 stats->rx_crcerrs); 3267 printf("Receive frames with length errors : %u\n", 3268 stats->rx_lenerrs); 3269 printf("Receive good octets : %ju\n", 3270 (uintmax_t)stats->rx_bytes); 3271 printf("Receive good broadcast octets : %ju\n", 3272 (uintmax_t)stats->rx_bcast_bytes); 3273 printf("Receive good multicast octets : %ju\n", 3274 (uintmax_t)stats->rx_mcast_bytes); 3275 printf("Receive frames too short : %u\n", 3276 stats->rx_runts); 3277 printf("Receive fragmented frames : %ju\n", 3278 (uintmax_t)stats->rx_fragments); 3279 printf("Receive frames 64 bytes : %ju\n", 3280 (uintmax_t)stats->rx_pkts_64); 3281 printf("Receive frames 65 to 127 bytes : %ju\n", 3282 (uintmax_t)stats->rx_pkts_65_127); 3283 printf("Receive frames 128 to 255 bytes : %ju\n", 3284 (uintmax_t)stats->rx_pkts_128_255); 3285 printf("Receive frames 256 to 511 bytes : %ju\n", 3286 (uintmax_t)stats->rx_pkts_256_511); 3287 printf("Receive frames 512 to 1024 bytes : %ju\n", 3288 (uintmax_t)stats->rx_pkts_512_1023); 3289 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3290 (uintmax_t)stats->rx_pkts_1024_1518); 3291 printf("Receive frames 1519 to MTU bytes : %ju\n", 3292 (uintmax_t)stats->rx_pkts_1519_max); 3293 printf("Receive frames too long : %ju\n", 3294 (uint64_t)stats->rx_pkts_truncated); 3295 printf("Receive frames with FIFO overflow : %u\n", 3296 stats->rx_fifo_oflows); 3297 printf("Receive frames with return descriptor overflow : %u\n", 3298 stats->rx_desc_oflows); 3299 printf("Receive frames with alignment errors : %u\n", 3300 stats->rx_alignerrs); 3301 printf("Receive frames dropped due to address filtering : %ju\n", 3302 (uint64_t)stats->rx_pkts_filtered); 3303 3304 return (error); 3305 } 3306 3307 static int 3308 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3309 { 3310 int error, value; 3311 3312 if (arg1 == NULL) 3313 return (EINVAL); 3314 value = *(int *)arg1; 3315 error = sysctl_handle_int(oidp, &value, 0, req); 3316 if (error || req->newptr == NULL) 3317 return (error); 3318 if (value < low || value > high) 3319 return (EINVAL); 3320 *(int *)arg1 = value; 3321 3322 return (0); 3323 } 3324 3325 static int 3326 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3327 { 3328 return (sysctl_int_range(oidp, arg1, arg2, req, 3329 AGE_PROC_MIN, AGE_PROC_MAX)); 3330 } 3331 3332 static int 3333 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3334 { 3335 3336 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3337 AGE_IM_TIMER_MAX)); 3338 } 3339