1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Attansic Technology Corp. L1 Gigabit Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/rman.h> 41 #include <sys/module.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 #include <machine/in_cksum.h> 71 72 #include <dev/age/if_agereg.h> 73 #include <dev/age/if_agevar.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 #define AGE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 79 80 MODULE_DEPEND(age, pci, 1, 1, 1); 81 MODULE_DEPEND(age, ether, 1, 1, 1); 82 MODULE_DEPEND(age, miibus, 1, 1, 1); 83 84 /* Tunables. */ 85 static int msi_disable = 0; 86 static int msix_disable = 0; 87 TUNABLE_INT("hw.age.msi_disable", &msi_disable); 88 TUNABLE_INT("hw.age.msix_disable", &msix_disable); 89 90 /* 91 * Devices supported by this driver. 92 */ 93 static struct age_dev { 94 uint16_t age_vendorid; 95 uint16_t age_deviceid; 96 const char *age_name; 97 } age_devs[] = { 98 { VENDORID_ATTANSIC, DEVICEID_ATTANSIC_L1, 99 "Attansic Technology Corp, L1 Gigabit Ethernet" }, 100 }; 101 102 static int age_miibus_readreg(device_t, int, int); 103 static int age_miibus_writereg(device_t, int, int, int); 104 static void age_miibus_statchg(device_t); 105 static void age_mediastatus(struct ifnet *, struct ifmediareq *); 106 static int age_mediachange(struct ifnet *); 107 static int age_probe(device_t); 108 static void age_get_macaddr(struct age_softc *); 109 static void age_phy_reset(struct age_softc *); 110 static int age_attach(device_t); 111 static int age_detach(device_t); 112 static void age_sysctl_node(struct age_softc *); 113 static void age_dmamap_cb(void *, bus_dma_segment_t *, int, int); 114 static int age_check_boundary(struct age_softc *); 115 static int age_dma_alloc(struct age_softc *); 116 static void age_dma_free(struct age_softc *); 117 static int age_shutdown(device_t); 118 static void age_setwol(struct age_softc *); 119 static int age_suspend(device_t); 120 static int age_resume(device_t); 121 static int age_encap(struct age_softc *, struct mbuf **); 122 static void age_start(struct ifnet *); 123 static void age_start_locked(struct ifnet *); 124 static void age_watchdog(struct age_softc *); 125 static int age_ioctl(struct ifnet *, u_long, caddr_t); 126 static void age_mac_config(struct age_softc *); 127 static void age_link_task(void *, int); 128 static void age_stats_update(struct age_softc *); 129 static int age_intr(void *); 130 static void age_int_task(void *, int); 131 static void age_txintr(struct age_softc *, int); 132 static void age_rxeof(struct age_softc *sc, struct rx_rdesc *); 133 static int age_rxintr(struct age_softc *, int, int); 134 static void age_tick(void *); 135 static void age_reset(struct age_softc *); 136 static void age_init(void *); 137 static void age_init_locked(struct age_softc *); 138 static void age_stop(struct age_softc *); 139 static void age_stop_txmac(struct age_softc *); 140 static void age_stop_rxmac(struct age_softc *); 141 static void age_init_tx_ring(struct age_softc *); 142 static int age_init_rx_ring(struct age_softc *); 143 static void age_init_rr_ring(struct age_softc *); 144 static void age_init_cmb_block(struct age_softc *); 145 static void age_init_smb_block(struct age_softc *); 146 #ifndef __NO_STRICT_ALIGNMENT 147 static struct mbuf *age_fixup_rx(struct ifnet *, struct mbuf *); 148 #endif 149 static int age_newbuf(struct age_softc *, struct age_rxdesc *); 150 static void age_rxvlan(struct age_softc *); 151 static void age_rxfilter(struct age_softc *); 152 static int sysctl_age_stats(SYSCTL_HANDLER_ARGS); 153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154 static int sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS); 155 static int sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS); 156 157 158 static device_method_t age_methods[] = { 159 /* Device interface. */ 160 DEVMETHOD(device_probe, age_probe), 161 DEVMETHOD(device_attach, age_attach), 162 DEVMETHOD(device_detach, age_detach), 163 DEVMETHOD(device_shutdown, age_shutdown), 164 DEVMETHOD(device_suspend, age_suspend), 165 DEVMETHOD(device_resume, age_resume), 166 167 /* MII interface. */ 168 DEVMETHOD(miibus_readreg, age_miibus_readreg), 169 DEVMETHOD(miibus_writereg, age_miibus_writereg), 170 DEVMETHOD(miibus_statchg, age_miibus_statchg), 171 172 { NULL, NULL } 173 }; 174 175 static driver_t age_driver = { 176 "age", 177 age_methods, 178 sizeof(struct age_softc) 179 }; 180 181 static devclass_t age_devclass; 182 183 DRIVER_MODULE(age, pci, age_driver, age_devclass, 0, 0); 184 DRIVER_MODULE(miibus, age, miibus_driver, miibus_devclass, 0, 0); 185 186 static struct resource_spec age_res_spec_mem[] = { 187 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 188 { -1, 0, 0 } 189 }; 190 191 static struct resource_spec age_irq_spec_legacy[] = { 192 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 193 { -1, 0, 0 } 194 }; 195 196 static struct resource_spec age_irq_spec_msi[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static struct resource_spec age_irq_spec_msix[] = { 202 { SYS_RES_IRQ, 1, RF_ACTIVE }, 203 { -1, 0, 0 } 204 }; 205 206 /* 207 * Read a PHY register on the MII of the L1. 208 */ 209 static int 210 age_miibus_readreg(device_t dev, int phy, int reg) 211 { 212 struct age_softc *sc; 213 uint32_t v; 214 int i; 215 216 sc = device_get_softc(dev); 217 218 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 219 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 220 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 221 DELAY(1); 222 v = CSR_READ_4(sc, AGE_MDIO); 223 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 224 break; 225 } 226 227 if (i == 0) { 228 device_printf(sc->age_dev, "phy read timeout : %d\n", reg); 229 return (0); 230 } 231 232 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 233 } 234 235 /* 236 * Write a PHY register on the MII of the L1. 237 */ 238 static int 239 age_miibus_writereg(device_t dev, int phy, int reg, int val) 240 { 241 struct age_softc *sc; 242 uint32_t v; 243 int i; 244 245 sc = device_get_softc(dev); 246 247 CSR_WRITE_4(sc, AGE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 248 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 249 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 250 for (i = AGE_PHY_TIMEOUT; i > 0; i--) { 251 DELAY(1); 252 v = CSR_READ_4(sc, AGE_MDIO); 253 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 254 break; 255 } 256 257 if (i == 0) 258 device_printf(sc->age_dev, "phy write timeout : %d\n", reg); 259 260 return (0); 261 } 262 263 /* 264 * Callback from MII layer when media changes. 265 */ 266 static void 267 age_miibus_statchg(device_t dev) 268 { 269 struct age_softc *sc; 270 271 sc = device_get_softc(dev); 272 taskqueue_enqueue(taskqueue_swi, &sc->age_link_task); 273 } 274 275 /* 276 * Get the current interface media status. 277 */ 278 static void 279 age_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 280 { 281 struct age_softc *sc; 282 struct mii_data *mii; 283 284 sc = ifp->if_softc; 285 AGE_LOCK(sc); 286 mii = device_get_softc(sc->age_miibus); 287 288 mii_pollstat(mii); 289 ifmr->ifm_status = mii->mii_media_status; 290 ifmr->ifm_active = mii->mii_media_active; 291 AGE_UNLOCK(sc); 292 } 293 294 /* 295 * Set hardware to newly-selected media. 296 */ 297 static int 298 age_mediachange(struct ifnet *ifp) 299 { 300 struct age_softc *sc; 301 struct mii_data *mii; 302 struct mii_softc *miisc; 303 int error; 304 305 sc = ifp->if_softc; 306 AGE_LOCK(sc); 307 mii = device_get_softc(sc->age_miibus); 308 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 309 PHY_RESET(miisc); 310 error = mii_mediachg(mii); 311 AGE_UNLOCK(sc); 312 313 return (error); 314 } 315 316 static int 317 age_probe(device_t dev) 318 { 319 struct age_dev *sp; 320 int i; 321 uint16_t vendor, devid; 322 323 vendor = pci_get_vendor(dev); 324 devid = pci_get_device(dev); 325 sp = age_devs; 326 for (i = 0; i < sizeof(age_devs) / sizeof(age_devs[0]); 327 i++, sp++) { 328 if (vendor == sp->age_vendorid && 329 devid == sp->age_deviceid) { 330 device_set_desc(dev, sp->age_name); 331 return (BUS_PROBE_DEFAULT); 332 } 333 } 334 335 return (ENXIO); 336 } 337 338 static void 339 age_get_macaddr(struct age_softc *sc) 340 { 341 uint32_t ea[2], reg; 342 int i, vpdc; 343 344 reg = CSR_READ_4(sc, AGE_SPI_CTRL); 345 if ((reg & SPI_VPD_ENB) != 0) { 346 /* Get VPD stored in TWSI EEPROM. */ 347 reg &= ~SPI_VPD_ENB; 348 CSR_WRITE_4(sc, AGE_SPI_CTRL, reg); 349 } 350 351 if (pci_find_cap(sc->age_dev, PCIY_VPD, &vpdc) == 0) { 352 /* 353 * PCI VPD capability found, let TWSI reload EEPROM. 354 * This will set ethernet address of controller. 355 */ 356 CSR_WRITE_4(sc, AGE_TWSI_CTRL, CSR_READ_4(sc, AGE_TWSI_CTRL) | 357 TWSI_CTRL_SW_LD_START); 358 for (i = 100; i > 0; i--) { 359 DELAY(1000); 360 reg = CSR_READ_4(sc, AGE_TWSI_CTRL); 361 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 362 break; 363 } 364 if (i == 0) 365 device_printf(sc->age_dev, 366 "reloading EEPROM timeout!\n"); 367 } else { 368 if (bootverbose) 369 device_printf(sc->age_dev, 370 "PCI VPD capability not found!\n"); 371 } 372 373 ea[0] = CSR_READ_4(sc, AGE_PAR0); 374 ea[1] = CSR_READ_4(sc, AGE_PAR1); 375 sc->age_eaddr[0] = (ea[1] >> 8) & 0xFF; 376 sc->age_eaddr[1] = (ea[1] >> 0) & 0xFF; 377 sc->age_eaddr[2] = (ea[0] >> 24) & 0xFF; 378 sc->age_eaddr[3] = (ea[0] >> 16) & 0xFF; 379 sc->age_eaddr[4] = (ea[0] >> 8) & 0xFF; 380 sc->age_eaddr[5] = (ea[0] >> 0) & 0xFF; 381 } 382 383 static void 384 age_phy_reset(struct age_softc *sc) 385 { 386 uint16_t reg, pn; 387 int i, linkup; 388 389 /* Reset PHY. */ 390 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_RST); 391 DELAY(2000); 392 CSR_WRITE_4(sc, AGE_GPHY_CTRL, GPHY_CTRL_CLR); 393 DELAY(2000); 394 395 #define ATPHY_DBG_ADDR 0x1D 396 #define ATPHY_DBG_DATA 0x1E 397 #define ATPHY_CDTC 0x16 398 #define PHY_CDTC_ENB 0x0001 399 #define PHY_CDTC_POFF 8 400 #define ATPHY_CDTS 0x1C 401 #define PHY_CDTS_STAT_OK 0x0000 402 #define PHY_CDTS_STAT_SHORT 0x0100 403 #define PHY_CDTS_STAT_OPEN 0x0200 404 #define PHY_CDTS_STAT_INVAL 0x0300 405 #define PHY_CDTS_STAT_MASK 0x0300 406 407 /* Check power saving mode. Magic from Linux. */ 408 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET); 409 for (linkup = 0, pn = 0; pn < 4; pn++) { 410 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, ATPHY_CDTC, 411 (pn << PHY_CDTC_POFF) | PHY_CDTC_ENB); 412 for (i = 200; i > 0; i--) { 413 DELAY(1000); 414 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 415 ATPHY_CDTC); 416 if ((reg & PHY_CDTC_ENB) == 0) 417 break; 418 } 419 DELAY(1000); 420 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 421 ATPHY_CDTS); 422 if ((reg & PHY_CDTS_STAT_MASK) != PHY_CDTS_STAT_OPEN) { 423 linkup++; 424 break; 425 } 426 } 427 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, 428 BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 429 if (linkup == 0) { 430 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 431 ATPHY_DBG_ADDR, 0); 432 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 433 ATPHY_DBG_DATA, 0x124E); 434 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 435 ATPHY_DBG_ADDR, 1); 436 reg = age_miibus_readreg(sc->age_dev, sc->age_phyaddr, 437 ATPHY_DBG_DATA); 438 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 439 ATPHY_DBG_DATA, reg | 0x03); 440 /* XXX */ 441 DELAY(1500 * 1000); 442 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 443 ATPHY_DBG_ADDR, 0); 444 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 445 ATPHY_DBG_DATA, 0x024E); 446 } 447 448 #undef ATPHY_DBG_ADDR 449 #undef ATPHY_DBG_DATA 450 #undef ATPHY_CDTC 451 #undef PHY_CDTC_ENB 452 #undef PHY_CDTC_POFF 453 #undef ATPHY_CDTS 454 #undef PHY_CDTS_STAT_OK 455 #undef PHY_CDTS_STAT_SHORT 456 #undef PHY_CDTS_STAT_OPEN 457 #undef PHY_CDTS_STAT_INVAL 458 #undef PHY_CDTS_STAT_MASK 459 } 460 461 static int 462 age_attach(device_t dev) 463 { 464 struct age_softc *sc; 465 struct ifnet *ifp; 466 uint16_t burst; 467 int error, i, msic, msixc, pmc; 468 469 error = 0; 470 sc = device_get_softc(dev); 471 sc->age_dev = dev; 472 473 mtx_init(&sc->age_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 474 MTX_DEF); 475 callout_init_mtx(&sc->age_tick_ch, &sc->age_mtx, 0); 476 TASK_INIT(&sc->age_int_task, 0, age_int_task, sc); 477 TASK_INIT(&sc->age_link_task, 0, age_link_task, sc); 478 479 /* Map the device. */ 480 pci_enable_busmaster(dev); 481 sc->age_res_spec = age_res_spec_mem; 482 sc->age_irq_spec = age_irq_spec_legacy; 483 error = bus_alloc_resources(dev, sc->age_res_spec, sc->age_res); 484 if (error != 0) { 485 device_printf(dev, "cannot allocate memory resources.\n"); 486 goto fail; 487 } 488 489 /* Set PHY address. */ 490 sc->age_phyaddr = AGE_PHY_ADDR; 491 492 /* Reset PHY. */ 493 age_phy_reset(sc); 494 495 /* Reset the ethernet controller. */ 496 age_reset(sc); 497 498 /* Get PCI and chip id/revision. */ 499 sc->age_rev = pci_get_revid(dev); 500 sc->age_chip_rev = CSR_READ_4(sc, AGE_MASTER_CFG) >> 501 MASTER_CHIP_REV_SHIFT; 502 if (bootverbose) { 503 device_printf(dev, "PCI device revision : 0x%04x\n", 504 sc->age_rev); 505 device_printf(dev, "Chip id/revision : 0x%04x\n", 506 sc->age_chip_rev); 507 } 508 509 /* 510 * XXX 511 * Unintialized hardware returns an invalid chip id/revision 512 * as well as 0xFFFFFFFF for Tx/Rx fifo length. It seems that 513 * unplugged cable results in putting hardware into automatic 514 * power down mode which in turn returns invalld chip revision. 515 */ 516 if (sc->age_chip_rev == 0xFFFF) { 517 device_printf(dev,"invalid chip revision : 0x%04x -- " 518 "not initialized?\n", sc->age_chip_rev); 519 error = ENXIO; 520 goto fail; 521 } 522 523 device_printf(dev, "%d Tx FIFO, %d Rx FIFO\n", 524 CSR_READ_4(sc, AGE_SRAM_TX_FIFO_LEN), 525 CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN)); 526 527 /* Allocate IRQ resources. */ 528 msixc = pci_msix_count(dev); 529 msic = pci_msi_count(dev); 530 if (bootverbose) { 531 device_printf(dev, "MSIX count : %d\n", msixc); 532 device_printf(dev, "MSI count : %d\n", msic); 533 } 534 535 /* Prefer MSIX over MSI. */ 536 if (msix_disable == 0 || msi_disable == 0) { 537 if (msix_disable == 0 && msixc == AGE_MSIX_MESSAGES && 538 pci_alloc_msix(dev, &msixc) == 0) { 539 if (msic == AGE_MSIX_MESSAGES) { 540 device_printf(dev, "Using %d MSIX messages.\n", 541 msixc); 542 sc->age_flags |= AGE_FLAG_MSIX; 543 sc->age_irq_spec = age_irq_spec_msix; 544 } else 545 pci_release_msi(dev); 546 } 547 if (msi_disable == 0 && (sc->age_flags & AGE_FLAG_MSIX) == 0 && 548 msic == AGE_MSI_MESSAGES && 549 pci_alloc_msi(dev, &msic) == 0) { 550 if (msic == AGE_MSI_MESSAGES) { 551 device_printf(dev, "Using %d MSI messages.\n", 552 msic); 553 sc->age_flags |= AGE_FLAG_MSI; 554 sc->age_irq_spec = age_irq_spec_msi; 555 } else 556 pci_release_msi(dev); 557 } 558 } 559 560 error = bus_alloc_resources(dev, sc->age_irq_spec, sc->age_irq); 561 if (error != 0) { 562 device_printf(dev, "cannot allocate IRQ resources.\n"); 563 goto fail; 564 } 565 566 567 /* Get DMA parameters from PCIe device control register. */ 568 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 569 sc->age_flags |= AGE_FLAG_PCIE; 570 burst = pci_read_config(dev, i + 0x08, 2); 571 /* Max read request size. */ 572 sc->age_dma_rd_burst = ((burst >> 12) & 0x07) << 573 DMA_CFG_RD_BURST_SHIFT; 574 /* Max payload size. */ 575 sc->age_dma_wr_burst = ((burst >> 5) & 0x07) << 576 DMA_CFG_WR_BURST_SHIFT; 577 if (bootverbose) { 578 device_printf(dev, "Read request size : %d bytes.\n", 579 128 << ((burst >> 12) & 0x07)); 580 device_printf(dev, "TLP payload size : %d bytes.\n", 581 128 << ((burst >> 5) & 0x07)); 582 } 583 } else { 584 sc->age_dma_rd_burst = DMA_CFG_RD_BURST_128; 585 sc->age_dma_wr_burst = DMA_CFG_WR_BURST_128; 586 } 587 588 /* Create device sysctl node. */ 589 age_sysctl_node(sc); 590 591 if ((error = age_dma_alloc(sc)) != 0) 592 goto fail; 593 594 /* Load station address. */ 595 age_get_macaddr(sc); 596 597 ifp = sc->age_ifp = if_alloc(IFT_ETHER); 598 if (ifp == NULL) { 599 device_printf(dev, "cannot allocate ifnet structure.\n"); 600 error = ENXIO; 601 goto fail; 602 } 603 604 ifp->if_softc = sc; 605 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 606 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 607 ifp->if_ioctl = age_ioctl; 608 ifp->if_start = age_start; 609 ifp->if_init = age_init; 610 ifp->if_snd.ifq_drv_maxlen = AGE_TX_RING_CNT - 1; 611 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 612 IFQ_SET_READY(&ifp->if_snd); 613 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 614 ifp->if_hwassist = AGE_CSUM_FEATURES | CSUM_TSO; 615 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 616 sc->age_flags |= AGE_FLAG_PMCAP; 617 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 618 } 619 ifp->if_capenable = ifp->if_capabilities; 620 621 /* Set up MII bus. */ 622 error = mii_attach(dev, &sc->age_miibus, ifp, age_mediachange, 623 age_mediastatus, BMSR_DEFCAPMASK, sc->age_phyaddr, MII_OFFSET_ANY, 624 0); 625 if (error != 0) { 626 device_printf(dev, "attaching PHYs failed\n"); 627 goto fail; 628 } 629 630 ether_ifattach(ifp, sc->age_eaddr); 631 632 /* VLAN capability setup. */ 633 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 634 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 635 ifp->if_capenable = ifp->if_capabilities; 636 637 /* Tell the upper layer(s) we support long frames. */ 638 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 639 640 /* Create local taskq. */ 641 sc->age_tq = taskqueue_create_fast("age_taskq", M_WAITOK, 642 taskqueue_thread_enqueue, &sc->age_tq); 643 if (sc->age_tq == NULL) { 644 device_printf(dev, "could not create taskqueue.\n"); 645 ether_ifdetach(ifp); 646 error = ENXIO; 647 goto fail; 648 } 649 taskqueue_start_threads(&sc->age_tq, 1, PI_NET, "%s taskq", 650 device_get_nameunit(sc->age_dev)); 651 652 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 653 msic = AGE_MSIX_MESSAGES; 654 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 655 msic = AGE_MSI_MESSAGES; 656 else 657 msic = 1; 658 for (i = 0; i < msic; i++) { 659 error = bus_setup_intr(dev, sc->age_irq[i], 660 INTR_TYPE_NET | INTR_MPSAFE, age_intr, NULL, sc, 661 &sc->age_intrhand[i]); 662 if (error != 0) 663 break; 664 } 665 if (error != 0) { 666 device_printf(dev, "could not set up interrupt handler.\n"); 667 taskqueue_free(sc->age_tq); 668 sc->age_tq = NULL; 669 ether_ifdetach(ifp); 670 goto fail; 671 } 672 673 fail: 674 if (error != 0) 675 age_detach(dev); 676 677 return (error); 678 } 679 680 static int 681 age_detach(device_t dev) 682 { 683 struct age_softc *sc; 684 struct ifnet *ifp; 685 int i, msic; 686 687 sc = device_get_softc(dev); 688 689 ifp = sc->age_ifp; 690 if (device_is_attached(dev)) { 691 AGE_LOCK(sc); 692 sc->age_flags |= AGE_FLAG_DETACH; 693 age_stop(sc); 694 AGE_UNLOCK(sc); 695 callout_drain(&sc->age_tick_ch); 696 taskqueue_drain(sc->age_tq, &sc->age_int_task); 697 taskqueue_drain(taskqueue_swi, &sc->age_link_task); 698 ether_ifdetach(ifp); 699 } 700 701 if (sc->age_tq != NULL) { 702 taskqueue_drain(sc->age_tq, &sc->age_int_task); 703 taskqueue_free(sc->age_tq); 704 sc->age_tq = NULL; 705 } 706 707 if (sc->age_miibus != NULL) { 708 device_delete_child(dev, sc->age_miibus); 709 sc->age_miibus = NULL; 710 } 711 bus_generic_detach(dev); 712 age_dma_free(sc); 713 714 if (ifp != NULL) { 715 if_free(ifp); 716 sc->age_ifp = NULL; 717 } 718 719 if ((sc->age_flags & AGE_FLAG_MSIX) != 0) 720 msic = AGE_MSIX_MESSAGES; 721 else if ((sc->age_flags & AGE_FLAG_MSI) != 0) 722 msic = AGE_MSI_MESSAGES; 723 else 724 msic = 1; 725 for (i = 0; i < msic; i++) { 726 if (sc->age_intrhand[i] != NULL) { 727 bus_teardown_intr(dev, sc->age_irq[i], 728 sc->age_intrhand[i]); 729 sc->age_intrhand[i] = NULL; 730 } 731 } 732 733 bus_release_resources(dev, sc->age_irq_spec, sc->age_irq); 734 if ((sc->age_flags & (AGE_FLAG_MSI | AGE_FLAG_MSIX)) != 0) 735 pci_release_msi(dev); 736 bus_release_resources(dev, sc->age_res_spec, sc->age_res); 737 mtx_destroy(&sc->age_mtx); 738 739 return (0); 740 } 741 742 static void 743 age_sysctl_node(struct age_softc *sc) 744 { 745 int error; 746 747 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 748 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 749 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_age_stats, 750 "I", "Statistics"); 751 752 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 753 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 754 "int_mod", CTLTYPE_INT | CTLFLAG_RW, &sc->age_int_mod, 0, 755 sysctl_hw_age_int_mod, "I", "age interrupt moderation"); 756 757 /* Pull in device tunables. */ 758 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 759 error = resource_int_value(device_get_name(sc->age_dev), 760 device_get_unit(sc->age_dev), "int_mod", &sc->age_int_mod); 761 if (error == 0) { 762 if (sc->age_int_mod < AGE_IM_TIMER_MIN || 763 sc->age_int_mod > AGE_IM_TIMER_MAX) { 764 device_printf(sc->age_dev, 765 "int_mod value out of range; using default: %d\n", 766 AGE_IM_TIMER_DEFAULT); 767 sc->age_int_mod = AGE_IM_TIMER_DEFAULT; 768 } 769 } 770 771 SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->age_dev), 772 SYSCTL_CHILDREN(device_get_sysctl_tree(sc->age_dev)), OID_AUTO, 773 "process_limit", CTLTYPE_INT | CTLFLAG_RW, &sc->age_process_limit, 774 0, sysctl_hw_age_proc_limit, "I", 775 "max number of Rx events to process"); 776 777 /* Pull in device tunables. */ 778 sc->age_process_limit = AGE_PROC_DEFAULT; 779 error = resource_int_value(device_get_name(sc->age_dev), 780 device_get_unit(sc->age_dev), "process_limit", 781 &sc->age_process_limit); 782 if (error == 0) { 783 if (sc->age_process_limit < AGE_PROC_MIN || 784 sc->age_process_limit > AGE_PROC_MAX) { 785 device_printf(sc->age_dev, 786 "process_limit value out of range; " 787 "using default: %d\n", AGE_PROC_DEFAULT); 788 sc->age_process_limit = AGE_PROC_DEFAULT; 789 } 790 } 791 } 792 793 struct age_dmamap_arg { 794 bus_addr_t age_busaddr; 795 }; 796 797 static void 798 age_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 799 { 800 struct age_dmamap_arg *ctx; 801 802 if (error != 0) 803 return; 804 805 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 806 807 ctx = (struct age_dmamap_arg *)arg; 808 ctx->age_busaddr = segs[0].ds_addr; 809 } 810 811 /* 812 * Attansic L1 controller have single register to specify high 813 * address part of DMA blocks. So all descriptor structures and 814 * DMA memory blocks should have the same high address of given 815 * 4GB address space(i.e. crossing 4GB boundary is not allowed). 816 */ 817 static int 818 age_check_boundary(struct age_softc *sc) 819 { 820 bus_addr_t rx_ring_end, rr_ring_end, tx_ring_end; 821 bus_addr_t cmb_block_end, smb_block_end; 822 823 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 824 tx_ring_end = sc->age_rdata.age_tx_ring_paddr + AGE_TX_RING_SZ; 825 rx_ring_end = sc->age_rdata.age_rx_ring_paddr + AGE_RX_RING_SZ; 826 rr_ring_end = sc->age_rdata.age_rr_ring_paddr + AGE_RR_RING_SZ; 827 cmb_block_end = sc->age_rdata.age_cmb_block_paddr + AGE_CMB_BLOCK_SZ; 828 smb_block_end = sc->age_rdata.age_smb_block_paddr + AGE_SMB_BLOCK_SZ; 829 830 if ((AGE_ADDR_HI(tx_ring_end) != 831 AGE_ADDR_HI(sc->age_rdata.age_tx_ring_paddr)) || 832 (AGE_ADDR_HI(rx_ring_end) != 833 AGE_ADDR_HI(sc->age_rdata.age_rx_ring_paddr)) || 834 (AGE_ADDR_HI(rr_ring_end) != 835 AGE_ADDR_HI(sc->age_rdata.age_rr_ring_paddr)) || 836 (AGE_ADDR_HI(cmb_block_end) != 837 AGE_ADDR_HI(sc->age_rdata.age_cmb_block_paddr)) || 838 (AGE_ADDR_HI(smb_block_end) != 839 AGE_ADDR_HI(sc->age_rdata.age_smb_block_paddr))) 840 return (EFBIG); 841 842 if ((AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rx_ring_end)) || 843 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(rr_ring_end)) || 844 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(cmb_block_end)) || 845 (AGE_ADDR_HI(tx_ring_end) != AGE_ADDR_HI(smb_block_end))) 846 return (EFBIG); 847 848 return (0); 849 } 850 851 static int 852 age_dma_alloc(struct age_softc *sc) 853 { 854 struct age_txdesc *txd; 855 struct age_rxdesc *rxd; 856 bus_addr_t lowaddr; 857 struct age_dmamap_arg ctx; 858 int error, i; 859 860 lowaddr = BUS_SPACE_MAXADDR; 861 862 again: 863 /* Create parent ring/DMA block tag. */ 864 error = bus_dma_tag_create( 865 bus_get_dma_tag(sc->age_dev), /* parent */ 866 1, 0, /* alignment, boundary */ 867 lowaddr, /* lowaddr */ 868 BUS_SPACE_MAXADDR, /* highaddr */ 869 NULL, NULL, /* filter, filterarg */ 870 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 871 0, /* nsegments */ 872 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 873 0, /* flags */ 874 NULL, NULL, /* lockfunc, lockarg */ 875 &sc->age_cdata.age_parent_tag); 876 if (error != 0) { 877 device_printf(sc->age_dev, 878 "could not create parent DMA tag.\n"); 879 goto fail; 880 } 881 882 /* Create tag for Tx ring. */ 883 error = bus_dma_tag_create( 884 sc->age_cdata.age_parent_tag, /* parent */ 885 AGE_TX_RING_ALIGN, 0, /* alignment, boundary */ 886 BUS_SPACE_MAXADDR, /* lowaddr */ 887 BUS_SPACE_MAXADDR, /* highaddr */ 888 NULL, NULL, /* filter, filterarg */ 889 AGE_TX_RING_SZ, /* maxsize */ 890 1, /* nsegments */ 891 AGE_TX_RING_SZ, /* maxsegsize */ 892 0, /* flags */ 893 NULL, NULL, /* lockfunc, lockarg */ 894 &sc->age_cdata.age_tx_ring_tag); 895 if (error != 0) { 896 device_printf(sc->age_dev, 897 "could not create Tx ring DMA tag.\n"); 898 goto fail; 899 } 900 901 /* Create tag for Rx ring. */ 902 error = bus_dma_tag_create( 903 sc->age_cdata.age_parent_tag, /* parent */ 904 AGE_RX_RING_ALIGN, 0, /* alignment, boundary */ 905 BUS_SPACE_MAXADDR, /* lowaddr */ 906 BUS_SPACE_MAXADDR, /* highaddr */ 907 NULL, NULL, /* filter, filterarg */ 908 AGE_RX_RING_SZ, /* maxsize */ 909 1, /* nsegments */ 910 AGE_RX_RING_SZ, /* maxsegsize */ 911 0, /* flags */ 912 NULL, NULL, /* lockfunc, lockarg */ 913 &sc->age_cdata.age_rx_ring_tag); 914 if (error != 0) { 915 device_printf(sc->age_dev, 916 "could not create Rx ring DMA tag.\n"); 917 goto fail; 918 } 919 920 /* Create tag for Rx return ring. */ 921 error = bus_dma_tag_create( 922 sc->age_cdata.age_parent_tag, /* parent */ 923 AGE_RR_RING_ALIGN, 0, /* alignment, boundary */ 924 BUS_SPACE_MAXADDR, /* lowaddr */ 925 BUS_SPACE_MAXADDR, /* highaddr */ 926 NULL, NULL, /* filter, filterarg */ 927 AGE_RR_RING_SZ, /* maxsize */ 928 1, /* nsegments */ 929 AGE_RR_RING_SZ, /* maxsegsize */ 930 0, /* flags */ 931 NULL, NULL, /* lockfunc, lockarg */ 932 &sc->age_cdata.age_rr_ring_tag); 933 if (error != 0) { 934 device_printf(sc->age_dev, 935 "could not create Rx return ring DMA tag.\n"); 936 goto fail; 937 } 938 939 /* Create tag for coalesing message block. */ 940 error = bus_dma_tag_create( 941 sc->age_cdata.age_parent_tag, /* parent */ 942 AGE_CMB_ALIGN, 0, /* alignment, boundary */ 943 BUS_SPACE_MAXADDR, /* lowaddr */ 944 BUS_SPACE_MAXADDR, /* highaddr */ 945 NULL, NULL, /* filter, filterarg */ 946 AGE_CMB_BLOCK_SZ, /* maxsize */ 947 1, /* nsegments */ 948 AGE_CMB_BLOCK_SZ, /* maxsegsize */ 949 0, /* flags */ 950 NULL, NULL, /* lockfunc, lockarg */ 951 &sc->age_cdata.age_cmb_block_tag); 952 if (error != 0) { 953 device_printf(sc->age_dev, 954 "could not create CMB DMA tag.\n"); 955 goto fail; 956 } 957 958 /* Create tag for statistics message block. */ 959 error = bus_dma_tag_create( 960 sc->age_cdata.age_parent_tag, /* parent */ 961 AGE_SMB_ALIGN, 0, /* alignment, boundary */ 962 BUS_SPACE_MAXADDR, /* lowaddr */ 963 BUS_SPACE_MAXADDR, /* highaddr */ 964 NULL, NULL, /* filter, filterarg */ 965 AGE_SMB_BLOCK_SZ, /* maxsize */ 966 1, /* nsegments */ 967 AGE_SMB_BLOCK_SZ, /* maxsegsize */ 968 0, /* flags */ 969 NULL, NULL, /* lockfunc, lockarg */ 970 &sc->age_cdata.age_smb_block_tag); 971 if (error != 0) { 972 device_printf(sc->age_dev, 973 "could not create SMB DMA tag.\n"); 974 goto fail; 975 } 976 977 /* Allocate DMA'able memory and load the DMA map. */ 978 error = bus_dmamem_alloc(sc->age_cdata.age_tx_ring_tag, 979 (void **)&sc->age_rdata.age_tx_ring, 980 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 981 &sc->age_cdata.age_tx_ring_map); 982 if (error != 0) { 983 device_printf(sc->age_dev, 984 "could not allocate DMA'able memory for Tx ring.\n"); 985 goto fail; 986 } 987 ctx.age_busaddr = 0; 988 error = bus_dmamap_load(sc->age_cdata.age_tx_ring_tag, 989 sc->age_cdata.age_tx_ring_map, sc->age_rdata.age_tx_ring, 990 AGE_TX_RING_SZ, age_dmamap_cb, &ctx, 0); 991 if (error != 0 || ctx.age_busaddr == 0) { 992 device_printf(sc->age_dev, 993 "could not load DMA'able memory for Tx ring.\n"); 994 goto fail; 995 } 996 sc->age_rdata.age_tx_ring_paddr = ctx.age_busaddr; 997 /* Rx ring */ 998 error = bus_dmamem_alloc(sc->age_cdata.age_rx_ring_tag, 999 (void **)&sc->age_rdata.age_rx_ring, 1000 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1001 &sc->age_cdata.age_rx_ring_map); 1002 if (error != 0) { 1003 device_printf(sc->age_dev, 1004 "could not allocate DMA'able memory for Rx ring.\n"); 1005 goto fail; 1006 } 1007 ctx.age_busaddr = 0; 1008 error = bus_dmamap_load(sc->age_cdata.age_rx_ring_tag, 1009 sc->age_cdata.age_rx_ring_map, sc->age_rdata.age_rx_ring, 1010 AGE_RX_RING_SZ, age_dmamap_cb, &ctx, 0); 1011 if (error != 0 || ctx.age_busaddr == 0) { 1012 device_printf(sc->age_dev, 1013 "could not load DMA'able memory for Rx ring.\n"); 1014 goto fail; 1015 } 1016 sc->age_rdata.age_rx_ring_paddr = ctx.age_busaddr; 1017 /* Rx return ring */ 1018 error = bus_dmamem_alloc(sc->age_cdata.age_rr_ring_tag, 1019 (void **)&sc->age_rdata.age_rr_ring, 1020 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1021 &sc->age_cdata.age_rr_ring_map); 1022 if (error != 0) { 1023 device_printf(sc->age_dev, 1024 "could not allocate DMA'able memory for Rx return ring.\n"); 1025 goto fail; 1026 } 1027 ctx.age_busaddr = 0; 1028 error = bus_dmamap_load(sc->age_cdata.age_rr_ring_tag, 1029 sc->age_cdata.age_rr_ring_map, sc->age_rdata.age_rr_ring, 1030 AGE_RR_RING_SZ, age_dmamap_cb, 1031 &ctx, 0); 1032 if (error != 0 || ctx.age_busaddr == 0) { 1033 device_printf(sc->age_dev, 1034 "could not load DMA'able memory for Rx return ring.\n"); 1035 goto fail; 1036 } 1037 sc->age_rdata.age_rr_ring_paddr = ctx.age_busaddr; 1038 /* CMB block */ 1039 error = bus_dmamem_alloc(sc->age_cdata.age_cmb_block_tag, 1040 (void **)&sc->age_rdata.age_cmb_block, 1041 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1042 &sc->age_cdata.age_cmb_block_map); 1043 if (error != 0) { 1044 device_printf(sc->age_dev, 1045 "could not allocate DMA'able memory for CMB block.\n"); 1046 goto fail; 1047 } 1048 ctx.age_busaddr = 0; 1049 error = bus_dmamap_load(sc->age_cdata.age_cmb_block_tag, 1050 sc->age_cdata.age_cmb_block_map, sc->age_rdata.age_cmb_block, 1051 AGE_CMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1052 if (error != 0 || ctx.age_busaddr == 0) { 1053 device_printf(sc->age_dev, 1054 "could not load DMA'able memory for CMB block.\n"); 1055 goto fail; 1056 } 1057 sc->age_rdata.age_cmb_block_paddr = ctx.age_busaddr; 1058 /* SMB block */ 1059 error = bus_dmamem_alloc(sc->age_cdata.age_smb_block_tag, 1060 (void **)&sc->age_rdata.age_smb_block, 1061 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1062 &sc->age_cdata.age_smb_block_map); 1063 if (error != 0) { 1064 device_printf(sc->age_dev, 1065 "could not allocate DMA'able memory for SMB block.\n"); 1066 goto fail; 1067 } 1068 ctx.age_busaddr = 0; 1069 error = bus_dmamap_load(sc->age_cdata.age_smb_block_tag, 1070 sc->age_cdata.age_smb_block_map, sc->age_rdata.age_smb_block, 1071 AGE_SMB_BLOCK_SZ, age_dmamap_cb, &ctx, 0); 1072 if (error != 0 || ctx.age_busaddr == 0) { 1073 device_printf(sc->age_dev, 1074 "could not load DMA'able memory for SMB block.\n"); 1075 goto fail; 1076 } 1077 sc->age_rdata.age_smb_block_paddr = ctx.age_busaddr; 1078 1079 /* 1080 * All ring buffer and DMA blocks should have the same 1081 * high address part of 64bit DMA address space. 1082 */ 1083 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1084 (error = age_check_boundary(sc)) != 0) { 1085 device_printf(sc->age_dev, "4GB boundary crossed, " 1086 "switching to 32bit DMA addressing mode.\n"); 1087 age_dma_free(sc); 1088 /* Limit DMA address space to 32bit and try again. */ 1089 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1090 goto again; 1091 } 1092 1093 /* 1094 * Create Tx/Rx buffer parent tag. 1095 * L1 supports full 64bit DMA addressing in Tx/Rx buffers 1096 * so it needs separate parent DMA tag. 1097 * XXX 1098 * It seems enabling 64bit DMA causes data corruption. Limit 1099 * DMA address space to 32bit. 1100 */ 1101 error = bus_dma_tag_create( 1102 bus_get_dma_tag(sc->age_dev), /* parent */ 1103 1, 0, /* alignment, boundary */ 1104 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1105 BUS_SPACE_MAXADDR, /* highaddr */ 1106 NULL, NULL, /* filter, filterarg */ 1107 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1108 0, /* nsegments */ 1109 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1110 0, /* flags */ 1111 NULL, NULL, /* lockfunc, lockarg */ 1112 &sc->age_cdata.age_buffer_tag); 1113 if (error != 0) { 1114 device_printf(sc->age_dev, 1115 "could not create parent buffer DMA tag.\n"); 1116 goto fail; 1117 } 1118 1119 /* Create tag for Tx buffers. */ 1120 error = bus_dma_tag_create( 1121 sc->age_cdata.age_buffer_tag, /* parent */ 1122 1, 0, /* alignment, boundary */ 1123 BUS_SPACE_MAXADDR, /* lowaddr */ 1124 BUS_SPACE_MAXADDR, /* highaddr */ 1125 NULL, NULL, /* filter, filterarg */ 1126 AGE_TSO_MAXSIZE, /* maxsize */ 1127 AGE_MAXTXSEGS, /* nsegments */ 1128 AGE_TSO_MAXSEGSIZE, /* maxsegsize */ 1129 0, /* flags */ 1130 NULL, NULL, /* lockfunc, lockarg */ 1131 &sc->age_cdata.age_tx_tag); 1132 if (error != 0) { 1133 device_printf(sc->age_dev, "could not create Tx DMA tag.\n"); 1134 goto fail; 1135 } 1136 1137 /* Create tag for Rx buffers. */ 1138 error = bus_dma_tag_create( 1139 sc->age_cdata.age_buffer_tag, /* parent */ 1140 AGE_RX_BUF_ALIGN, 0, /* alignment, boundary */ 1141 BUS_SPACE_MAXADDR, /* lowaddr */ 1142 BUS_SPACE_MAXADDR, /* highaddr */ 1143 NULL, NULL, /* filter, filterarg */ 1144 MCLBYTES, /* maxsize */ 1145 1, /* nsegments */ 1146 MCLBYTES, /* maxsegsize */ 1147 0, /* flags */ 1148 NULL, NULL, /* lockfunc, lockarg */ 1149 &sc->age_cdata.age_rx_tag); 1150 if (error != 0) { 1151 device_printf(sc->age_dev, "could not create Rx DMA tag.\n"); 1152 goto fail; 1153 } 1154 1155 /* Create DMA maps for Tx buffers. */ 1156 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1157 txd = &sc->age_cdata.age_txdesc[i]; 1158 txd->tx_m = NULL; 1159 txd->tx_dmamap = NULL; 1160 error = bus_dmamap_create(sc->age_cdata.age_tx_tag, 0, 1161 &txd->tx_dmamap); 1162 if (error != 0) { 1163 device_printf(sc->age_dev, 1164 "could not create Tx dmamap.\n"); 1165 goto fail; 1166 } 1167 } 1168 /* Create DMA maps for Rx buffers. */ 1169 if ((error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1170 &sc->age_cdata.age_rx_sparemap)) != 0) { 1171 device_printf(sc->age_dev, 1172 "could not create spare Rx dmamap.\n"); 1173 goto fail; 1174 } 1175 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1176 rxd = &sc->age_cdata.age_rxdesc[i]; 1177 rxd->rx_m = NULL; 1178 rxd->rx_dmamap = NULL; 1179 error = bus_dmamap_create(sc->age_cdata.age_rx_tag, 0, 1180 &rxd->rx_dmamap); 1181 if (error != 0) { 1182 device_printf(sc->age_dev, 1183 "could not create Rx dmamap.\n"); 1184 goto fail; 1185 } 1186 } 1187 1188 fail: 1189 return (error); 1190 } 1191 1192 static void 1193 age_dma_free(struct age_softc *sc) 1194 { 1195 struct age_txdesc *txd; 1196 struct age_rxdesc *rxd; 1197 int i; 1198 1199 /* Tx buffers */ 1200 if (sc->age_cdata.age_tx_tag != NULL) { 1201 for (i = 0; i < AGE_TX_RING_CNT; i++) { 1202 txd = &sc->age_cdata.age_txdesc[i]; 1203 if (txd->tx_dmamap != NULL) { 1204 bus_dmamap_destroy(sc->age_cdata.age_tx_tag, 1205 txd->tx_dmamap); 1206 txd->tx_dmamap = NULL; 1207 } 1208 } 1209 bus_dma_tag_destroy(sc->age_cdata.age_tx_tag); 1210 sc->age_cdata.age_tx_tag = NULL; 1211 } 1212 /* Rx buffers */ 1213 if (sc->age_cdata.age_rx_tag != NULL) { 1214 for (i = 0; i < AGE_RX_RING_CNT; i++) { 1215 rxd = &sc->age_cdata.age_rxdesc[i]; 1216 if (rxd->rx_dmamap != NULL) { 1217 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1218 rxd->rx_dmamap); 1219 rxd->rx_dmamap = NULL; 1220 } 1221 } 1222 if (sc->age_cdata.age_rx_sparemap != NULL) { 1223 bus_dmamap_destroy(sc->age_cdata.age_rx_tag, 1224 sc->age_cdata.age_rx_sparemap); 1225 sc->age_cdata.age_rx_sparemap = NULL; 1226 } 1227 bus_dma_tag_destroy(sc->age_cdata.age_rx_tag); 1228 sc->age_cdata.age_rx_tag = NULL; 1229 } 1230 /* Tx ring. */ 1231 if (sc->age_cdata.age_tx_ring_tag != NULL) { 1232 if (sc->age_rdata.age_tx_ring_paddr != 0) 1233 bus_dmamap_unload(sc->age_cdata.age_tx_ring_tag, 1234 sc->age_cdata.age_tx_ring_map); 1235 if (sc->age_rdata.age_tx_ring != NULL) 1236 bus_dmamem_free(sc->age_cdata.age_tx_ring_tag, 1237 sc->age_rdata.age_tx_ring, 1238 sc->age_cdata.age_tx_ring_map); 1239 sc->age_rdata.age_tx_ring_paddr = 0; 1240 sc->age_rdata.age_tx_ring = NULL; 1241 bus_dma_tag_destroy(sc->age_cdata.age_tx_ring_tag); 1242 sc->age_cdata.age_tx_ring_tag = NULL; 1243 } 1244 /* Rx ring. */ 1245 if (sc->age_cdata.age_rx_ring_tag != NULL) { 1246 if (sc->age_rdata.age_rx_ring_paddr != 0) 1247 bus_dmamap_unload(sc->age_cdata.age_rx_ring_tag, 1248 sc->age_cdata.age_rx_ring_map); 1249 if (sc->age_rdata.age_rx_ring != NULL) 1250 bus_dmamem_free(sc->age_cdata.age_rx_ring_tag, 1251 sc->age_rdata.age_rx_ring, 1252 sc->age_cdata.age_rx_ring_map); 1253 sc->age_rdata.age_rx_ring_paddr = 0; 1254 sc->age_rdata.age_rx_ring = NULL; 1255 bus_dma_tag_destroy(sc->age_cdata.age_rx_ring_tag); 1256 sc->age_cdata.age_rx_ring_tag = NULL; 1257 } 1258 /* Rx return ring. */ 1259 if (sc->age_cdata.age_rr_ring_tag != NULL) { 1260 if (sc->age_rdata.age_rr_ring_paddr != 0) 1261 bus_dmamap_unload(sc->age_cdata.age_rr_ring_tag, 1262 sc->age_cdata.age_rr_ring_map); 1263 if (sc->age_rdata.age_rr_ring != NULL) 1264 bus_dmamem_free(sc->age_cdata.age_rr_ring_tag, 1265 sc->age_rdata.age_rr_ring, 1266 sc->age_cdata.age_rr_ring_map); 1267 sc->age_rdata.age_rr_ring_paddr = 0; 1268 sc->age_rdata.age_rr_ring = NULL; 1269 bus_dma_tag_destroy(sc->age_cdata.age_rr_ring_tag); 1270 sc->age_cdata.age_rr_ring_tag = NULL; 1271 } 1272 /* CMB block */ 1273 if (sc->age_cdata.age_cmb_block_tag != NULL) { 1274 if (sc->age_rdata.age_cmb_block_paddr != 0) 1275 bus_dmamap_unload(sc->age_cdata.age_cmb_block_tag, 1276 sc->age_cdata.age_cmb_block_map); 1277 if (sc->age_rdata.age_cmb_block != NULL) 1278 bus_dmamem_free(sc->age_cdata.age_cmb_block_tag, 1279 sc->age_rdata.age_cmb_block, 1280 sc->age_cdata.age_cmb_block_map); 1281 sc->age_rdata.age_cmb_block_paddr = 0; 1282 sc->age_rdata.age_cmb_block = NULL; 1283 bus_dma_tag_destroy(sc->age_cdata.age_cmb_block_tag); 1284 sc->age_cdata.age_cmb_block_tag = NULL; 1285 } 1286 /* SMB block */ 1287 if (sc->age_cdata.age_smb_block_tag != NULL) { 1288 if (sc->age_rdata.age_smb_block_paddr != 0) 1289 bus_dmamap_unload(sc->age_cdata.age_smb_block_tag, 1290 sc->age_cdata.age_smb_block_map); 1291 if (sc->age_rdata.age_smb_block != NULL) 1292 bus_dmamem_free(sc->age_cdata.age_smb_block_tag, 1293 sc->age_rdata.age_smb_block, 1294 sc->age_cdata.age_smb_block_map); 1295 sc->age_rdata.age_smb_block_paddr = 0; 1296 sc->age_rdata.age_smb_block = NULL; 1297 bus_dma_tag_destroy(sc->age_cdata.age_smb_block_tag); 1298 sc->age_cdata.age_smb_block_tag = NULL; 1299 } 1300 1301 if (sc->age_cdata.age_buffer_tag != NULL) { 1302 bus_dma_tag_destroy(sc->age_cdata.age_buffer_tag); 1303 sc->age_cdata.age_buffer_tag = NULL; 1304 } 1305 if (sc->age_cdata.age_parent_tag != NULL) { 1306 bus_dma_tag_destroy(sc->age_cdata.age_parent_tag); 1307 sc->age_cdata.age_parent_tag = NULL; 1308 } 1309 } 1310 1311 /* 1312 * Make sure the interface is stopped at reboot time. 1313 */ 1314 static int 1315 age_shutdown(device_t dev) 1316 { 1317 1318 return (age_suspend(dev)); 1319 } 1320 1321 static void 1322 age_setwol(struct age_softc *sc) 1323 { 1324 struct ifnet *ifp; 1325 struct mii_data *mii; 1326 uint32_t reg, pmcs; 1327 uint16_t pmstat; 1328 int aneg, i, pmc; 1329 1330 AGE_LOCK_ASSERT(sc); 1331 1332 if (pci_find_cap(sc->age_dev, PCIY_PMG, &pmc) != 0) { 1333 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 1334 /* 1335 * No PME capability, PHY power down. 1336 * XXX 1337 * Due to an unknown reason powering down PHY resulted 1338 * in unexpected results such as inaccessbility of 1339 * hardware of freshly rebooted system. Disable 1340 * powering down PHY until I got more information for 1341 * Attansic/Atheros PHY hardwares. 1342 */ 1343 #ifdef notyet 1344 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1345 MII_BMCR, BMCR_PDOWN); 1346 #endif 1347 return; 1348 } 1349 1350 ifp = sc->age_ifp; 1351 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1352 /* 1353 * Note, this driver resets the link speed to 10/100Mbps with 1354 * auto-negotiation but we don't know whether that operation 1355 * would succeed or not as it have no control after powering 1356 * off. If the renegotiation fail WOL may not work. Running 1357 * at 1Gbps will draw more power than 375mA at 3.3V which is 1358 * specified in PCI specification and that would result in 1359 * complete shutdowning power to ethernet controller. 1360 * 1361 * TODO 1362 * Save current negotiated media speed/duplex/flow-control 1363 * to softc and restore the same link again after resuming. 1364 * PHY handling such as power down/resetting to 100Mbps 1365 * may be better handled in suspend method in phy driver. 1366 */ 1367 mii = device_get_softc(sc->age_miibus); 1368 mii_pollstat(mii); 1369 aneg = 0; 1370 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1371 switch IFM_SUBTYPE(mii->mii_media_active) { 1372 case IFM_10_T: 1373 case IFM_100_TX: 1374 goto got_link; 1375 case IFM_1000_T: 1376 aneg++; 1377 default: 1378 break; 1379 } 1380 } 1381 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1382 MII_100T2CR, 0); 1383 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1384 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | 1385 ANAR_10 | ANAR_CSMA); 1386 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1387 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1388 DELAY(1000); 1389 if (aneg != 0) { 1390 /* Poll link state until age(4) get a 10/100 link. */ 1391 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1392 mii_pollstat(mii); 1393 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1394 switch (IFM_SUBTYPE( 1395 mii->mii_media_active)) { 1396 case IFM_10_T: 1397 case IFM_100_TX: 1398 age_mac_config(sc); 1399 goto got_link; 1400 default: 1401 break; 1402 } 1403 } 1404 AGE_UNLOCK(sc); 1405 pause("agelnk", hz); 1406 AGE_LOCK(sc); 1407 } 1408 if (i == MII_ANEGTICKS_GIGE) 1409 device_printf(sc->age_dev, 1410 "establishing link failed, " 1411 "WOL may not work!"); 1412 } 1413 /* 1414 * No link, force MAC to have 100Mbps, full-duplex link. 1415 * This is the last resort and may/may not work. 1416 */ 1417 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1418 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1419 age_mac_config(sc); 1420 } 1421 1422 got_link: 1423 pmcs = 0; 1424 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1425 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1426 CSR_WRITE_4(sc, AGE_WOL_CFG, pmcs); 1427 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1428 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC); 1429 reg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST); 1430 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1431 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1432 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1433 reg |= MAC_CFG_RX_ENB; 1434 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1435 } 1436 1437 /* Request PME. */ 1438 pmstat = pci_read_config(sc->age_dev, pmc + PCIR_POWER_STATUS, 2); 1439 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1440 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1441 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1442 pci_write_config(sc->age_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1443 #ifdef notyet 1444 /* See above for powering down PHY issues. */ 1445 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1446 /* No WOL, PHY power down. */ 1447 age_miibus_writereg(sc->age_dev, sc->age_phyaddr, 1448 MII_BMCR, BMCR_PDOWN); 1449 } 1450 #endif 1451 } 1452 1453 static int 1454 age_suspend(device_t dev) 1455 { 1456 struct age_softc *sc; 1457 1458 sc = device_get_softc(dev); 1459 1460 AGE_LOCK(sc); 1461 age_stop(sc); 1462 age_setwol(sc); 1463 AGE_UNLOCK(sc); 1464 1465 return (0); 1466 } 1467 1468 static int 1469 age_resume(device_t dev) 1470 { 1471 struct age_softc *sc; 1472 struct ifnet *ifp; 1473 1474 sc = device_get_softc(dev); 1475 1476 AGE_LOCK(sc); 1477 age_phy_reset(sc); 1478 ifp = sc->age_ifp; 1479 if ((ifp->if_flags & IFF_UP) != 0) 1480 age_init_locked(sc); 1481 1482 AGE_UNLOCK(sc); 1483 1484 return (0); 1485 } 1486 1487 static int 1488 age_encap(struct age_softc *sc, struct mbuf **m_head) 1489 { 1490 struct age_txdesc *txd, *txd_last; 1491 struct tx_desc *desc; 1492 struct mbuf *m; 1493 struct ip *ip; 1494 struct tcphdr *tcp; 1495 bus_dma_segment_t txsegs[AGE_MAXTXSEGS]; 1496 bus_dmamap_t map; 1497 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1498 int error, i, nsegs, prod, si; 1499 1500 AGE_LOCK_ASSERT(sc); 1501 1502 M_ASSERTPKTHDR((*m_head)); 1503 1504 m = *m_head; 1505 ip = NULL; 1506 tcp = NULL; 1507 cflags = vtag = 0; 1508 ip_off = poff = 0; 1509 if ((m->m_pkthdr.csum_flags & (AGE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1510 /* 1511 * L1 requires offset of TCP/UDP payload in its Tx 1512 * descriptor to perform hardware Tx checksum offload. 1513 * Additionally, TSO requires IP/TCP header size and 1514 * modification of IP/TCP header in order to make TSO 1515 * engine work. This kind of operation takes many CPU 1516 * cycles on FreeBSD so fast host CPU is needed to get 1517 * smooth TSO performance. 1518 */ 1519 struct ether_header *eh; 1520 1521 if (M_WRITABLE(m) == 0) { 1522 /* Get a writable copy. */ 1523 m = m_dup(*m_head, M_NOWAIT); 1524 /* Release original mbufs. */ 1525 m_freem(*m_head); 1526 if (m == NULL) { 1527 *m_head = NULL; 1528 return (ENOBUFS); 1529 } 1530 *m_head = m; 1531 } 1532 ip_off = sizeof(struct ether_header); 1533 m = m_pullup(m, ip_off); 1534 if (m == NULL) { 1535 *m_head = NULL; 1536 return (ENOBUFS); 1537 } 1538 eh = mtod(m, struct ether_header *); 1539 /* 1540 * Check if hardware VLAN insertion is off. 1541 * Additional check for LLC/SNAP frame? 1542 */ 1543 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1544 ip_off = sizeof(struct ether_vlan_header); 1545 m = m_pullup(m, ip_off); 1546 if (m == NULL) { 1547 *m_head = NULL; 1548 return (ENOBUFS); 1549 } 1550 } 1551 m = m_pullup(m, ip_off + sizeof(struct ip)); 1552 if (m == NULL) { 1553 *m_head = NULL; 1554 return (ENOBUFS); 1555 } 1556 ip = (struct ip *)(mtod(m, char *) + ip_off); 1557 poff = ip_off + (ip->ip_hl << 2); 1558 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1559 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1560 if (m == NULL) { 1561 *m_head = NULL; 1562 return (ENOBUFS); 1563 } 1564 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1565 m = m_pullup(m, poff + (tcp->th_off << 2)); 1566 if (m == NULL) { 1567 *m_head = NULL; 1568 return (ENOBUFS); 1569 } 1570 /* 1571 * L1 requires IP/TCP header size and offset as 1572 * well as TCP pseudo checksum which complicates 1573 * TSO configuration. I guess this comes from the 1574 * adherence to Microsoft NDIS Large Send 1575 * specification which requires insertion of 1576 * pseudo checksum by upper stack. The pseudo 1577 * checksum that NDIS refers to doesn't include 1578 * TCP payload length so age(4) should recompute 1579 * the pseudo checksum here. Hopefully this wouldn't 1580 * be much burden on modern CPUs. 1581 * Reset IP checksum and recompute TCP pseudo 1582 * checksum as NDIS specification said. 1583 */ 1584 ip = (struct ip *)(mtod(m, char *) + ip_off); 1585 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1586 ip->ip_sum = 0; 1587 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1588 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1589 } 1590 *m_head = m; 1591 } 1592 1593 si = prod = sc->age_cdata.age_tx_prod; 1594 txd = &sc->age_cdata.age_txdesc[prod]; 1595 txd_last = txd; 1596 map = txd->tx_dmamap; 1597 1598 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1599 *m_head, txsegs, &nsegs, 0); 1600 if (error == EFBIG) { 1601 m = m_collapse(*m_head, M_NOWAIT, AGE_MAXTXSEGS); 1602 if (m == NULL) { 1603 m_freem(*m_head); 1604 *m_head = NULL; 1605 return (ENOMEM); 1606 } 1607 *m_head = m; 1608 error = bus_dmamap_load_mbuf_sg(sc->age_cdata.age_tx_tag, map, 1609 *m_head, txsegs, &nsegs, 0); 1610 if (error != 0) { 1611 m_freem(*m_head); 1612 *m_head = NULL; 1613 return (error); 1614 } 1615 } else if (error != 0) 1616 return (error); 1617 if (nsegs == 0) { 1618 m_freem(*m_head); 1619 *m_head = NULL; 1620 return (EIO); 1621 } 1622 1623 /* Check descriptor overrun. */ 1624 if (sc->age_cdata.age_tx_cnt + nsegs >= AGE_TX_RING_CNT - 2) { 1625 bus_dmamap_unload(sc->age_cdata.age_tx_tag, map); 1626 return (ENOBUFS); 1627 } 1628 1629 m = *m_head; 1630 /* Configure VLAN hardware tag insertion. */ 1631 if ((m->m_flags & M_VLANTAG) != 0) { 1632 vtag = AGE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1633 vtag = ((vtag << AGE_TD_VLAN_SHIFT) & AGE_TD_VLAN_MASK); 1634 cflags |= AGE_TD_INSERT_VLAN_TAG; 1635 } 1636 1637 desc = NULL; 1638 i = 0; 1639 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1640 /* Request TSO and set MSS. */ 1641 cflags |= AGE_TD_TSO_IPV4; 1642 cflags |= AGE_TD_IPCSUM | AGE_TD_TCPCSUM; 1643 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << 1644 AGE_TD_TSO_MSS_SHIFT); 1645 /* Set IP/TCP header size. */ 1646 cflags |= ip->ip_hl << AGE_TD_IPHDR_LEN_SHIFT; 1647 cflags |= tcp->th_off << AGE_TD_TSO_TCPHDR_LEN_SHIFT; 1648 /* 1649 * L1 requires the first buffer should only hold IP/TCP 1650 * header data. TCP payload should be handled in other 1651 * descriptors. 1652 */ 1653 hdrlen = poff + (tcp->th_off << 2); 1654 desc = &sc->age_rdata.age_tx_ring[prod]; 1655 desc->addr = htole64(txsegs[0].ds_addr); 1656 desc->len = htole32(AGE_TX_BYTES(hdrlen) | vtag); 1657 desc->flags = htole32(cflags); 1658 sc->age_cdata.age_tx_cnt++; 1659 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1660 if (m->m_len - hdrlen > 0) { 1661 /* Handle remaining payload of the 1st fragment. */ 1662 desc = &sc->age_rdata.age_tx_ring[prod]; 1663 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 1664 desc->len = htole32(AGE_TX_BYTES(m->m_len - hdrlen) | 1665 vtag); 1666 desc->flags = htole32(cflags); 1667 sc->age_cdata.age_tx_cnt++; 1668 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1669 } 1670 /* Handle remaining fragments. */ 1671 i = 1; 1672 } else if ((m->m_pkthdr.csum_flags & AGE_CSUM_FEATURES) != 0) { 1673 /* Configure Tx IP/TCP/UDP checksum offload. */ 1674 cflags |= AGE_TD_CSUM; 1675 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1676 cflags |= AGE_TD_TCPCSUM; 1677 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1678 cflags |= AGE_TD_UDPCSUM; 1679 /* Set checksum start offset. */ 1680 cflags |= (poff << AGE_TD_CSUM_PLOADOFFSET_SHIFT); 1681 /* Set checksum insertion position of TCP/UDP. */ 1682 cflags |= ((poff + m->m_pkthdr.csum_data) << 1683 AGE_TD_CSUM_XSUMOFFSET_SHIFT); 1684 } 1685 for (; i < nsegs; i++) { 1686 desc = &sc->age_rdata.age_tx_ring[prod]; 1687 desc->addr = htole64(txsegs[i].ds_addr); 1688 desc->len = htole32(AGE_TX_BYTES(txsegs[i].ds_len) | vtag); 1689 desc->flags = htole32(cflags); 1690 sc->age_cdata.age_tx_cnt++; 1691 AGE_DESC_INC(prod, AGE_TX_RING_CNT); 1692 } 1693 /* Update producer index. */ 1694 sc->age_cdata.age_tx_prod = prod; 1695 1696 /* Set EOP on the last descriptor. */ 1697 prod = (prod + AGE_TX_RING_CNT - 1) % AGE_TX_RING_CNT; 1698 desc = &sc->age_rdata.age_tx_ring[prod]; 1699 desc->flags |= htole32(AGE_TD_EOP); 1700 1701 /* Lastly set TSO header and modify IP/TCP header for TSO operation. */ 1702 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1703 desc = &sc->age_rdata.age_tx_ring[si]; 1704 desc->flags |= htole32(AGE_TD_TSO_HDR); 1705 } 1706 1707 /* Swap dmamap of the first and the last. */ 1708 txd = &sc->age_cdata.age_txdesc[prod]; 1709 map = txd_last->tx_dmamap; 1710 txd_last->tx_dmamap = txd->tx_dmamap; 1711 txd->tx_dmamap = map; 1712 txd->tx_m = m; 1713 1714 /* Sync descriptors. */ 1715 bus_dmamap_sync(sc->age_cdata.age_tx_tag, map, BUS_DMASYNC_PREWRITE); 1716 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 1717 sc->age_cdata.age_tx_ring_map, 1718 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1719 1720 return (0); 1721 } 1722 1723 static void 1724 age_start(struct ifnet *ifp) 1725 { 1726 struct age_softc *sc; 1727 1728 sc = ifp->if_softc; 1729 AGE_LOCK(sc); 1730 age_start_locked(ifp); 1731 AGE_UNLOCK(sc); 1732 } 1733 1734 static void 1735 age_start_locked(struct ifnet *ifp) 1736 { 1737 struct age_softc *sc; 1738 struct mbuf *m_head; 1739 int enq; 1740 1741 sc = ifp->if_softc; 1742 1743 AGE_LOCK_ASSERT(sc); 1744 1745 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1746 IFF_DRV_RUNNING || (sc->age_flags & AGE_FLAG_LINK) == 0) 1747 return; 1748 1749 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1750 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1751 if (m_head == NULL) 1752 break; 1753 /* 1754 * Pack the data into the transmit ring. If we 1755 * don't have room, set the OACTIVE flag and wait 1756 * for the NIC to drain the ring. 1757 */ 1758 if (age_encap(sc, &m_head)) { 1759 if (m_head == NULL) 1760 break; 1761 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1762 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1763 break; 1764 } 1765 1766 enq++; 1767 /* 1768 * If there's a BPF listener, bounce a copy of this frame 1769 * to him. 1770 */ 1771 ETHER_BPF_MTAP(ifp, m_head); 1772 } 1773 1774 if (enq > 0) { 1775 /* Update mbox. */ 1776 AGE_COMMIT_MBOX(sc); 1777 /* Set a timeout in case the chip goes out to lunch. */ 1778 sc->age_watchdog_timer = AGE_TX_TIMEOUT; 1779 } 1780 } 1781 1782 static void 1783 age_watchdog(struct age_softc *sc) 1784 { 1785 struct ifnet *ifp; 1786 1787 AGE_LOCK_ASSERT(sc); 1788 1789 if (sc->age_watchdog_timer == 0 || --sc->age_watchdog_timer) 1790 return; 1791 1792 ifp = sc->age_ifp; 1793 if ((sc->age_flags & AGE_FLAG_LINK) == 0) { 1794 if_printf(sc->age_ifp, "watchdog timeout (missed link)\n"); 1795 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1796 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1797 age_init_locked(sc); 1798 return; 1799 } 1800 if (sc->age_cdata.age_tx_cnt == 0) { 1801 if_printf(sc->age_ifp, 1802 "watchdog timeout (missed Tx interrupts) -- recovering\n"); 1803 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1804 age_start_locked(ifp); 1805 return; 1806 } 1807 if_printf(sc->age_ifp, "watchdog timeout\n"); 1808 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1809 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1810 age_init_locked(sc); 1811 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1812 age_start_locked(ifp); 1813 } 1814 1815 static int 1816 age_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1817 { 1818 struct age_softc *sc; 1819 struct ifreq *ifr; 1820 struct mii_data *mii; 1821 uint32_t reg; 1822 int error, mask; 1823 1824 sc = ifp->if_softc; 1825 ifr = (struct ifreq *)data; 1826 error = 0; 1827 switch (cmd) { 1828 case SIOCSIFMTU: 1829 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > AGE_JUMBO_MTU) 1830 error = EINVAL; 1831 else if (ifp->if_mtu != ifr->ifr_mtu) { 1832 AGE_LOCK(sc); 1833 ifp->if_mtu = ifr->ifr_mtu; 1834 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1835 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1836 age_init_locked(sc); 1837 } 1838 AGE_UNLOCK(sc); 1839 } 1840 break; 1841 case SIOCSIFFLAGS: 1842 AGE_LOCK(sc); 1843 if ((ifp->if_flags & IFF_UP) != 0) { 1844 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1845 if (((ifp->if_flags ^ sc->age_if_flags) 1846 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1847 age_rxfilter(sc); 1848 } else { 1849 if ((sc->age_flags & AGE_FLAG_DETACH) == 0) 1850 age_init_locked(sc); 1851 } 1852 } else { 1853 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1854 age_stop(sc); 1855 } 1856 sc->age_if_flags = ifp->if_flags; 1857 AGE_UNLOCK(sc); 1858 break; 1859 case SIOCADDMULTI: 1860 case SIOCDELMULTI: 1861 AGE_LOCK(sc); 1862 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1863 age_rxfilter(sc); 1864 AGE_UNLOCK(sc); 1865 break; 1866 case SIOCSIFMEDIA: 1867 case SIOCGIFMEDIA: 1868 mii = device_get_softc(sc->age_miibus); 1869 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1870 break; 1871 case SIOCSIFCAP: 1872 AGE_LOCK(sc); 1873 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1874 if ((mask & IFCAP_TXCSUM) != 0 && 1875 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1876 ifp->if_capenable ^= IFCAP_TXCSUM; 1877 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1878 ifp->if_hwassist |= AGE_CSUM_FEATURES; 1879 else 1880 ifp->if_hwassist &= ~AGE_CSUM_FEATURES; 1881 } 1882 if ((mask & IFCAP_RXCSUM) != 0 && 1883 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 1884 ifp->if_capenable ^= IFCAP_RXCSUM; 1885 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1886 reg &= ~MAC_CFG_RXCSUM_ENB; 1887 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1888 reg |= MAC_CFG_RXCSUM_ENB; 1889 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1890 } 1891 if ((mask & IFCAP_TSO4) != 0 && 1892 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1893 ifp->if_capenable ^= IFCAP_TSO4; 1894 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1895 ifp->if_hwassist |= CSUM_TSO; 1896 else 1897 ifp->if_hwassist &= ~CSUM_TSO; 1898 } 1899 1900 if ((mask & IFCAP_WOL_MCAST) != 0 && 1901 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1902 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1903 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1904 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1905 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1906 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1907 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1908 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1909 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1910 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1911 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1912 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1913 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1914 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1915 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1916 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 1917 age_rxvlan(sc); 1918 } 1919 AGE_UNLOCK(sc); 1920 VLAN_CAPABILITIES(ifp); 1921 break; 1922 default: 1923 error = ether_ioctl(ifp, cmd, data); 1924 break; 1925 } 1926 1927 return (error); 1928 } 1929 1930 static void 1931 age_mac_config(struct age_softc *sc) 1932 { 1933 struct mii_data *mii; 1934 uint32_t reg; 1935 1936 AGE_LOCK_ASSERT(sc); 1937 1938 mii = device_get_softc(sc->age_miibus); 1939 reg = CSR_READ_4(sc, AGE_MAC_CFG); 1940 reg &= ~MAC_CFG_FULL_DUPLEX; 1941 reg &= ~(MAC_CFG_TX_FC | MAC_CFG_RX_FC); 1942 reg &= ~MAC_CFG_SPEED_MASK; 1943 /* Reprogram MAC with resolved speed/duplex. */ 1944 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1945 case IFM_10_T: 1946 case IFM_100_TX: 1947 reg |= MAC_CFG_SPEED_10_100; 1948 break; 1949 case IFM_1000_T: 1950 reg |= MAC_CFG_SPEED_1000; 1951 break; 1952 } 1953 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 1954 reg |= MAC_CFG_FULL_DUPLEX; 1955 #ifdef notyet 1956 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 1957 reg |= MAC_CFG_TX_FC; 1958 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 1959 reg |= MAC_CFG_RX_FC; 1960 #endif 1961 } 1962 1963 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 1964 } 1965 1966 static void 1967 age_link_task(void *arg, int pending) 1968 { 1969 struct age_softc *sc; 1970 struct mii_data *mii; 1971 struct ifnet *ifp; 1972 uint32_t reg; 1973 1974 sc = (struct age_softc *)arg; 1975 1976 AGE_LOCK(sc); 1977 mii = device_get_softc(sc->age_miibus); 1978 ifp = sc->age_ifp; 1979 if (mii == NULL || ifp == NULL || 1980 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1981 AGE_UNLOCK(sc); 1982 return; 1983 } 1984 1985 sc->age_flags &= ~AGE_FLAG_LINK; 1986 if ((mii->mii_media_status & IFM_AVALID) != 0) { 1987 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1988 case IFM_10_T: 1989 case IFM_100_TX: 1990 case IFM_1000_T: 1991 sc->age_flags |= AGE_FLAG_LINK; 1992 break; 1993 default: 1994 break; 1995 } 1996 } 1997 1998 /* Stop Rx/Tx MACs. */ 1999 age_stop_rxmac(sc); 2000 age_stop_txmac(sc); 2001 2002 /* Program MACs with resolved speed/duplex/flow-control. */ 2003 if ((sc->age_flags & AGE_FLAG_LINK) != 0) { 2004 age_mac_config(sc); 2005 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2006 /* Restart DMA engine and Tx/Rx MAC. */ 2007 CSR_WRITE_4(sc, AGE_DMA_CFG, CSR_READ_4(sc, AGE_DMA_CFG) | 2008 DMA_CFG_RD_ENB | DMA_CFG_WR_ENB); 2009 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2010 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2011 } 2012 2013 AGE_UNLOCK(sc); 2014 } 2015 2016 static void 2017 age_stats_update(struct age_softc *sc) 2018 { 2019 struct age_stats *stat; 2020 struct smb *smb; 2021 struct ifnet *ifp; 2022 2023 AGE_LOCK_ASSERT(sc); 2024 2025 stat = &sc->age_stat; 2026 2027 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2028 sc->age_cdata.age_smb_block_map, 2029 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2030 2031 smb = sc->age_rdata.age_smb_block; 2032 if (smb->updated == 0) 2033 return; 2034 2035 ifp = sc->age_ifp; 2036 /* Rx stats. */ 2037 stat->rx_frames += smb->rx_frames; 2038 stat->rx_bcast_frames += smb->rx_bcast_frames; 2039 stat->rx_mcast_frames += smb->rx_mcast_frames; 2040 stat->rx_pause_frames += smb->rx_pause_frames; 2041 stat->rx_control_frames += smb->rx_control_frames; 2042 stat->rx_crcerrs += smb->rx_crcerrs; 2043 stat->rx_lenerrs += smb->rx_lenerrs; 2044 stat->rx_bytes += smb->rx_bytes; 2045 stat->rx_runts += smb->rx_runts; 2046 stat->rx_fragments += smb->rx_fragments; 2047 stat->rx_pkts_64 += smb->rx_pkts_64; 2048 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2049 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2050 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2051 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2052 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2053 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2054 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2055 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2056 stat->rx_desc_oflows += smb->rx_desc_oflows; 2057 stat->rx_alignerrs += smb->rx_alignerrs; 2058 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2059 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2060 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2061 2062 /* Tx stats. */ 2063 stat->tx_frames += smb->tx_frames; 2064 stat->tx_bcast_frames += smb->tx_bcast_frames; 2065 stat->tx_mcast_frames += smb->tx_mcast_frames; 2066 stat->tx_pause_frames += smb->tx_pause_frames; 2067 stat->tx_excess_defer += smb->tx_excess_defer; 2068 stat->tx_control_frames += smb->tx_control_frames; 2069 stat->tx_deferred += smb->tx_deferred; 2070 stat->tx_bytes += smb->tx_bytes; 2071 stat->tx_pkts_64 += smb->tx_pkts_64; 2072 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2073 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2074 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2075 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2076 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2077 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2078 stat->tx_single_colls += smb->tx_single_colls; 2079 stat->tx_multi_colls += smb->tx_multi_colls; 2080 stat->tx_late_colls += smb->tx_late_colls; 2081 stat->tx_excess_colls += smb->tx_excess_colls; 2082 stat->tx_underrun += smb->tx_underrun; 2083 stat->tx_desc_underrun += smb->tx_desc_underrun; 2084 stat->tx_lenerrs += smb->tx_lenerrs; 2085 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2086 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2087 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2088 2089 /* Update counters in ifnet. */ 2090 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2091 2092 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2093 smb->tx_multi_colls + smb->tx_late_colls + 2094 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2095 2096 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_excess_colls + 2097 smb->tx_late_colls + smb->tx_underrun + 2098 smb->tx_pkts_truncated); 2099 2100 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2101 2102 if_inc_counter(ifp, IFCOUNTER_IERRORS, smb->rx_crcerrs + 2103 smb->rx_lenerrs + smb->rx_runts + smb->rx_pkts_truncated + 2104 smb->rx_fifo_oflows + smb->rx_desc_oflows + 2105 smb->rx_alignerrs); 2106 2107 /* Update done, clear. */ 2108 smb->updated = 0; 2109 2110 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 2111 sc->age_cdata.age_smb_block_map, 2112 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2113 } 2114 2115 static int 2116 age_intr(void *arg) 2117 { 2118 struct age_softc *sc; 2119 uint32_t status; 2120 2121 sc = (struct age_softc *)arg; 2122 2123 status = CSR_READ_4(sc, AGE_INTR_STATUS); 2124 if (status == 0 || (status & AGE_INTRS) == 0) 2125 return (FILTER_STRAY); 2126 /* Disable interrupts. */ 2127 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2128 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2129 2130 return (FILTER_HANDLED); 2131 } 2132 2133 static void 2134 age_int_task(void *arg, int pending) 2135 { 2136 struct age_softc *sc; 2137 struct ifnet *ifp; 2138 struct cmb *cmb; 2139 uint32_t status; 2140 2141 sc = (struct age_softc *)arg; 2142 2143 AGE_LOCK(sc); 2144 2145 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2146 sc->age_cdata.age_cmb_block_map, 2147 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2148 cmb = sc->age_rdata.age_cmb_block; 2149 status = le32toh(cmb->intr_status); 2150 if (sc->age_morework != 0) 2151 status |= INTR_CMB_RX; 2152 if ((status & AGE_INTRS) == 0) 2153 goto done; 2154 2155 sc->age_tpd_cons = (le32toh(cmb->tpd_cons) & TPD_CONS_MASK) >> 2156 TPD_CONS_SHIFT; 2157 sc->age_rr_prod = (le32toh(cmb->rprod_cons) & RRD_PROD_MASK) >> 2158 RRD_PROD_SHIFT; 2159 /* Let hardware know CMB was served. */ 2160 cmb->intr_status = 0; 2161 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2162 sc->age_cdata.age_cmb_block_map, 2163 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2164 2165 #if 0 2166 printf("INTR: 0x%08x\n", status); 2167 status &= ~INTR_DIS_DMA; 2168 CSR_WRITE_4(sc, AGE_INTR_STATUS, status | INTR_DIS_INT); 2169 #endif 2170 ifp = sc->age_ifp; 2171 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2172 if ((status & INTR_CMB_RX) != 0) 2173 sc->age_morework = age_rxintr(sc, sc->age_rr_prod, 2174 sc->age_process_limit); 2175 if ((status & INTR_CMB_TX) != 0) 2176 age_txintr(sc, sc->age_tpd_cons); 2177 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2178 if ((status & INTR_DMA_RD_TO_RST) != 0) 2179 device_printf(sc->age_dev, 2180 "DMA read error! -- resetting\n"); 2181 if ((status & INTR_DMA_WR_TO_RST) != 0) 2182 device_printf(sc->age_dev, 2183 "DMA write error! -- resetting\n"); 2184 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2185 age_init_locked(sc); 2186 } 2187 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2188 age_start_locked(ifp); 2189 if ((status & INTR_SMB) != 0) 2190 age_stats_update(sc); 2191 } 2192 2193 /* Check whether CMB was updated while serving Tx/Rx/SMB handler. */ 2194 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 2195 sc->age_cdata.age_cmb_block_map, 2196 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2197 status = le32toh(cmb->intr_status); 2198 if (sc->age_morework != 0 || (status & AGE_INTRS) != 0) { 2199 taskqueue_enqueue(sc->age_tq, &sc->age_int_task); 2200 AGE_UNLOCK(sc); 2201 return; 2202 } 2203 2204 done: 2205 /* Re-enable interrupts. */ 2206 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2207 AGE_UNLOCK(sc); 2208 } 2209 2210 static void 2211 age_txintr(struct age_softc *sc, int tpd_cons) 2212 { 2213 struct ifnet *ifp; 2214 struct age_txdesc *txd; 2215 int cons, prog; 2216 2217 AGE_LOCK_ASSERT(sc); 2218 2219 ifp = sc->age_ifp; 2220 2221 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2222 sc->age_cdata.age_tx_ring_map, 2223 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2224 2225 /* 2226 * Go through our Tx list and free mbufs for those 2227 * frames which have been transmitted. 2228 */ 2229 cons = sc->age_cdata.age_tx_cons; 2230 for (prog = 0; cons != tpd_cons; AGE_DESC_INC(cons, AGE_TX_RING_CNT)) { 2231 if (sc->age_cdata.age_tx_cnt <= 0) 2232 break; 2233 prog++; 2234 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2235 sc->age_cdata.age_tx_cnt--; 2236 txd = &sc->age_cdata.age_txdesc[cons]; 2237 /* 2238 * Clear Tx descriptors, it's not required but would 2239 * help debugging in case of Tx issues. 2240 */ 2241 txd->tx_desc->addr = 0; 2242 txd->tx_desc->len = 0; 2243 txd->tx_desc->flags = 0; 2244 2245 if (txd->tx_m == NULL) 2246 continue; 2247 /* Reclaim transmitted mbufs. */ 2248 bus_dmamap_sync(sc->age_cdata.age_tx_tag, txd->tx_dmamap, 2249 BUS_DMASYNC_POSTWRITE); 2250 bus_dmamap_unload(sc->age_cdata.age_tx_tag, txd->tx_dmamap); 2251 m_freem(txd->tx_m); 2252 txd->tx_m = NULL; 2253 } 2254 2255 if (prog > 0) { 2256 sc->age_cdata.age_tx_cons = cons; 2257 2258 /* 2259 * Unarm watchdog timer only when there are no pending 2260 * Tx descriptors in queue. 2261 */ 2262 if (sc->age_cdata.age_tx_cnt == 0) 2263 sc->age_watchdog_timer = 0; 2264 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 2265 sc->age_cdata.age_tx_ring_map, 2266 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2267 } 2268 } 2269 2270 #ifndef __NO_STRICT_ALIGNMENT 2271 static struct mbuf * 2272 age_fixup_rx(struct ifnet *ifp, struct mbuf *m) 2273 { 2274 struct mbuf *n; 2275 int i; 2276 uint16_t *src, *dst; 2277 2278 src = mtod(m, uint16_t *); 2279 dst = src - 3; 2280 2281 if (m->m_next == NULL) { 2282 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2283 *dst++ = *src++; 2284 m->m_data -= 6; 2285 return (m); 2286 } 2287 /* 2288 * Append a new mbuf to received mbuf chain and copy ethernet 2289 * header from the mbuf chain. This can save lots of CPU 2290 * cycles for jumbo frame. 2291 */ 2292 MGETHDR(n, M_NOWAIT, MT_DATA); 2293 if (n == NULL) { 2294 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2295 m_freem(m); 2296 return (NULL); 2297 } 2298 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 2299 m->m_data += ETHER_HDR_LEN; 2300 m->m_len -= ETHER_HDR_LEN; 2301 n->m_len = ETHER_HDR_LEN; 2302 M_MOVE_PKTHDR(n, m); 2303 n->m_next = m; 2304 return (n); 2305 } 2306 #endif 2307 2308 /* Receive a frame. */ 2309 static void 2310 age_rxeof(struct age_softc *sc, struct rx_rdesc *rxrd) 2311 { 2312 struct age_rxdesc *rxd; 2313 struct ifnet *ifp; 2314 struct mbuf *mp, *m; 2315 uint32_t status, index, vtag; 2316 int count, nsegs; 2317 int rx_cons; 2318 2319 AGE_LOCK_ASSERT(sc); 2320 2321 ifp = sc->age_ifp; 2322 status = le32toh(rxrd->flags); 2323 index = le32toh(rxrd->index); 2324 rx_cons = AGE_RX_CONS(index); 2325 nsegs = AGE_RX_NSEGS(index); 2326 2327 sc->age_cdata.age_rxlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2328 if ((status & (AGE_RRD_ERROR | AGE_RRD_LENGTH_NOK)) != 0) { 2329 /* 2330 * We want to pass the following frames to upper 2331 * layer regardless of error status of Rx return 2332 * ring. 2333 * 2334 * o IP/TCP/UDP checksum is bad. 2335 * o frame length and protocol specific length 2336 * does not match. 2337 */ 2338 status |= AGE_RRD_IPCSUM_NOK | AGE_RRD_TCP_UDPCSUM_NOK; 2339 if ((status & (AGE_RRD_CRC | AGE_RRD_CODE | AGE_RRD_DRIBBLE | 2340 AGE_RRD_RUNT | AGE_RRD_OFLOW | AGE_RRD_TRUNC)) != 0) 2341 return; 2342 } 2343 2344 for (count = 0; count < nsegs; count++, 2345 AGE_DESC_INC(rx_cons, AGE_RX_RING_CNT)) { 2346 rxd = &sc->age_cdata.age_rxdesc[rx_cons]; 2347 mp = rxd->rx_m; 2348 /* Add a new receive buffer to the ring. */ 2349 if (age_newbuf(sc, rxd) != 0) { 2350 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2351 /* Reuse Rx buffers. */ 2352 if (sc->age_cdata.age_rxhead != NULL) 2353 m_freem(sc->age_cdata.age_rxhead); 2354 break; 2355 } 2356 2357 /* 2358 * Assume we've received a full sized frame. 2359 * Actual size is fixed when we encounter the end of 2360 * multi-segmented frame. 2361 */ 2362 mp->m_len = AGE_RX_BUF_SIZE; 2363 2364 /* Chain received mbufs. */ 2365 if (sc->age_cdata.age_rxhead == NULL) { 2366 sc->age_cdata.age_rxhead = mp; 2367 sc->age_cdata.age_rxtail = mp; 2368 } else { 2369 mp->m_flags &= ~M_PKTHDR; 2370 sc->age_cdata.age_rxprev_tail = 2371 sc->age_cdata.age_rxtail; 2372 sc->age_cdata.age_rxtail->m_next = mp; 2373 sc->age_cdata.age_rxtail = mp; 2374 } 2375 2376 if (count == nsegs - 1) { 2377 /* Last desc. for this frame. */ 2378 m = sc->age_cdata.age_rxhead; 2379 m->m_flags |= M_PKTHDR; 2380 /* 2381 * It seems that L1 controller has no way 2382 * to tell hardware to strip CRC bytes. 2383 */ 2384 m->m_pkthdr.len = sc->age_cdata.age_rxlen - 2385 ETHER_CRC_LEN; 2386 if (nsegs > 1) { 2387 /* Set last mbuf size. */ 2388 mp->m_len = sc->age_cdata.age_rxlen - 2389 ((nsegs - 1) * AGE_RX_BUF_SIZE); 2390 /* Remove the CRC bytes in chained mbufs. */ 2391 if (mp->m_len <= ETHER_CRC_LEN) { 2392 sc->age_cdata.age_rxtail = 2393 sc->age_cdata.age_rxprev_tail; 2394 sc->age_cdata.age_rxtail->m_len -= 2395 (ETHER_CRC_LEN - mp->m_len); 2396 sc->age_cdata.age_rxtail->m_next = NULL; 2397 m_freem(mp); 2398 } else { 2399 mp->m_len -= ETHER_CRC_LEN; 2400 } 2401 } else 2402 m->m_len = m->m_pkthdr.len; 2403 m->m_pkthdr.rcvif = ifp; 2404 /* 2405 * Set checksum information. 2406 * It seems that L1 controller can compute partial 2407 * checksum. The partial checksum value can be used 2408 * to accelerate checksum computation for fragmented 2409 * TCP/UDP packets. Upper network stack already 2410 * takes advantage of the partial checksum value in 2411 * IP reassembly stage. But I'm not sure the 2412 * correctness of the partial hardware checksum 2413 * assistance due to lack of data sheet. If it is 2414 * proven to work on L1 I'll enable it. 2415 */ 2416 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2417 (status & AGE_RRD_IPV4) != 0) { 2418 if ((status & AGE_RRD_IPCSUM_NOK) == 0) 2419 m->m_pkthdr.csum_flags |= 2420 CSUM_IP_CHECKED | CSUM_IP_VALID; 2421 if ((status & (AGE_RRD_TCP | AGE_RRD_UDP)) && 2422 (status & AGE_RRD_TCP_UDPCSUM_NOK) == 0) { 2423 m->m_pkthdr.csum_flags |= 2424 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2425 m->m_pkthdr.csum_data = 0xffff; 2426 } 2427 /* 2428 * Don't mark bad checksum for TCP/UDP frames 2429 * as fragmented frames may always have set 2430 * bad checksummed bit of descriptor status. 2431 */ 2432 } 2433 2434 /* Check for VLAN tagged frames. */ 2435 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2436 (status & AGE_RRD_VLAN) != 0) { 2437 vtag = AGE_RX_VLAN(le32toh(rxrd->vtags)); 2438 m->m_pkthdr.ether_vtag = AGE_RX_VLAN_TAG(vtag); 2439 m->m_flags |= M_VLANTAG; 2440 } 2441 #ifndef __NO_STRICT_ALIGNMENT 2442 m = age_fixup_rx(ifp, m); 2443 if (m != NULL) 2444 #endif 2445 { 2446 /* Pass it on. */ 2447 AGE_UNLOCK(sc); 2448 (*ifp->if_input)(ifp, m); 2449 AGE_LOCK(sc); 2450 } 2451 } 2452 } 2453 2454 /* Reset mbuf chains. */ 2455 AGE_RXCHAIN_RESET(sc); 2456 } 2457 2458 static int 2459 age_rxintr(struct age_softc *sc, int rr_prod, int count) 2460 { 2461 struct rx_rdesc *rxrd; 2462 int rr_cons, nsegs, pktlen, prog; 2463 2464 AGE_LOCK_ASSERT(sc); 2465 2466 rr_cons = sc->age_cdata.age_rr_cons; 2467 if (rr_cons == rr_prod) 2468 return (0); 2469 2470 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2471 sc->age_cdata.age_rr_ring_map, 2472 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2473 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2474 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_POSTWRITE); 2475 2476 for (prog = 0; rr_cons != rr_prod; prog++) { 2477 if (count-- <= 0) 2478 break; 2479 rxrd = &sc->age_rdata.age_rr_ring[rr_cons]; 2480 nsegs = AGE_RX_NSEGS(le32toh(rxrd->index)); 2481 if (nsegs == 0) 2482 break; 2483 /* 2484 * Check number of segments against received bytes. 2485 * Non-matching value would indicate that hardware 2486 * is still trying to update Rx return descriptors. 2487 * I'm not sure whether this check is really needed. 2488 */ 2489 pktlen = AGE_RX_BYTES(le32toh(rxrd->len)); 2490 if (nsegs != (pktlen + (AGE_RX_BUF_SIZE - 1)) / AGE_RX_BUF_SIZE) 2491 break; 2492 2493 /* Received a frame. */ 2494 age_rxeof(sc, rxrd); 2495 /* Clear return ring. */ 2496 rxrd->index = 0; 2497 AGE_DESC_INC(rr_cons, AGE_RR_RING_CNT); 2498 sc->age_cdata.age_rx_cons += nsegs; 2499 sc->age_cdata.age_rx_cons %= AGE_RX_RING_CNT; 2500 } 2501 2502 if (prog > 0) { 2503 /* Update the consumer index. */ 2504 sc->age_cdata.age_rr_cons = rr_cons; 2505 2506 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 2507 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 2508 /* Sync descriptors. */ 2509 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 2510 sc->age_cdata.age_rr_ring_map, 2511 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2512 2513 /* Notify hardware availability of new Rx buffers. */ 2514 AGE_COMMIT_MBOX(sc); 2515 } 2516 2517 return (count > 0 ? 0 : EAGAIN); 2518 } 2519 2520 static void 2521 age_tick(void *arg) 2522 { 2523 struct age_softc *sc; 2524 struct mii_data *mii; 2525 2526 sc = (struct age_softc *)arg; 2527 2528 AGE_LOCK_ASSERT(sc); 2529 2530 mii = device_get_softc(sc->age_miibus); 2531 mii_tick(mii); 2532 age_watchdog(sc); 2533 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2534 } 2535 2536 static void 2537 age_reset(struct age_softc *sc) 2538 { 2539 uint32_t reg; 2540 int i; 2541 2542 CSR_WRITE_4(sc, AGE_MASTER_CFG, MASTER_RESET); 2543 CSR_READ_4(sc, AGE_MASTER_CFG); 2544 DELAY(1000); 2545 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2546 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2547 break; 2548 DELAY(10); 2549 } 2550 2551 if (i == 0) 2552 device_printf(sc->age_dev, "reset timeout(0x%08x)!\n", reg); 2553 /* Initialize PCIe module. From Linux. */ 2554 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2555 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2556 } 2557 2558 static void 2559 age_init(void *xsc) 2560 { 2561 struct age_softc *sc; 2562 2563 sc = (struct age_softc *)xsc; 2564 AGE_LOCK(sc); 2565 age_init_locked(sc); 2566 AGE_UNLOCK(sc); 2567 } 2568 2569 static void 2570 age_init_locked(struct age_softc *sc) 2571 { 2572 struct ifnet *ifp; 2573 struct mii_data *mii; 2574 uint8_t eaddr[ETHER_ADDR_LEN]; 2575 bus_addr_t paddr; 2576 uint32_t reg, fsize; 2577 uint32_t rxf_hi, rxf_lo, rrd_hi, rrd_lo; 2578 int error; 2579 2580 AGE_LOCK_ASSERT(sc); 2581 2582 ifp = sc->age_ifp; 2583 mii = device_get_softc(sc->age_miibus); 2584 2585 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2586 return; 2587 2588 /* 2589 * Cancel any pending I/O. 2590 */ 2591 age_stop(sc); 2592 2593 /* 2594 * Reset the chip to a known state. 2595 */ 2596 age_reset(sc); 2597 2598 /* Initialize descriptors. */ 2599 error = age_init_rx_ring(sc); 2600 if (error != 0) { 2601 device_printf(sc->age_dev, "no memory for Rx buffers.\n"); 2602 age_stop(sc); 2603 return; 2604 } 2605 age_init_rr_ring(sc); 2606 age_init_tx_ring(sc); 2607 age_init_cmb_block(sc); 2608 age_init_smb_block(sc); 2609 2610 /* Reprogram the station address. */ 2611 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2612 CSR_WRITE_4(sc, AGE_PAR0, 2613 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2614 CSR_WRITE_4(sc, AGE_PAR1, eaddr[0] << 8 | eaddr[1]); 2615 2616 /* Set descriptor base addresses. */ 2617 paddr = sc->age_rdata.age_tx_ring_paddr; 2618 CSR_WRITE_4(sc, AGE_DESC_ADDR_HI, AGE_ADDR_HI(paddr)); 2619 paddr = sc->age_rdata.age_rx_ring_paddr; 2620 CSR_WRITE_4(sc, AGE_DESC_RD_ADDR_LO, AGE_ADDR_LO(paddr)); 2621 paddr = sc->age_rdata.age_rr_ring_paddr; 2622 CSR_WRITE_4(sc, AGE_DESC_RRD_ADDR_LO, AGE_ADDR_LO(paddr)); 2623 paddr = sc->age_rdata.age_tx_ring_paddr; 2624 CSR_WRITE_4(sc, AGE_DESC_TPD_ADDR_LO, AGE_ADDR_LO(paddr)); 2625 paddr = sc->age_rdata.age_cmb_block_paddr; 2626 CSR_WRITE_4(sc, AGE_DESC_CMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2627 paddr = sc->age_rdata.age_smb_block_paddr; 2628 CSR_WRITE_4(sc, AGE_DESC_SMB_ADDR_LO, AGE_ADDR_LO(paddr)); 2629 /* Set Rx/Rx return descriptor counter. */ 2630 CSR_WRITE_4(sc, AGE_DESC_RRD_RD_CNT, 2631 ((AGE_RR_RING_CNT << DESC_RRD_CNT_SHIFT) & 2632 DESC_RRD_CNT_MASK) | 2633 ((AGE_RX_RING_CNT << DESC_RD_CNT_SHIFT) & DESC_RD_CNT_MASK)); 2634 /* Set Tx descriptor counter. */ 2635 CSR_WRITE_4(sc, AGE_DESC_TPD_CNT, 2636 (AGE_TX_RING_CNT << DESC_TPD_CNT_SHIFT) & DESC_TPD_CNT_MASK); 2637 2638 /* Tell hardware that we're ready to load descriptors. */ 2639 CSR_WRITE_4(sc, AGE_DMA_BLOCK, DMA_BLOCK_LOAD); 2640 2641 /* 2642 * Initialize mailbox register. 2643 * Updated producer/consumer index information is exchanged 2644 * through this mailbox register. However Tx producer and 2645 * Rx return consumer/Rx producer are all shared such that 2646 * it's hard to separate code path between Tx and Rx without 2647 * locking. If L1 hardware have a separate mail box register 2648 * for Tx and Rx consumer/producer management we could have 2649 * indepent Tx/Rx handler which in turn Rx handler could have 2650 * been run without any locking. 2651 */ 2652 AGE_COMMIT_MBOX(sc); 2653 2654 /* Configure IPG/IFG parameters. */ 2655 CSR_WRITE_4(sc, AGE_IPG_IFG_CFG, 2656 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK) | 2657 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2658 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2659 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK)); 2660 2661 /* Set parameters for half-duplex media. */ 2662 CSR_WRITE_4(sc, AGE_HDPX_CFG, 2663 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2664 HDPX_CFG_LCOL_MASK) | 2665 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2666 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2667 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2668 HDPX_CFG_ABEBT_MASK) | 2669 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2670 HDPX_CFG_JAMIPG_MASK)); 2671 2672 /* Configure interrupt moderation timer. */ 2673 CSR_WRITE_2(sc, AGE_IM_TIMER, AGE_USECS(sc->age_int_mod)); 2674 reg = CSR_READ_4(sc, AGE_MASTER_CFG); 2675 reg &= ~MASTER_MTIMER_ENB; 2676 if (AGE_USECS(sc->age_int_mod) == 0) 2677 reg &= ~MASTER_ITIMER_ENB; 2678 else 2679 reg |= MASTER_ITIMER_ENB; 2680 CSR_WRITE_4(sc, AGE_MASTER_CFG, reg); 2681 if (bootverbose) 2682 device_printf(sc->age_dev, "interrupt moderation is %d us.\n", 2683 sc->age_int_mod); 2684 CSR_WRITE_2(sc, AGE_INTR_CLR_TIMER, AGE_USECS(1000)); 2685 2686 /* Set Maximum frame size but don't let MTU be lass than ETHER_MTU. */ 2687 if (ifp->if_mtu < ETHERMTU) 2688 sc->age_max_frame_size = ETHERMTU; 2689 else 2690 sc->age_max_frame_size = ifp->if_mtu; 2691 sc->age_max_frame_size += ETHER_HDR_LEN + 2692 sizeof(struct ether_vlan_header) + ETHER_CRC_LEN; 2693 CSR_WRITE_4(sc, AGE_FRAME_SIZE, sc->age_max_frame_size); 2694 /* Configure jumbo frame. */ 2695 fsize = roundup(sc->age_max_frame_size, sizeof(uint64_t)); 2696 CSR_WRITE_4(sc, AGE_RXQ_JUMBO_CFG, 2697 (((fsize / sizeof(uint64_t)) << 2698 RXQ_JUMBO_CFG_SZ_THRESH_SHIFT) & RXQ_JUMBO_CFG_SZ_THRESH_MASK) | 2699 ((RXQ_JUMBO_CFG_LKAH_DEFAULT << 2700 RXQ_JUMBO_CFG_LKAH_SHIFT) & RXQ_JUMBO_CFG_LKAH_MASK) | 2701 ((AGE_USECS(8) << RXQ_JUMBO_CFG_RRD_TIMER_SHIFT) & 2702 RXQ_JUMBO_CFG_RRD_TIMER_MASK)); 2703 2704 /* Configure flow-control parameters. From Linux. */ 2705 if ((sc->age_flags & AGE_FLAG_PCIE) != 0) { 2706 /* 2707 * Magic workaround for old-L1. 2708 * Don't know which hw revision requires this magic. 2709 */ 2710 CSR_WRITE_4(sc, 0x12FC, 0x6500); 2711 /* 2712 * Another magic workaround for flow-control mode 2713 * change. From Linux. 2714 */ 2715 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2716 } 2717 /* 2718 * TODO 2719 * Should understand pause parameter relationships between FIFO 2720 * size and number of Rx descriptors and Rx return descriptors. 2721 * 2722 * Magic parameters came from Linux. 2723 */ 2724 switch (sc->age_chip_rev) { 2725 case 0x8001: 2726 case 0x9001: 2727 case 0x9002: 2728 case 0x9003: 2729 rxf_hi = AGE_RX_RING_CNT / 16; 2730 rxf_lo = (AGE_RX_RING_CNT * 7) / 8; 2731 rrd_hi = (AGE_RR_RING_CNT * 7) / 8; 2732 rrd_lo = AGE_RR_RING_CNT / 16; 2733 break; 2734 default: 2735 reg = CSR_READ_4(sc, AGE_SRAM_RX_FIFO_LEN); 2736 rxf_lo = reg / 16; 2737 if (rxf_lo < 192) 2738 rxf_lo = 192; 2739 rxf_hi = (reg * 7) / 8; 2740 if (rxf_hi < rxf_lo) 2741 rxf_hi = rxf_lo + 16; 2742 reg = CSR_READ_4(sc, AGE_SRAM_RRD_LEN); 2743 rrd_lo = reg / 8; 2744 rrd_hi = (reg * 7) / 8; 2745 if (rrd_lo < 2) 2746 rrd_lo = 2; 2747 if (rrd_hi < rrd_lo) 2748 rrd_hi = rrd_lo + 3; 2749 break; 2750 } 2751 CSR_WRITE_4(sc, AGE_RXQ_FIFO_PAUSE_THRESH, 2752 ((rxf_lo << RXQ_FIFO_PAUSE_THRESH_LO_SHIFT) & 2753 RXQ_FIFO_PAUSE_THRESH_LO_MASK) | 2754 ((rxf_hi << RXQ_FIFO_PAUSE_THRESH_HI_SHIFT) & 2755 RXQ_FIFO_PAUSE_THRESH_HI_MASK)); 2756 CSR_WRITE_4(sc, AGE_RXQ_RRD_PAUSE_THRESH, 2757 ((rrd_lo << RXQ_RRD_PAUSE_THRESH_LO_SHIFT) & 2758 RXQ_RRD_PAUSE_THRESH_LO_MASK) | 2759 ((rrd_hi << RXQ_RRD_PAUSE_THRESH_HI_SHIFT) & 2760 RXQ_RRD_PAUSE_THRESH_HI_MASK)); 2761 2762 /* Configure RxQ. */ 2763 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2764 ((RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 2765 RXQ_CFG_RD_BURST_MASK) | 2766 ((RXQ_CFG_RRD_BURST_THRESH_DEFAULT << 2767 RXQ_CFG_RRD_BURST_THRESH_SHIFT) & RXQ_CFG_RRD_BURST_THRESH_MASK) | 2768 ((RXQ_CFG_RD_PREF_MIN_IPG_DEFAULT << 2769 RXQ_CFG_RD_PREF_MIN_IPG_SHIFT) & RXQ_CFG_RD_PREF_MIN_IPG_MASK) | 2770 RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2771 2772 /* Configure TxQ. */ 2773 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2774 ((TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2775 TXQ_CFG_TPD_BURST_MASK) | 2776 ((TXQ_CFG_TX_FIFO_BURST_DEFAULT << TXQ_CFG_TX_FIFO_BURST_SHIFT) & 2777 TXQ_CFG_TX_FIFO_BURST_MASK) | 2778 ((TXQ_CFG_TPD_FETCH_DEFAULT << 2779 TXQ_CFG_TPD_FETCH_THRESH_SHIFT) & TXQ_CFG_TPD_FETCH_THRESH_MASK) | 2780 TXQ_CFG_ENB); 2781 2782 CSR_WRITE_4(sc, AGE_TX_JUMBO_TPD_TH_IPG, 2783 (((fsize / sizeof(uint64_t) << TX_JUMBO_TPD_TH_SHIFT)) & 2784 TX_JUMBO_TPD_TH_MASK) | 2785 ((TX_JUMBO_TPD_IPG_DEFAULT << TX_JUMBO_TPD_IPG_SHIFT) & 2786 TX_JUMBO_TPD_IPG_MASK)); 2787 /* Configure DMA parameters. */ 2788 CSR_WRITE_4(sc, AGE_DMA_CFG, 2789 DMA_CFG_ENH_ORDER | DMA_CFG_RCB_64 | 2790 sc->age_dma_rd_burst | DMA_CFG_RD_ENB | 2791 sc->age_dma_wr_burst | DMA_CFG_WR_ENB); 2792 2793 /* Configure CMB DMA write threshold. */ 2794 CSR_WRITE_4(sc, AGE_CMB_WR_THRESH, 2795 ((CMB_WR_THRESH_RRD_DEFAULT << CMB_WR_THRESH_RRD_SHIFT) & 2796 CMB_WR_THRESH_RRD_MASK) | 2797 ((CMB_WR_THRESH_TPD_DEFAULT << CMB_WR_THRESH_TPD_SHIFT) & 2798 CMB_WR_THRESH_TPD_MASK)); 2799 2800 /* Set CMB/SMB timer and enable them. */ 2801 CSR_WRITE_4(sc, AGE_CMB_WR_TIMER, 2802 ((AGE_USECS(2) << CMB_WR_TIMER_TX_SHIFT) & CMB_WR_TIMER_TX_MASK) | 2803 ((AGE_USECS(2) << CMB_WR_TIMER_RX_SHIFT) & CMB_WR_TIMER_RX_MASK)); 2804 /* Request SMB updates for every seconds. */ 2805 CSR_WRITE_4(sc, AGE_SMB_TIMER, AGE_USECS(1000 * 1000)); 2806 CSR_WRITE_4(sc, AGE_CSMB_CTRL, CSMB_CTRL_SMB_ENB | CSMB_CTRL_CMB_ENB); 2807 2808 /* 2809 * Disable all WOL bits as WOL can interfere normal Rx 2810 * operation. 2811 */ 2812 CSR_WRITE_4(sc, AGE_WOL_CFG, 0); 2813 2814 /* 2815 * Configure Tx/Rx MACs. 2816 * - Auto-padding for short frames. 2817 * - Enable CRC generation. 2818 * Start with full-duplex/1000Mbps media. Actual reconfiguration 2819 * of MAC is followed after link establishment. 2820 */ 2821 CSR_WRITE_4(sc, AGE_MAC_CFG, 2822 MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | 2823 MAC_CFG_FULL_DUPLEX | MAC_CFG_SPEED_1000 | 2824 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2825 MAC_CFG_PREAMBLE_MASK)); 2826 /* Set up the receive filter. */ 2827 age_rxfilter(sc); 2828 age_rxvlan(sc); 2829 2830 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2831 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 2832 reg |= MAC_CFG_RXCSUM_ENB; 2833 2834 /* Ack all pending interrupts and clear it. */ 2835 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0); 2836 CSR_WRITE_4(sc, AGE_INTR_MASK, AGE_INTRS); 2837 2838 /* Finally enable Tx/Rx MAC. */ 2839 CSR_WRITE_4(sc, AGE_MAC_CFG, reg | MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2840 2841 sc->age_flags &= ~AGE_FLAG_LINK; 2842 /* Switch to the current media. */ 2843 mii_mediachg(mii); 2844 2845 callout_reset(&sc->age_tick_ch, hz, age_tick, sc); 2846 2847 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2848 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2849 } 2850 2851 static void 2852 age_stop(struct age_softc *sc) 2853 { 2854 struct ifnet *ifp; 2855 struct age_txdesc *txd; 2856 struct age_rxdesc *rxd; 2857 uint32_t reg; 2858 int i; 2859 2860 AGE_LOCK_ASSERT(sc); 2861 /* 2862 * Mark the interface down and cancel the watchdog timer. 2863 */ 2864 ifp = sc->age_ifp; 2865 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2866 sc->age_flags &= ~AGE_FLAG_LINK; 2867 callout_stop(&sc->age_tick_ch); 2868 sc->age_watchdog_timer = 0; 2869 2870 /* 2871 * Disable interrupts. 2872 */ 2873 CSR_WRITE_4(sc, AGE_INTR_MASK, 0); 2874 CSR_WRITE_4(sc, AGE_INTR_STATUS, 0xFFFFFFFF); 2875 /* Stop CMB/SMB updates. */ 2876 CSR_WRITE_4(sc, AGE_CSMB_CTRL, 0); 2877 /* Stop Rx/Tx MAC. */ 2878 age_stop_rxmac(sc); 2879 age_stop_txmac(sc); 2880 /* Stop DMA. */ 2881 CSR_WRITE_4(sc, AGE_DMA_CFG, 2882 CSR_READ_4(sc, AGE_DMA_CFG) & ~(DMA_CFG_RD_ENB | DMA_CFG_WR_ENB)); 2883 /* Stop TxQ/RxQ. */ 2884 CSR_WRITE_4(sc, AGE_TXQ_CFG, 2885 CSR_READ_4(sc, AGE_TXQ_CFG) & ~TXQ_CFG_ENB); 2886 CSR_WRITE_4(sc, AGE_RXQ_CFG, 2887 CSR_READ_4(sc, AGE_RXQ_CFG) & ~RXQ_CFG_ENB); 2888 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2889 if ((reg = CSR_READ_4(sc, AGE_IDLE_STATUS)) == 0) 2890 break; 2891 DELAY(10); 2892 } 2893 if (i == 0) 2894 device_printf(sc->age_dev, 2895 "stopping Rx/Tx MACs timed out(0x%08x)!\n", reg); 2896 2897 /* Reclaim Rx buffers that have been processed. */ 2898 if (sc->age_cdata.age_rxhead != NULL) 2899 m_freem(sc->age_cdata.age_rxhead); 2900 AGE_RXCHAIN_RESET(sc); 2901 /* 2902 * Free RX and TX mbufs still in the queues. 2903 */ 2904 for (i = 0; i < AGE_RX_RING_CNT; i++) { 2905 rxd = &sc->age_cdata.age_rxdesc[i]; 2906 if (rxd->rx_m != NULL) { 2907 bus_dmamap_sync(sc->age_cdata.age_rx_tag, 2908 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 2909 bus_dmamap_unload(sc->age_cdata.age_rx_tag, 2910 rxd->rx_dmamap); 2911 m_freem(rxd->rx_m); 2912 rxd->rx_m = NULL; 2913 } 2914 } 2915 for (i = 0; i < AGE_TX_RING_CNT; i++) { 2916 txd = &sc->age_cdata.age_txdesc[i]; 2917 if (txd->tx_m != NULL) { 2918 bus_dmamap_sync(sc->age_cdata.age_tx_tag, 2919 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2920 bus_dmamap_unload(sc->age_cdata.age_tx_tag, 2921 txd->tx_dmamap); 2922 m_freem(txd->tx_m); 2923 txd->tx_m = NULL; 2924 } 2925 } 2926 } 2927 2928 static void 2929 age_stop_txmac(struct age_softc *sc) 2930 { 2931 uint32_t reg; 2932 int i; 2933 2934 AGE_LOCK_ASSERT(sc); 2935 2936 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2937 if ((reg & MAC_CFG_TX_ENB) != 0) { 2938 reg &= ~MAC_CFG_TX_ENB; 2939 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2940 } 2941 /* Stop Tx DMA engine. */ 2942 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2943 if ((reg & DMA_CFG_RD_ENB) != 0) { 2944 reg &= ~DMA_CFG_RD_ENB; 2945 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2946 } 2947 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2948 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2949 (IDLE_STATUS_TXMAC | IDLE_STATUS_DMARD)) == 0) 2950 break; 2951 DELAY(10); 2952 } 2953 if (i == 0) 2954 device_printf(sc->age_dev, "stopping TxMAC timeout!\n"); 2955 } 2956 2957 static void 2958 age_stop_rxmac(struct age_softc *sc) 2959 { 2960 uint32_t reg; 2961 int i; 2962 2963 AGE_LOCK_ASSERT(sc); 2964 2965 reg = CSR_READ_4(sc, AGE_MAC_CFG); 2966 if ((reg & MAC_CFG_RX_ENB) != 0) { 2967 reg &= ~MAC_CFG_RX_ENB; 2968 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 2969 } 2970 /* Stop Rx DMA engine. */ 2971 reg = CSR_READ_4(sc, AGE_DMA_CFG); 2972 if ((reg & DMA_CFG_WR_ENB) != 0) { 2973 reg &= ~DMA_CFG_WR_ENB; 2974 CSR_WRITE_4(sc, AGE_DMA_CFG, reg); 2975 } 2976 for (i = AGE_RESET_TIMEOUT; i > 0; i--) { 2977 if ((CSR_READ_4(sc, AGE_IDLE_STATUS) & 2978 (IDLE_STATUS_RXMAC | IDLE_STATUS_DMAWR)) == 0) 2979 break; 2980 DELAY(10); 2981 } 2982 if (i == 0) 2983 device_printf(sc->age_dev, "stopping RxMAC timeout!\n"); 2984 } 2985 2986 static void 2987 age_init_tx_ring(struct age_softc *sc) 2988 { 2989 struct age_ring_data *rd; 2990 struct age_txdesc *txd; 2991 int i; 2992 2993 AGE_LOCK_ASSERT(sc); 2994 2995 sc->age_cdata.age_tx_prod = 0; 2996 sc->age_cdata.age_tx_cons = 0; 2997 sc->age_cdata.age_tx_cnt = 0; 2998 2999 rd = &sc->age_rdata; 3000 bzero(rd->age_tx_ring, AGE_TX_RING_SZ); 3001 for (i = 0; i < AGE_TX_RING_CNT; i++) { 3002 txd = &sc->age_cdata.age_txdesc[i]; 3003 txd->tx_desc = &rd->age_tx_ring[i]; 3004 txd->tx_m = NULL; 3005 } 3006 3007 bus_dmamap_sync(sc->age_cdata.age_tx_ring_tag, 3008 sc->age_cdata.age_tx_ring_map, 3009 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3010 } 3011 3012 static int 3013 age_init_rx_ring(struct age_softc *sc) 3014 { 3015 struct age_ring_data *rd; 3016 struct age_rxdesc *rxd; 3017 int i; 3018 3019 AGE_LOCK_ASSERT(sc); 3020 3021 sc->age_cdata.age_rx_cons = AGE_RX_RING_CNT - 1; 3022 sc->age_morework = 0; 3023 rd = &sc->age_rdata; 3024 bzero(rd->age_rx_ring, AGE_RX_RING_SZ); 3025 for (i = 0; i < AGE_RX_RING_CNT; i++) { 3026 rxd = &sc->age_cdata.age_rxdesc[i]; 3027 rxd->rx_m = NULL; 3028 rxd->rx_desc = &rd->age_rx_ring[i]; 3029 if (age_newbuf(sc, rxd) != 0) 3030 return (ENOBUFS); 3031 } 3032 3033 bus_dmamap_sync(sc->age_cdata.age_rx_ring_tag, 3034 sc->age_cdata.age_rx_ring_map, BUS_DMASYNC_PREWRITE); 3035 3036 return (0); 3037 } 3038 3039 static void 3040 age_init_rr_ring(struct age_softc *sc) 3041 { 3042 struct age_ring_data *rd; 3043 3044 AGE_LOCK_ASSERT(sc); 3045 3046 sc->age_cdata.age_rr_cons = 0; 3047 AGE_RXCHAIN_RESET(sc); 3048 3049 rd = &sc->age_rdata; 3050 bzero(rd->age_rr_ring, AGE_RR_RING_SZ); 3051 bus_dmamap_sync(sc->age_cdata.age_rr_ring_tag, 3052 sc->age_cdata.age_rr_ring_map, 3053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3054 } 3055 3056 static void 3057 age_init_cmb_block(struct age_softc *sc) 3058 { 3059 struct age_ring_data *rd; 3060 3061 AGE_LOCK_ASSERT(sc); 3062 3063 rd = &sc->age_rdata; 3064 bzero(rd->age_cmb_block, AGE_CMB_BLOCK_SZ); 3065 bus_dmamap_sync(sc->age_cdata.age_cmb_block_tag, 3066 sc->age_cdata.age_cmb_block_map, 3067 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3068 } 3069 3070 static void 3071 age_init_smb_block(struct age_softc *sc) 3072 { 3073 struct age_ring_data *rd; 3074 3075 AGE_LOCK_ASSERT(sc); 3076 3077 rd = &sc->age_rdata; 3078 bzero(rd->age_smb_block, AGE_SMB_BLOCK_SZ); 3079 bus_dmamap_sync(sc->age_cdata.age_smb_block_tag, 3080 sc->age_cdata.age_smb_block_map, 3081 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3082 } 3083 3084 static int 3085 age_newbuf(struct age_softc *sc, struct age_rxdesc *rxd) 3086 { 3087 struct rx_desc *desc; 3088 struct mbuf *m; 3089 bus_dma_segment_t segs[1]; 3090 bus_dmamap_t map; 3091 int nsegs; 3092 3093 AGE_LOCK_ASSERT(sc); 3094 3095 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3096 if (m == NULL) 3097 return (ENOBUFS); 3098 m->m_len = m->m_pkthdr.len = MCLBYTES; 3099 #ifndef __NO_STRICT_ALIGNMENT 3100 m_adj(m, AGE_RX_BUF_ALIGN); 3101 #endif 3102 3103 if (bus_dmamap_load_mbuf_sg(sc->age_cdata.age_rx_tag, 3104 sc->age_cdata.age_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3105 m_freem(m); 3106 return (ENOBUFS); 3107 } 3108 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3109 3110 if (rxd->rx_m != NULL) { 3111 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3112 BUS_DMASYNC_POSTREAD); 3113 bus_dmamap_unload(sc->age_cdata.age_rx_tag, rxd->rx_dmamap); 3114 } 3115 map = rxd->rx_dmamap; 3116 rxd->rx_dmamap = sc->age_cdata.age_rx_sparemap; 3117 sc->age_cdata.age_rx_sparemap = map; 3118 bus_dmamap_sync(sc->age_cdata.age_rx_tag, rxd->rx_dmamap, 3119 BUS_DMASYNC_PREREAD); 3120 rxd->rx_m = m; 3121 3122 desc = rxd->rx_desc; 3123 desc->addr = htole64(segs[0].ds_addr); 3124 desc->len = htole32((segs[0].ds_len & AGE_RD_LEN_MASK) << 3125 AGE_RD_LEN_SHIFT); 3126 return (0); 3127 } 3128 3129 static void 3130 age_rxvlan(struct age_softc *sc) 3131 { 3132 struct ifnet *ifp; 3133 uint32_t reg; 3134 3135 AGE_LOCK_ASSERT(sc); 3136 3137 ifp = sc->age_ifp; 3138 reg = CSR_READ_4(sc, AGE_MAC_CFG); 3139 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3140 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3141 reg |= MAC_CFG_VLAN_TAG_STRIP; 3142 CSR_WRITE_4(sc, AGE_MAC_CFG, reg); 3143 } 3144 3145 static void 3146 age_rxfilter(struct age_softc *sc) 3147 { 3148 struct ifnet *ifp; 3149 struct ifmultiaddr *ifma; 3150 uint32_t crc; 3151 uint32_t mchash[2]; 3152 uint32_t rxcfg; 3153 3154 AGE_LOCK_ASSERT(sc); 3155 3156 ifp = sc->age_ifp; 3157 3158 rxcfg = CSR_READ_4(sc, AGE_MAC_CFG); 3159 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3160 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3161 rxcfg |= MAC_CFG_BCAST; 3162 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3163 if ((ifp->if_flags & IFF_PROMISC) != 0) 3164 rxcfg |= MAC_CFG_PROMISC; 3165 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3166 rxcfg |= MAC_CFG_ALLMULTI; 3167 CSR_WRITE_4(sc, AGE_MAR0, 0xFFFFFFFF); 3168 CSR_WRITE_4(sc, AGE_MAR1, 0xFFFFFFFF); 3169 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3170 return; 3171 } 3172 3173 /* Program new filter. */ 3174 bzero(mchash, sizeof(mchash)); 3175 3176 if_maddr_rlock(ifp); 3177 TAILQ_FOREACH(ifma, &sc->age_ifp->if_multiaddrs, ifma_link) { 3178 if (ifma->ifma_addr->sa_family != AF_LINK) 3179 continue; 3180 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3181 ifma->ifma_addr), ETHER_ADDR_LEN); 3182 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3183 } 3184 if_maddr_runlock(ifp); 3185 3186 CSR_WRITE_4(sc, AGE_MAR0, mchash[0]); 3187 CSR_WRITE_4(sc, AGE_MAR1, mchash[1]); 3188 CSR_WRITE_4(sc, AGE_MAC_CFG, rxcfg); 3189 } 3190 3191 static int 3192 sysctl_age_stats(SYSCTL_HANDLER_ARGS) 3193 { 3194 struct age_softc *sc; 3195 struct age_stats *stats; 3196 int error, result; 3197 3198 result = -1; 3199 error = sysctl_handle_int(oidp, &result, 0, req); 3200 3201 if (error != 0 || req->newptr == NULL) 3202 return (error); 3203 3204 if (result != 1) 3205 return (error); 3206 3207 sc = (struct age_softc *)arg1; 3208 stats = &sc->age_stat; 3209 printf("%s statistics:\n", device_get_nameunit(sc->age_dev)); 3210 printf("Transmit good frames : %ju\n", 3211 (uintmax_t)stats->tx_frames); 3212 printf("Transmit good broadcast frames : %ju\n", 3213 (uintmax_t)stats->tx_bcast_frames); 3214 printf("Transmit good multicast frames : %ju\n", 3215 (uintmax_t)stats->tx_mcast_frames); 3216 printf("Transmit pause control frames : %u\n", 3217 stats->tx_pause_frames); 3218 printf("Transmit control frames : %u\n", 3219 stats->tx_control_frames); 3220 printf("Transmit frames with excessive deferrals : %u\n", 3221 stats->tx_excess_defer); 3222 printf("Transmit deferrals : %u\n", 3223 stats->tx_deferred); 3224 printf("Transmit good octets : %ju\n", 3225 (uintmax_t)stats->tx_bytes); 3226 printf("Transmit good broadcast octets : %ju\n", 3227 (uintmax_t)stats->tx_bcast_bytes); 3228 printf("Transmit good multicast octets : %ju\n", 3229 (uintmax_t)stats->tx_mcast_bytes); 3230 printf("Transmit frames 64 bytes : %ju\n", 3231 (uintmax_t)stats->tx_pkts_64); 3232 printf("Transmit frames 65 to 127 bytes : %ju\n", 3233 (uintmax_t)stats->tx_pkts_65_127); 3234 printf("Transmit frames 128 to 255 bytes : %ju\n", 3235 (uintmax_t)stats->tx_pkts_128_255); 3236 printf("Transmit frames 256 to 511 bytes : %ju\n", 3237 (uintmax_t)stats->tx_pkts_256_511); 3238 printf("Transmit frames 512 to 1024 bytes : %ju\n", 3239 (uintmax_t)stats->tx_pkts_512_1023); 3240 printf("Transmit frames 1024 to 1518 bytes : %ju\n", 3241 (uintmax_t)stats->tx_pkts_1024_1518); 3242 printf("Transmit frames 1519 to MTU bytes : %ju\n", 3243 (uintmax_t)stats->tx_pkts_1519_max); 3244 printf("Transmit single collisions : %u\n", 3245 stats->tx_single_colls); 3246 printf("Transmit multiple collisions : %u\n", 3247 stats->tx_multi_colls); 3248 printf("Transmit late collisions : %u\n", 3249 stats->tx_late_colls); 3250 printf("Transmit abort due to excessive collisions : %u\n", 3251 stats->tx_excess_colls); 3252 printf("Transmit underruns due to FIFO underruns : %u\n", 3253 stats->tx_underrun); 3254 printf("Transmit descriptor write-back errors : %u\n", 3255 stats->tx_desc_underrun); 3256 printf("Transmit frames with length mismatched frame size : %u\n", 3257 stats->tx_lenerrs); 3258 printf("Transmit frames with truncated due to MTU size : %u\n", 3259 stats->tx_lenerrs); 3260 3261 printf("Receive good frames : %ju\n", 3262 (uintmax_t)stats->rx_frames); 3263 printf("Receive good broadcast frames : %ju\n", 3264 (uintmax_t)stats->rx_bcast_frames); 3265 printf("Receive good multicast frames : %ju\n", 3266 (uintmax_t)stats->rx_mcast_frames); 3267 printf("Receive pause control frames : %u\n", 3268 stats->rx_pause_frames); 3269 printf("Receive control frames : %u\n", 3270 stats->rx_control_frames); 3271 printf("Receive CRC errors : %u\n", 3272 stats->rx_crcerrs); 3273 printf("Receive frames with length errors : %u\n", 3274 stats->rx_lenerrs); 3275 printf("Receive good octets : %ju\n", 3276 (uintmax_t)stats->rx_bytes); 3277 printf("Receive good broadcast octets : %ju\n", 3278 (uintmax_t)stats->rx_bcast_bytes); 3279 printf("Receive good multicast octets : %ju\n", 3280 (uintmax_t)stats->rx_mcast_bytes); 3281 printf("Receive frames too short : %u\n", 3282 stats->rx_runts); 3283 printf("Receive fragmented frames : %ju\n", 3284 (uintmax_t)stats->rx_fragments); 3285 printf("Receive frames 64 bytes : %ju\n", 3286 (uintmax_t)stats->rx_pkts_64); 3287 printf("Receive frames 65 to 127 bytes : %ju\n", 3288 (uintmax_t)stats->rx_pkts_65_127); 3289 printf("Receive frames 128 to 255 bytes : %ju\n", 3290 (uintmax_t)stats->rx_pkts_128_255); 3291 printf("Receive frames 256 to 511 bytes : %ju\n", 3292 (uintmax_t)stats->rx_pkts_256_511); 3293 printf("Receive frames 512 to 1024 bytes : %ju\n", 3294 (uintmax_t)stats->rx_pkts_512_1023); 3295 printf("Receive frames 1024 to 1518 bytes : %ju\n", 3296 (uintmax_t)stats->rx_pkts_1024_1518); 3297 printf("Receive frames 1519 to MTU bytes : %ju\n", 3298 (uintmax_t)stats->rx_pkts_1519_max); 3299 printf("Receive frames too long : %ju\n", 3300 (uint64_t)stats->rx_pkts_truncated); 3301 printf("Receive frames with FIFO overflow : %u\n", 3302 stats->rx_fifo_oflows); 3303 printf("Receive frames with return descriptor overflow : %u\n", 3304 stats->rx_desc_oflows); 3305 printf("Receive frames with alignment errors : %u\n", 3306 stats->rx_alignerrs); 3307 printf("Receive frames dropped due to address filtering : %ju\n", 3308 (uint64_t)stats->rx_pkts_filtered); 3309 3310 return (error); 3311 } 3312 3313 static int 3314 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3315 { 3316 int error, value; 3317 3318 if (arg1 == NULL) 3319 return (EINVAL); 3320 value = *(int *)arg1; 3321 error = sysctl_handle_int(oidp, &value, 0, req); 3322 if (error || req->newptr == NULL) 3323 return (error); 3324 if (value < low || value > high) 3325 return (EINVAL); 3326 *(int *)arg1 = value; 3327 3328 return (0); 3329 } 3330 3331 static int 3332 sysctl_hw_age_proc_limit(SYSCTL_HANDLER_ARGS) 3333 { 3334 return (sysctl_int_range(oidp, arg1, arg2, req, 3335 AGE_PROC_MIN, AGE_PROC_MAX)); 3336 } 3337 3338 static int 3339 sysctl_hw_age_int_mod(SYSCTL_HANDLER_ARGS) 3340 { 3341 3342 return (sysctl_int_range(oidp, arg1, arg2, req, AGE_IM_TIMER_MIN, 3343 AGE_IM_TIMER_MAX)); 3344 } 3345