1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * Copyright (c) 2009-2012 Alexander Motin <mav@FreeBSD.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification, immediately at the beginning of the file. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 18 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 19 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 20 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 21 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 25 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 /* ATA register defines */ 31 #define ATA_DATA 0 /* (RW) data */ 32 33 #define ATA_FEATURE 1 /* (W) feature */ 34 #define ATA_F_DMA 0x01 /* enable DMA */ 35 #define ATA_F_OVL 0x02 /* enable overlap */ 36 37 #define ATA_COUNT 2 /* (W) sector count */ 38 39 #define ATA_SECTOR 3 /* (RW) sector # */ 40 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 41 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 42 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 43 #define ATA_D_LBA 0x40 /* use LBA addressing */ 44 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 45 46 #define ATA_COMMAND 7 /* (W) command */ 47 48 #define ATA_ERROR 8 /* (R) error */ 49 #define ATA_E_ILI 0x01 /* illegal length */ 50 #define ATA_E_NM 0x02 /* no media */ 51 #define ATA_E_ABORT 0x04 /* command aborted */ 52 #define ATA_E_MCR 0x08 /* media change request */ 53 #define ATA_E_IDNF 0x10 /* ID not found */ 54 #define ATA_E_MC 0x20 /* media changed */ 55 #define ATA_E_UNC 0x40 /* uncorrectable data */ 56 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 57 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 58 59 #define ATA_IREASON 9 /* (R) interrupt reason */ 60 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 61 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 62 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 63 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 64 65 #define ATA_STATUS 10 /* (R) status */ 66 #define ATA_ALTSTAT 11 /* (R) alternate status */ 67 #define ATA_S_ERROR 0x01 /* error */ 68 #define ATA_S_INDEX 0x02 /* index */ 69 #define ATA_S_CORR 0x04 /* data corrected */ 70 #define ATA_S_DRQ 0x08 /* data request */ 71 #define ATA_S_DSC 0x10 /* drive seek completed */ 72 #define ATA_S_SERVICE 0x10 /* drive needs service */ 73 #define ATA_S_DWF 0x20 /* drive write fault */ 74 #define ATA_S_DMA 0x20 /* DMA ready */ 75 #define ATA_S_READY 0x40 /* drive ready */ 76 #define ATA_S_BUSY 0x80 /* busy */ 77 78 #define ATA_CONTROL 12 /* (W) control */ 79 #define ATA_A_IDS 0x02 /* disable interrupts */ 80 #define ATA_A_RESET 0x04 /* RESET controller */ 81 #define ATA_A_4BIT 0x08 /* 4 head bits */ 82 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 83 84 /* SATA register defines */ 85 #define ATA_SSTATUS 13 86 #define ATA_SS_DET_MASK 0x0000000f 87 #define ATA_SS_DET_NO_DEVICE 0x00000000 88 #define ATA_SS_DET_DEV_PRESENT 0x00000001 89 #define ATA_SS_DET_PHY_ONLINE 0x00000003 90 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 91 92 #define ATA_SS_SPD_MASK 0x000000f0 93 #define ATA_SS_SPD_NO_SPEED 0x00000000 94 #define ATA_SS_SPD_GEN1 0x00000010 95 #define ATA_SS_SPD_GEN2 0x00000020 96 #define ATA_SS_SPD_GEN3 0x00000030 97 98 #define ATA_SS_IPM_MASK 0x00000f00 99 #define ATA_SS_IPM_NO_DEVICE 0x00000000 100 #define ATA_SS_IPM_ACTIVE 0x00000100 101 #define ATA_SS_IPM_PARTIAL 0x00000200 102 #define ATA_SS_IPM_SLUMBER 0x00000600 103 #define ATA_SS_IPM_DEVSLEEP 0x00000800 104 105 #define ATA_SERROR 14 106 #define ATA_SE_DATA_CORRECTED 0x00000001 107 #define ATA_SE_COMM_CORRECTED 0x00000002 108 #define ATA_SE_DATA_ERR 0x00000100 109 #define ATA_SE_COMM_ERR 0x00000200 110 #define ATA_SE_PROT_ERR 0x00000400 111 #define ATA_SE_HOST_ERR 0x00000800 112 #define ATA_SE_PHY_CHANGED 0x00010000 113 #define ATA_SE_PHY_IERROR 0x00020000 114 #define ATA_SE_COMM_WAKE 0x00040000 115 #define ATA_SE_DECODE_ERR 0x00080000 116 #define ATA_SE_PARITY_ERR 0x00100000 117 #define ATA_SE_CRC_ERR 0x00200000 118 #define ATA_SE_HANDSHAKE_ERR 0x00400000 119 #define ATA_SE_LINKSEQ_ERR 0x00800000 120 #define ATA_SE_TRANSPORT_ERR 0x01000000 121 #define ATA_SE_UNKNOWN_FIS 0x02000000 122 #define ATA_SE_EXCHANGED 0x04000000 123 124 #define ATA_SCONTROL 15 125 #define ATA_SC_DET_MASK 0x0000000f 126 #define ATA_SC_DET_IDLE 0x00000000 127 #define ATA_SC_DET_RESET 0x00000001 128 #define ATA_SC_DET_DISABLE 0x00000004 129 130 #define ATA_SC_SPD_MASK 0x000000f0 131 #define ATA_SC_SPD_NO_SPEED 0x00000000 132 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 133 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 134 #define ATA_SC_SPD_SPEED_GEN3 0x00000030 135 136 #define ATA_SC_IPM_MASK 0x00000f00 137 #define ATA_SC_IPM_NONE 0x00000000 138 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 139 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 140 #define ATA_SC_IPM_DIS_DEVSLEEP 0x00000400 141 142 #define ATA_SACTIVE 16 143 144 #define AHCI_MAX_PORTS 32 145 #define AHCI_MAX_SLOTS 32 146 #define AHCI_MAX_IRQS 16 147 148 /* SATA AHCI v1.0 register defines */ 149 #define AHCI_CAP 0x00 150 #define AHCI_CAP_NPMASK 0x0000001f 151 #define AHCI_CAP_SXS 0x00000020 152 #define AHCI_CAP_EMS 0x00000040 153 #define AHCI_CAP_CCCS 0x00000080 154 #define AHCI_CAP_NCS 0x00001F00 155 #define AHCI_CAP_NCS_SHIFT 8 156 #define AHCI_CAP_PSC 0x00002000 157 #define AHCI_CAP_SSC 0x00004000 158 #define AHCI_CAP_PMD 0x00008000 159 #define AHCI_CAP_FBSS 0x00010000 160 #define AHCI_CAP_SPM 0x00020000 161 #define AHCI_CAP_SAM 0x00080000 162 #define AHCI_CAP_ISS 0x00F00000 163 #define AHCI_CAP_ISS_SHIFT 20 164 #define AHCI_CAP_SCLO 0x01000000 165 #define AHCI_CAP_SAL 0x02000000 166 #define AHCI_CAP_SALP 0x04000000 167 #define AHCI_CAP_SSS 0x08000000 168 #define AHCI_CAP_SMPS 0x10000000 169 #define AHCI_CAP_SSNTF 0x20000000 170 #define AHCI_CAP_SNCQ 0x40000000 171 #define AHCI_CAP_64BIT 0x80000000 172 173 #define AHCI_GHC 0x04 174 #define AHCI_GHC_AE 0x80000000 175 #define AHCI_GHC_MRSM 0x00000004 176 #define AHCI_GHC_IE 0x00000002 177 #define AHCI_GHC_HR 0x00000001 178 179 #define AHCI_IS 0x08 180 #define AHCI_PI 0x0c 181 #define AHCI_VS 0x10 182 183 #define AHCI_CCCC 0x14 184 #define AHCI_CCCC_TV_MASK 0xffff0000 185 #define AHCI_CCCC_TV_SHIFT 16 186 #define AHCI_CCCC_CC_MASK 0x0000ff00 187 #define AHCI_CCCC_CC_SHIFT 8 188 #define AHCI_CCCC_INT_MASK 0x000000f8 189 #define AHCI_CCCC_INT_SHIFT 3 190 #define AHCI_CCCC_EN 0x00000001 191 #define AHCI_CCCP 0x18 192 193 #define AHCI_EM_LOC 0x1C 194 #define AHCI_EM_CTL 0x20 195 #define AHCI_EM_MR 0x00000001 196 #define AHCI_EM_TM 0x00000100 197 #define AHCI_EM_RST 0x00000200 198 #define AHCI_EM_LED 0x00010000 199 #define AHCI_EM_SAFTE 0x00020000 200 #define AHCI_EM_SES2 0x00040000 201 #define AHCI_EM_SGPIO 0x00080000 202 #define AHCI_EM_SMB 0x01000000 203 #define AHCI_EM_XMT 0x02000000 204 #define AHCI_EM_ALHD 0x04000000 205 #define AHCI_EM_PM 0x08000000 206 207 #define AHCI_CAP2 0x24 208 #define AHCI_CAP2_BOH 0x00000001 209 #define AHCI_CAP2_NVMP 0x00000002 210 #define AHCI_CAP2_APST 0x00000004 211 #define AHCI_CAP2_SDS 0x00000008 212 #define AHCI_CAP2_SADM 0x00000010 213 #define AHCI_CAP2_DESO 0x00000020 214 215 #define AHCI_OFFSET 0x100 216 #define AHCI_STEP 0x80 217 218 #define AHCI_P_CLB 0x00 219 #define AHCI_P_CLBU 0x04 220 #define AHCI_P_FB 0x08 221 #define AHCI_P_FBU 0x0c 222 #define AHCI_P_IS 0x10 223 #define AHCI_P_IE 0x14 224 #define AHCI_P_IX_DHR 0x00000001 225 #define AHCI_P_IX_PS 0x00000002 226 #define AHCI_P_IX_DS 0x00000004 227 #define AHCI_P_IX_SDB 0x00000008 228 #define AHCI_P_IX_UF 0x00000010 229 #define AHCI_P_IX_DP 0x00000020 230 #define AHCI_P_IX_PC 0x00000040 231 #define AHCI_P_IX_MP 0x00000080 232 233 #define AHCI_P_IX_PRC 0x00400000 234 #define AHCI_P_IX_IPM 0x00800000 235 #define AHCI_P_IX_OF 0x01000000 236 #define AHCI_P_IX_INF 0x04000000 237 #define AHCI_P_IX_IF 0x08000000 238 #define AHCI_P_IX_HBD 0x10000000 239 #define AHCI_P_IX_HBF 0x20000000 240 #define AHCI_P_IX_TFE 0x40000000 241 #define AHCI_P_IX_CPD 0x80000000 242 243 #define AHCI_P_CMD 0x18 244 #define AHCI_P_CMD_ST 0x00000001 245 #define AHCI_P_CMD_SUD 0x00000002 246 #define AHCI_P_CMD_POD 0x00000004 247 #define AHCI_P_CMD_CLO 0x00000008 248 #define AHCI_P_CMD_FRE 0x00000010 249 #define AHCI_P_CMD_CCS_MASK 0x00001f00 250 #define AHCI_P_CMD_CCS_SHIFT 8 251 #define AHCI_P_CMD_ISS 0x00002000 252 #define AHCI_P_CMD_FR 0x00004000 253 #define AHCI_P_CMD_CR 0x00008000 254 #define AHCI_P_CMD_CPS 0x00010000 255 #define AHCI_P_CMD_PMA 0x00020000 256 #define AHCI_P_CMD_HPCP 0x00040000 257 #define AHCI_P_CMD_MPSP 0x00080000 258 #define AHCI_P_CMD_CPD 0x00100000 259 #define AHCI_P_CMD_ESP 0x00200000 260 #define AHCI_P_CMD_FBSCP 0x00400000 261 #define AHCI_P_CMD_APSTE 0x00800000 262 #define AHCI_P_CMD_ATAPI 0x01000000 263 #define AHCI_P_CMD_DLAE 0x02000000 264 #define AHCI_P_CMD_ALPE 0x04000000 265 #define AHCI_P_CMD_ASP 0x08000000 266 #define AHCI_P_CMD_ICC_MASK 0xf0000000 267 #define AHCI_P_CMD_NOOP 0x00000000 268 #define AHCI_P_CMD_ACTIVE 0x10000000 269 #define AHCI_P_CMD_PARTIAL 0x20000000 270 #define AHCI_P_CMD_SLUMBER 0x60000000 271 #define AHCI_P_CMD_DEVSLEEP 0x80000000 272 273 #define AHCI_P_TFD 0x20 274 #define AHCI_P_SIG 0x24 275 #define AHCI_P_SSTS 0x28 276 #define AHCI_P_SCTL 0x2c 277 #define AHCI_P_SERR 0x30 278 #define AHCI_P_SACT 0x34 279 #define AHCI_P_CI 0x38 280 #define AHCI_P_SNTF 0x3C 281 #define AHCI_P_FBS 0x40 282 #define AHCI_P_FBS_EN 0x00000001 283 #define AHCI_P_FBS_DEC 0x00000002 284 #define AHCI_P_FBS_SDE 0x00000004 285 #define AHCI_P_FBS_DEV 0x00000f00 286 #define AHCI_P_FBS_DEV_SHIFT 8 287 #define AHCI_P_FBS_ADO 0x0000f000 288 #define AHCI_P_FBS_ADO_SHIFT 12 289 #define AHCI_P_FBS_DWE 0x000f0000 290 #define AHCI_P_FBS_DWE_SHIFT 16 291 #define AHCI_P_DEVSLP 0x44 292 #define AHCI_P_DEVSLP_ADSE 0x00000001 293 #define AHCI_P_DEVSLP_DSP 0x00000002 294 #define AHCI_P_DEVSLP_DETO 0x000003fc 295 #define AHCI_P_DEVSLP_DETO_SHIFT 2 296 #define AHCI_P_DEVSLP_MDAT 0x00007c00 297 #define AHCI_P_DEVSLP_MDAT_SHIFT 10 298 #define AHCI_P_DEVSLP_DITO 0x01ff8000 299 #define AHCI_P_DEVSLP_DITO_SHIFT 15 300 #define AHCI_P_DEVSLP_DM 0x0e000000 301 #define AHCI_P_DEVSLP_DM_SHIFT 25 302 303 /* Just to be sure, if building as module. */ 304 #if MAXPHYS < 512 * 1024 305 #undef MAXPHYS 306 #define MAXPHYS 512 * 1024 307 #endif 308 /* Pessimistic prognosis on number of required S/G entries */ 309 #define AHCI_SG_ENTRIES (roundup(btoc(MAXPHYS) + 1, 8)) 310 /* Command list. 32 commands. First, 1Kbyte aligned. */ 311 #define AHCI_CL_OFFSET 0 312 #define AHCI_CL_SIZE 32 313 /* Command tables. Up to 32 commands, Each, 128byte aligned. */ 314 #define AHCI_CT_OFFSET (AHCI_CL_OFFSET + AHCI_CL_SIZE * AHCI_MAX_SLOTS) 315 #define AHCI_CT_SIZE (128 + AHCI_SG_ENTRIES * 16) 316 /* Total main work area. */ 317 #define AHCI_WORK_SIZE (AHCI_CT_OFFSET + AHCI_CT_SIZE * ch->numslots) 318 319 struct ahci_dma_prd { 320 u_int64_t dba; 321 u_int32_t reserved; 322 u_int32_t dbc; /* 0 based */ 323 #define AHCI_PRD_MASK 0x003fffff /* max 4MB */ 324 #define AHCI_PRD_MAX (AHCI_PRD_MASK + 1) 325 #define AHCI_PRD_IPC (1U << 31) 326 } __packed; 327 328 struct ahci_cmd_tab { 329 u_int8_t cfis[64]; 330 u_int8_t acmd[32]; 331 u_int8_t reserved[32]; 332 struct ahci_dma_prd prd_tab[AHCI_SG_ENTRIES]; 333 } __packed; 334 335 struct ahci_cmd_list { 336 u_int16_t cmd_flags; 337 #define AHCI_CMD_ATAPI 0x0020 338 #define AHCI_CMD_WRITE 0x0040 339 #define AHCI_CMD_PREFETCH 0x0080 340 #define AHCI_CMD_RESET 0x0100 341 #define AHCI_CMD_BIST 0x0200 342 #define AHCI_CMD_CLR_BUSY 0x0400 343 344 u_int16_t prd_length; /* PRD entries */ 345 u_int32_t bytecount; 346 u_int64_t cmd_table_phys; /* 128byte aligned */ 347 } __packed; 348 349 /* misc defines */ 350 #define ATA_IRQ_RID 0 351 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 352 353 struct ata_dmaslot { 354 bus_dmamap_t data_map; /* data DMA map */ 355 int nsegs; /* Number of segs loaded */ 356 }; 357 358 /* structure holding DMA related information */ 359 struct ata_dma { 360 bus_dma_tag_t work_tag; /* workspace DMA tag */ 361 bus_dmamap_t work_map; /* workspace DMA map */ 362 uint8_t *work; /* workspace */ 363 bus_addr_t work_bus; /* bus address of work */ 364 bus_dma_tag_t rfis_tag; /* RFIS list DMA tag */ 365 bus_dmamap_t rfis_map; /* RFIS list DMA map */ 366 uint8_t *rfis; /* FIS receive area */ 367 bus_addr_t rfis_bus; /* bus address of rfis */ 368 bus_dma_tag_t data_tag; /* data DMA tag */ 369 }; 370 371 enum ahci_slot_states { 372 AHCI_SLOT_EMPTY, 373 AHCI_SLOT_LOADING, 374 AHCI_SLOT_RUNNING, 375 AHCI_SLOT_EXECUTING 376 }; 377 378 struct ahci_slot { 379 struct ahci_channel *ch; /* Channel */ 380 u_int8_t slot; /* Number of this slot */ 381 enum ahci_slot_states state; /* Slot state */ 382 union ccb *ccb; /* CCB occupying slot */ 383 struct ata_dmaslot dma; /* DMA data of this slot */ 384 struct callout timeout; /* Execution timeout */ 385 }; 386 387 struct ahci_device { 388 int revision; 389 int mode; 390 u_int bytecount; 391 u_int atapi; 392 u_int tags; 393 u_int caps; 394 }; 395 396 struct ahci_led { 397 device_t dev; /* Device handle */ 398 struct cdev *led; 399 uint8_t num; /* Number of this led */ 400 uint8_t state; /* State of this led */ 401 }; 402 403 #define AHCI_NUM_LEDS 3 404 405 /* structure describing an ATA channel */ 406 struct ahci_channel { 407 device_t dev; /* Device handle */ 408 int unit; /* Physical channel */ 409 struct resource *r_mem; /* Memory of this channel */ 410 struct resource *r_irq; /* Interrupt of this channel */ 411 void *ih; /* Interrupt handle */ 412 struct ata_dma dma; /* DMA data */ 413 struct cam_sim *sim; 414 struct cam_path *path; 415 uint32_t caps; /* Controller capabilities */ 416 uint32_t caps2; /* Controller capabilities */ 417 uint32_t chcaps; /* Channel capabilities */ 418 uint32_t chscaps; /* Channel sleep capabilities */ 419 uint16_t vendorid; /* Vendor ID from the bus */ 420 uint16_t deviceid; /* Device ID from the bus */ 421 uint16_t subvendorid; /* Subvendor ID from the bus */ 422 uint16_t subdeviceid; /* Subdevice ID from the bus */ 423 int quirks; 424 int numslots; /* Number of present slots */ 425 int pm_level; /* power management level */ 426 int devices; /* What is present */ 427 int pm_present; /* PM presence reported */ 428 int fbs_enabled; /* FIS-based switching enabled */ 429 430 void (*start)(struct ahci_channel *); 431 432 union ccb *hold[AHCI_MAX_SLOTS]; 433 struct ahci_slot slot[AHCI_MAX_SLOTS]; 434 uint32_t oslots; /* Occupied slots */ 435 uint32_t rslots; /* Running slots */ 436 uint32_t aslots; /* Slots with atomic commands */ 437 uint32_t eslots; /* Slots in error */ 438 uint32_t toslots; /* Slots in timeout */ 439 int lastslot; /* Last used slot */ 440 int taggedtarget; /* Last tagged target */ 441 int numrslots; /* Number of running slots */ 442 int numrslotspd[16];/* Number of running slots per dev */ 443 int numtslots; /* Number of tagged slots */ 444 int numtslotspd[16];/* Number of tagged slots per dev */ 445 int numhslots; /* Number of held slots */ 446 int recoverycmd; /* Our READ LOG active */ 447 int fatalerr; /* Fatal error happened */ 448 int resetting; /* Hard-reset in progress. */ 449 int resetpolldiv; /* Hard-reset poll divider. */ 450 int listening; /* SUD bit is cleared. */ 451 int wrongccs; /* CCS field in CMD was wrong */ 452 union ccb *frozen; /* Frozen command */ 453 struct callout pm_timer; /* Power management events */ 454 struct callout reset_timer; /* Hard-reset timeout */ 455 456 struct ahci_device user[16]; /* User-specified settings */ 457 struct ahci_device curr[16]; /* Current settings */ 458 459 struct mtx_padalign mtx; /* state lock */ 460 STAILQ_HEAD(, ccb_hdr) doneq; /* queue of completed CCBs */ 461 int batch; /* doneq is in use */ 462 }; 463 464 struct ahci_enclosure { 465 device_t dev; /* Device handle */ 466 struct resource *r_memc; /* Control register */ 467 struct resource *r_memt; /* Transmit buffer */ 468 struct resource *r_memr; /* Receive buffer */ 469 struct cam_sim *sim; 470 struct cam_path *path; 471 struct mtx mtx; /* state lock */ 472 struct ahci_led leds[AHCI_MAX_PORTS * 3]; 473 uint32_t capsem; /* Controller capabilities */ 474 uint8_t status[AHCI_MAX_PORTS][4]; /* ArrayDev statuses */ 475 int quirks; 476 int channels; 477 uint32_t ichannels; 478 }; 479 480 /* structure describing a AHCI controller */ 481 struct ahci_controller { 482 device_t dev; 483 bus_dma_tag_t dma_tag; 484 int r_rid; 485 int r_msix_tab_rid; 486 int r_msix_pba_rid; 487 uint16_t vendorid; /* Vendor ID from the bus */ 488 uint16_t deviceid; /* Device ID from the bus */ 489 uint16_t subvendorid; /* Subvendor ID from the bus */ 490 uint16_t subdeviceid; /* Subdevice ID from the bus */ 491 struct resource *r_mem; 492 struct resource *r_msix_table; 493 struct resource *r_msix_pba; 494 struct rman sc_iomem; 495 struct ahci_controller_irq { 496 struct ahci_controller *ctlr; 497 struct resource *r_irq; 498 void *handle; 499 int r_irq_rid; 500 int mode; 501 #define AHCI_IRQ_MODE_ALL 0 502 #define AHCI_IRQ_MODE_AFTER 1 503 #define AHCI_IRQ_MODE_ONE 2 504 } irqs[AHCI_MAX_IRQS]; 505 uint32_t caps; /* Controller capabilities */ 506 uint32_t caps2; /* Controller capabilities */ 507 uint32_t capsem; /* Controller capabilities */ 508 uint32_t emloc; /* EM buffer location */ 509 int quirks; 510 int numirqs; 511 int channels; 512 uint32_t ichannels; 513 int ccc; /* CCC timeout */ 514 int cccv; /* CCC vector */ 515 int direct; /* Direct command completion */ 516 int msi; /* MSI interupts */ 517 struct { 518 void (*function)(void *); 519 void *argument; 520 } interrupt[AHCI_MAX_PORTS]; 521 void (*ch_start)(struct ahci_channel *); 522 int dma_coherent; /* DMA is cache-coherent */ 523 }; 524 525 enum ahci_err_type { 526 AHCI_ERR_NONE, /* No error */ 527 AHCI_ERR_INVALID, /* Error detected by us before submitting. */ 528 AHCI_ERR_INNOCENT, /* Innocent victim. */ 529 AHCI_ERR_TFE, /* Task File Error. */ 530 AHCI_ERR_SATA, /* SATA error. */ 531 AHCI_ERR_TIMEOUT, /* Command execution timeout. */ 532 AHCI_ERR_NCQ, /* NCQ command error. CCB should be put on hold 533 * until READ LOG executed to reveal error. */ 534 }; 535 536 /* macros to hide busspace uglyness */ 537 #define ATA_INB(res, offset) \ 538 bus_read_1((res), (offset)) 539 #define ATA_INW(res, offset) \ 540 bus_read_2((res), (offset)) 541 #define ATA_INL(res, offset) \ 542 bus_read_4((res), (offset)) 543 #define ATA_INSW(res, offset, addr, count) \ 544 bus_read_multi_2((res), (offset), (addr), (count)) 545 #define ATA_INSW_STRM(res, offset, addr, count) \ 546 bus_read_multi_stream_2((res), (offset), (addr), (count)) 547 #define ATA_INSL(res, offset, addr, count) \ 548 bus_read_multi_4((res), (offset), (addr), (count)) 549 #define ATA_INSL_STRM(res, offset, addr, count) \ 550 bus_read_multi_stream_4((res), (offset), (addr), (count)) 551 #define ATA_OUTB(res, offset, value) \ 552 bus_write_1((res), (offset), (value)) 553 #define ATA_OUTW(res, offset, value) \ 554 bus_write_2((res), (offset), (value)) 555 #define ATA_OUTL(res, offset, value) \ 556 bus_write_4((res), (offset), (value)) 557 #define ATA_OUTSW(res, offset, addr, count) \ 558 bus_write_multi_2((res), (offset), (addr), (count)) 559 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 560 bus_write_multi_stream_2((res), (offset), (addr), (count)) 561 #define ATA_OUTSL(res, offset, addr, count) \ 562 bus_write_multi_4((res), (offset), (addr), (count)) 563 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 564 bus_write_multi_stream_4((res), (offset), (addr), (count)) 565 566 /* 567 * On some platforms, we must ensure proper interdevice write ordering. 568 * The AHCI interrupt status register must be updated in HW before 569 * registers in interrupt controller. 570 * Unfortunately, only way how we can do it is readback. 571 * 572 * Currently, only ARM is known to have this issue. 573 */ 574 #if defined(__arm__) 575 #define ATA_RBL(res, offset) \ 576 bus_read_4((res), (offset)) 577 #else 578 #define ATA_RBL(res, offset) 579 #endif 580 581 #define AHCI_Q_NOFORCE 0x00000001 582 #define AHCI_Q_NOPMP 0x00000002 583 #define AHCI_Q_NONCQ 0x00000004 584 #define AHCI_Q_1CH 0x00000008 585 #define AHCI_Q_2CH 0x00000010 586 #define AHCI_Q_4CH 0x00000020 587 #define AHCI_Q_EDGEIS 0x00000040 588 #define AHCI_Q_SATA2 0x00000080 589 #define AHCI_Q_NOBSYRES 0x00000100 590 #define AHCI_Q_NOAA 0x00000200 591 #define AHCI_Q_NOCOUNT 0x00000400 592 #define AHCI_Q_ALTSIG 0x00000800 593 #define AHCI_Q_NOMSI 0x00001000 594 #define AHCI_Q_ATI_PMP_BUG 0x00002000 595 #define AHCI_Q_MAXIO_64K 0x00004000 596 #define AHCI_Q_SATA1_UNIT0 0x00008000 /* need better method for this */ 597 #define AHCI_Q_ABAR0 0x00010000 598 #define AHCI_Q_1MSI 0x00020000 599 #define AHCI_Q_FORCE_PI 0x00040000 600 #define AHCI_Q_RESTORE_CAP 0x00080000 601 #define AHCI_Q_NOMSIX 0x00100000 602 #define AHCI_Q_MRVL_SR_DEL 0x00200000 603 #define AHCI_Q_NOCCS 0x00400000 604 #define AHCI_Q_NOAUX 0x00800000 605 606 #define AHCI_Q_BIT_STRING \ 607 "\020" \ 608 "\001NOFORCE" \ 609 "\002NOPMP" \ 610 "\003NONCQ" \ 611 "\0041CH" \ 612 "\0052CH" \ 613 "\0064CH" \ 614 "\007EDGEIS" \ 615 "\010SATA2" \ 616 "\011NOBSYRES" \ 617 "\012NOAA" \ 618 "\013NOCOUNT" \ 619 "\014ALTSIG" \ 620 "\015NOMSI" \ 621 "\016ATI_PMP_BUG" \ 622 "\017MAXIO_64K" \ 623 "\020SATA1_UNIT0" \ 624 "\021ABAR0" \ 625 "\0221MSI" \ 626 "\023FORCE_PI" \ 627 "\024RESTORE_CAP" \ 628 "\025NOMSIX" \ 629 "\026MRVL_SR_DEL" \ 630 "\027NOCCS" \ 631 "\030NOAUX" 632 633 int ahci_attach(device_t dev); 634 int ahci_detach(device_t dev); 635 int ahci_setup_interrupt(device_t dev); 636 int ahci_print_child(device_t dev, device_t child); 637 struct resource *ahci_alloc_resource(device_t dev, device_t child, int type, int *rid, 638 rman_res_t start, rman_res_t end, rman_res_t count, u_int flags); 639 int ahci_release_resource(device_t dev, device_t child, int type, int rid, 640 struct resource *r); 641 int ahci_setup_intr(device_t dev, device_t child, struct resource *irq, 642 int flags, driver_filter_t *filter, driver_intr_t *function, 643 void *argument, void **cookiep); 644 int ahci_teardown_intr(device_t dev, device_t child, struct resource *irq, 645 void *cookie); 646 int ahci_child_location_str(device_t dev, device_t child, char *buf, 647 size_t buflen); 648 bus_dma_tag_t ahci_get_dma_tag(device_t dev, device_t child); 649 int ahci_ctlr_reset(device_t dev); 650 int ahci_ctlr_setup(device_t dev); 651 void ahci_free_mem(device_t dev); 652