1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR813x/AR815x PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/lock.h> 41 #include <sys/malloc.h> 42 #include <sys/mbuf.h> 43 #include <sys/module.h> 44 #include <sys/mutex.h> 45 #include <sys/rman.h> 46 #include <sys/queue.h> 47 #include <sys/socket.h> 48 #include <sys/sockio.h> 49 #include <sys/sysctl.h> 50 #include <sys/taskqueue.h> 51 52 #include <net/bpf.h> 53 #include <net/if.h> 54 #include <net/if_var.h> 55 #include <net/if_arp.h> 56 #include <net/ethernet.h> 57 #include <net/if_dl.h> 58 #include <net/if_llc.h> 59 #include <net/if_media.h> 60 #include <net/if_types.h> 61 #include <net/if_vlan_var.h> 62 63 #include <netinet/in.h> 64 #include <netinet/in_systm.h> 65 #include <netinet/ip.h> 66 #include <netinet/tcp.h> 67 #include <netinet/netdump/netdump.h> 68 69 #include <dev/mii/mii.h> 70 #include <dev/mii/miivar.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <machine/bus.h> 76 #include <machine/in_cksum.h> 77 78 #include <dev/alc/if_alcreg.h> 79 #include <dev/alc/if_alcvar.h> 80 81 /* "device miibus" required. See GENERIC if you get errors here. */ 82 #include "miibus_if.h" 83 #undef ALC_USE_CUSTOM_CSUM 84 85 #ifdef ALC_USE_CUSTOM_CSUM 86 #define ALC_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 87 #else 88 #define ALC_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 89 #endif 90 91 MODULE_DEPEND(alc, pci, 1, 1, 1); 92 MODULE_DEPEND(alc, ether, 1, 1, 1); 93 MODULE_DEPEND(alc, miibus, 1, 1, 1); 94 95 /* Tunables. */ 96 static int msi_disable = 0; 97 static int msix_disable = 0; 98 TUNABLE_INT("hw.alc.msi_disable", &msi_disable); 99 TUNABLE_INT("hw.alc.msix_disable", &msix_disable); 100 101 /* 102 * Devices supported by this driver. 103 */ 104 static struct alc_ident alc_ident_table[] = { 105 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8131, 9 * 1024, 106 "Atheros AR8131 PCIe Gigabit Ethernet" }, 107 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8132, 9 * 1024, 108 "Atheros AR8132 PCIe Fast Ethernet" }, 109 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151, 6 * 1024, 110 "Atheros AR8151 v1.0 PCIe Gigabit Ethernet" }, 111 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8151_V2, 6 * 1024, 112 "Atheros AR8151 v2.0 PCIe Gigabit Ethernet" }, 113 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B, 6 * 1024, 114 "Atheros AR8152 v1.1 PCIe Fast Ethernet" }, 115 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8152_B2, 6 * 1024, 116 "Atheros AR8152 v2.0 PCIe Fast Ethernet" }, 117 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8161, 9 * 1024, 118 "Atheros AR8161 PCIe Gigabit Ethernet" }, 119 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8162, 9 * 1024, 120 "Atheros AR8162 PCIe Fast Ethernet" }, 121 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8171, 9 * 1024, 122 "Atheros AR8171 PCIe Gigabit Ethernet" }, 123 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR8172, 9 * 1024, 124 "Atheros AR8172 PCIe Fast Ethernet" }, 125 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2200, 9 * 1024, 126 "Killer E2200 Gigabit Ethernet" }, 127 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2400, 9 * 1024, 128 "Killer E2400 Gigabit Ethernet" }, 129 { VENDORID_ATHEROS, DEVICEID_ATHEROS_E2500, 9 * 1024, 130 "Killer E2500 Gigabit Ethernet" }, 131 { 0, 0, 0, NULL} 132 }; 133 134 static void alc_aspm(struct alc_softc *, int, int); 135 static void alc_aspm_813x(struct alc_softc *, int); 136 static void alc_aspm_816x(struct alc_softc *, int); 137 static int alc_attach(device_t); 138 static int alc_check_boundary(struct alc_softc *); 139 static void alc_config_msi(struct alc_softc *); 140 static int alc_detach(device_t); 141 static void alc_disable_l0s_l1(struct alc_softc *); 142 static int alc_dma_alloc(struct alc_softc *); 143 static void alc_dma_free(struct alc_softc *); 144 static void alc_dmamap_cb(void *, bus_dma_segment_t *, int, int); 145 static void alc_dsp_fixup(struct alc_softc *, int); 146 static int alc_encap(struct alc_softc *, struct mbuf **); 147 static struct alc_ident * 148 alc_find_ident(device_t); 149 #ifndef __NO_STRICT_ALIGNMENT 150 static struct mbuf * 151 alc_fixup_rx(struct ifnet *, struct mbuf *); 152 #endif 153 static void alc_get_macaddr(struct alc_softc *); 154 static void alc_get_macaddr_813x(struct alc_softc *); 155 static void alc_get_macaddr_816x(struct alc_softc *); 156 static void alc_get_macaddr_par(struct alc_softc *); 157 static void alc_init(void *); 158 static void alc_init_cmb(struct alc_softc *); 159 static void alc_init_locked(struct alc_softc *); 160 static void alc_init_rr_ring(struct alc_softc *); 161 static int alc_init_rx_ring(struct alc_softc *); 162 static void alc_init_smb(struct alc_softc *); 163 static void alc_init_tx_ring(struct alc_softc *); 164 static void alc_int_task(void *, int); 165 static int alc_intr(void *); 166 static int alc_ioctl(struct ifnet *, u_long, caddr_t); 167 static void alc_mac_config(struct alc_softc *); 168 static uint32_t alc_mii_readreg_813x(struct alc_softc *, int, int); 169 static uint32_t alc_mii_readreg_816x(struct alc_softc *, int, int); 170 static uint32_t alc_mii_writereg_813x(struct alc_softc *, int, int, int); 171 static uint32_t alc_mii_writereg_816x(struct alc_softc *, int, int, int); 172 static int alc_miibus_readreg(device_t, int, int); 173 static void alc_miibus_statchg(device_t); 174 static int alc_miibus_writereg(device_t, int, int, int); 175 static uint32_t alc_miidbg_readreg(struct alc_softc *, int); 176 static uint32_t alc_miidbg_writereg(struct alc_softc *, int, int); 177 static uint32_t alc_miiext_readreg(struct alc_softc *, int, int); 178 static uint32_t alc_miiext_writereg(struct alc_softc *, int, int, int); 179 static int alc_mediachange(struct ifnet *); 180 static int alc_mediachange_locked(struct alc_softc *); 181 static void alc_mediastatus(struct ifnet *, struct ifmediareq *); 182 static int alc_newbuf(struct alc_softc *, struct alc_rxdesc *); 183 static void alc_osc_reset(struct alc_softc *); 184 static void alc_phy_down(struct alc_softc *); 185 static void alc_phy_reset(struct alc_softc *); 186 static void alc_phy_reset_813x(struct alc_softc *); 187 static void alc_phy_reset_816x(struct alc_softc *); 188 static int alc_probe(device_t); 189 static void alc_reset(struct alc_softc *); 190 static int alc_resume(device_t); 191 static void alc_rxeof(struct alc_softc *, struct rx_rdesc *); 192 static int alc_rxintr(struct alc_softc *, int); 193 static void alc_rxfilter(struct alc_softc *); 194 static void alc_rxvlan(struct alc_softc *); 195 static void alc_setlinkspeed(struct alc_softc *); 196 static void alc_setwol(struct alc_softc *); 197 static void alc_setwol_813x(struct alc_softc *); 198 static void alc_setwol_816x(struct alc_softc *); 199 static int alc_shutdown(device_t); 200 static void alc_start(struct ifnet *); 201 static void alc_start_locked(struct ifnet *); 202 static void alc_start_queue(struct alc_softc *); 203 static void alc_start_tx(struct alc_softc *); 204 static void alc_stats_clear(struct alc_softc *); 205 static void alc_stats_update(struct alc_softc *); 206 static void alc_stop(struct alc_softc *); 207 static void alc_stop_mac(struct alc_softc *); 208 static void alc_stop_queue(struct alc_softc *); 209 static int alc_suspend(device_t); 210 static void alc_sysctl_node(struct alc_softc *); 211 static void alc_tick(void *); 212 static void alc_txeof(struct alc_softc *); 213 static void alc_watchdog(struct alc_softc *); 214 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 215 static int sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS); 216 static int sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS); 217 218 NETDUMP_DEFINE(alc); 219 220 static device_method_t alc_methods[] = { 221 /* Device interface. */ 222 DEVMETHOD(device_probe, alc_probe), 223 DEVMETHOD(device_attach, alc_attach), 224 DEVMETHOD(device_detach, alc_detach), 225 DEVMETHOD(device_shutdown, alc_shutdown), 226 DEVMETHOD(device_suspend, alc_suspend), 227 DEVMETHOD(device_resume, alc_resume), 228 229 /* MII interface. */ 230 DEVMETHOD(miibus_readreg, alc_miibus_readreg), 231 DEVMETHOD(miibus_writereg, alc_miibus_writereg), 232 DEVMETHOD(miibus_statchg, alc_miibus_statchg), 233 234 DEVMETHOD_END 235 }; 236 237 static driver_t alc_driver = { 238 "alc", 239 alc_methods, 240 sizeof(struct alc_softc) 241 }; 242 243 static devclass_t alc_devclass; 244 245 DRIVER_MODULE(alc, pci, alc_driver, alc_devclass, 0, 0); 246 DRIVER_MODULE(miibus, alc, miibus_driver, miibus_devclass, 0, 0); 247 248 static struct resource_spec alc_res_spec_mem[] = { 249 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 250 { -1, 0, 0 } 251 }; 252 253 static struct resource_spec alc_irq_spec_legacy[] = { 254 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 255 { -1, 0, 0 } 256 }; 257 258 static struct resource_spec alc_irq_spec_msi[] = { 259 { SYS_RES_IRQ, 1, RF_ACTIVE }, 260 { -1, 0, 0 } 261 }; 262 263 static struct resource_spec alc_irq_spec_msix[] = { 264 { SYS_RES_IRQ, 1, RF_ACTIVE }, 265 { -1, 0, 0 } 266 }; 267 268 static uint32_t alc_dma_burst[] = { 128, 256, 512, 1024, 2048, 4096, 0, 0 }; 269 270 static int 271 alc_miibus_readreg(device_t dev, int phy, int reg) 272 { 273 struct alc_softc *sc; 274 int v; 275 276 sc = device_get_softc(dev); 277 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 278 v = alc_mii_readreg_816x(sc, phy, reg); 279 else 280 v = alc_mii_readreg_813x(sc, phy, reg); 281 return (v); 282 } 283 284 static uint32_t 285 alc_mii_readreg_813x(struct alc_softc *sc, int phy, int reg) 286 { 287 uint32_t v; 288 int i; 289 290 /* 291 * For AR8132 fast ethernet controller, do not report 1000baseT 292 * capability to mii(4). Even though AR8132 uses the same 293 * model/revision number of F1 gigabit PHY, the PHY has no 294 * ability to establish 1000baseT link. 295 */ 296 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0 && 297 reg == MII_EXTSR) 298 return (0); 299 300 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 301 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 302 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 303 DELAY(5); 304 v = CSR_READ_4(sc, ALC_MDIO); 305 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 306 break; 307 } 308 309 if (i == 0) { 310 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 311 return (0); 312 } 313 314 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 315 } 316 317 static uint32_t 318 alc_mii_readreg_816x(struct alc_softc *sc, int phy, int reg) 319 { 320 uint32_t clk, v; 321 int i; 322 323 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 324 clk = MDIO_CLK_25_128; 325 else 326 clk = MDIO_CLK_25_4; 327 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 328 MDIO_SUP_PREAMBLE | clk | MDIO_REG_ADDR(reg)); 329 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 330 DELAY(5); 331 v = CSR_READ_4(sc, ALC_MDIO); 332 if ((v & MDIO_OP_BUSY) == 0) 333 break; 334 } 335 336 if (i == 0) { 337 device_printf(sc->alc_dev, "phy read timeout : %d\n", reg); 338 return (0); 339 } 340 341 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 342 } 343 344 static int 345 alc_miibus_writereg(device_t dev, int phy, int reg, int val) 346 { 347 struct alc_softc *sc; 348 int v; 349 350 sc = device_get_softc(dev); 351 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 352 v = alc_mii_writereg_816x(sc, phy, reg, val); 353 else 354 v = alc_mii_writereg_813x(sc, phy, reg, val); 355 return (v); 356 } 357 358 static uint32_t 359 alc_mii_writereg_813x(struct alc_softc *sc, int phy, int reg, int val) 360 { 361 uint32_t v; 362 int i; 363 364 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 365 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 366 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 367 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 368 DELAY(5); 369 v = CSR_READ_4(sc, ALC_MDIO); 370 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 371 break; 372 } 373 374 if (i == 0) 375 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 376 377 return (0); 378 } 379 380 static uint32_t 381 alc_mii_writereg_816x(struct alc_softc *sc, int phy, int reg, int val) 382 { 383 uint32_t clk, v; 384 int i; 385 386 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 387 clk = MDIO_CLK_25_128; 388 else 389 clk = MDIO_CLK_25_4; 390 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 391 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | MDIO_REG_ADDR(reg) | 392 MDIO_SUP_PREAMBLE | clk); 393 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 394 DELAY(5); 395 v = CSR_READ_4(sc, ALC_MDIO); 396 if ((v & MDIO_OP_BUSY) == 0) 397 break; 398 } 399 400 if (i == 0) 401 device_printf(sc->alc_dev, "phy write timeout : %d\n", reg); 402 403 return (0); 404 } 405 406 static void 407 alc_miibus_statchg(device_t dev) 408 { 409 struct alc_softc *sc; 410 struct mii_data *mii; 411 struct ifnet *ifp; 412 uint32_t reg; 413 414 sc = device_get_softc(dev); 415 416 mii = device_get_softc(sc->alc_miibus); 417 ifp = sc->alc_ifp; 418 if (mii == NULL || ifp == NULL || 419 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 420 return; 421 422 sc->alc_flags &= ~ALC_FLAG_LINK; 423 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 424 (IFM_ACTIVE | IFM_AVALID)) { 425 switch (IFM_SUBTYPE(mii->mii_media_active)) { 426 case IFM_10_T: 427 case IFM_100_TX: 428 sc->alc_flags |= ALC_FLAG_LINK; 429 break; 430 case IFM_1000_T: 431 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 432 sc->alc_flags |= ALC_FLAG_LINK; 433 break; 434 default: 435 break; 436 } 437 } 438 /* Stop Rx/Tx MACs. */ 439 alc_stop_mac(sc); 440 441 /* Program MACs with resolved speed/duplex/flow-control. */ 442 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 443 alc_start_queue(sc); 444 alc_mac_config(sc); 445 /* Re-enable Tx/Rx MACs. */ 446 reg = CSR_READ_4(sc, ALC_MAC_CFG); 447 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 448 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 449 } 450 alc_aspm(sc, 0, IFM_SUBTYPE(mii->mii_media_active)); 451 alc_dsp_fixup(sc, IFM_SUBTYPE(mii->mii_media_active)); 452 } 453 454 static uint32_t 455 alc_miidbg_readreg(struct alc_softc *sc, int reg) 456 { 457 458 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 459 reg); 460 return (alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 461 ALC_MII_DBG_DATA)); 462 } 463 464 static uint32_t 465 alc_miidbg_writereg(struct alc_softc *sc, int reg, int val) 466 { 467 468 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 469 reg); 470 return (alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 471 ALC_MII_DBG_DATA, val)); 472 } 473 474 static uint32_t 475 alc_miiext_readreg(struct alc_softc *sc, int devaddr, int reg) 476 { 477 uint32_t clk, v; 478 int i; 479 480 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 481 EXT_MDIO_DEVADDR(devaddr)); 482 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 483 clk = MDIO_CLK_25_128; 484 else 485 clk = MDIO_CLK_25_4; 486 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 487 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 488 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 489 DELAY(5); 490 v = CSR_READ_4(sc, ALC_MDIO); 491 if ((v & MDIO_OP_BUSY) == 0) 492 break; 493 } 494 495 if (i == 0) { 496 device_printf(sc->alc_dev, "phy ext read timeout : %d, %d\n", 497 devaddr, reg); 498 return (0); 499 } 500 501 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 502 } 503 504 static uint32_t 505 alc_miiext_writereg(struct alc_softc *sc, int devaddr, int reg, int val) 506 { 507 uint32_t clk, v; 508 int i; 509 510 CSR_WRITE_4(sc, ALC_EXT_MDIO, EXT_MDIO_REG(reg) | 511 EXT_MDIO_DEVADDR(devaddr)); 512 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) 513 clk = MDIO_CLK_25_128; 514 else 515 clk = MDIO_CLK_25_4; 516 CSR_WRITE_4(sc, ALC_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 517 ((val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT) | 518 MDIO_SUP_PREAMBLE | clk | MDIO_MODE_EXT); 519 for (i = ALC_PHY_TIMEOUT; i > 0; i--) { 520 DELAY(5); 521 v = CSR_READ_4(sc, ALC_MDIO); 522 if ((v & MDIO_OP_BUSY) == 0) 523 break; 524 } 525 526 if (i == 0) 527 device_printf(sc->alc_dev, "phy ext write timeout : %d, %d\n", 528 devaddr, reg); 529 530 return (0); 531 } 532 533 static void 534 alc_dsp_fixup(struct alc_softc *sc, int media) 535 { 536 uint16_t agc, len, val; 537 538 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 539 return; 540 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_C0) 541 return; 542 543 /* 544 * Vendor PHY magic. 545 * 1000BT/AZ, wrong cable length 546 */ 547 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 548 len = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL6); 549 len = (len >> EXT_CLDCTL6_CAB_LEN_SHIFT) & 550 EXT_CLDCTL6_CAB_LEN_MASK; 551 agc = alc_miidbg_readreg(sc, MII_DBG_AGC); 552 agc = (agc >> DBG_AGC_2_VGA_SHIFT) & DBG_AGC_2_VGA_MASK; 553 if ((media == IFM_1000_T && len > EXT_CLDCTL6_CAB_LEN_SHORT1G && 554 agc > DBG_AGC_LONG1G_LIMT) || 555 (media == IFM_100_TX && len > DBG_AGC_LONG100M_LIMT && 556 agc > DBG_AGC_LONG1G_LIMT)) { 557 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 558 DBG_AZ_ANADECT_LONG); 559 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 560 MII_EXT_ANEG_AFE); 561 val |= ANEG_AFEE_10BT_100M_TH; 562 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 563 val); 564 } else { 565 alc_miidbg_writereg(sc, MII_DBG_AZ_ANADECT, 566 DBG_AZ_ANADECT_DEFAULT); 567 val = alc_miiext_readreg(sc, MII_EXT_ANEG, 568 MII_EXT_ANEG_AFE); 569 val &= ~ANEG_AFEE_10BT_100M_TH; 570 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, 571 val); 572 } 573 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 574 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 575 if (media == IFM_1000_T) { 576 /* 577 * Giga link threshold, raise the tolerance of 578 * noise 50%. 579 */ 580 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 581 val &= ~DBG_MSE20DB_TH_MASK; 582 val |= (DBG_MSE20DB_TH_HI << 583 DBG_MSE20DB_TH_SHIFT); 584 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 585 } else if (media == IFM_100_TX) 586 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 587 DBG_MSE16DB_UP); 588 } 589 } else { 590 val = alc_miiext_readreg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE); 591 val &= ~ANEG_AFEE_10BT_100M_TH; 592 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_AFE, val); 593 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0 && 594 AR816X_REV(sc->alc_rev) == AR816X_REV_B0) { 595 alc_miidbg_writereg(sc, MII_DBG_MSE16DB, 596 DBG_MSE16DB_DOWN); 597 val = alc_miidbg_readreg(sc, MII_DBG_MSE20DB); 598 val &= ~DBG_MSE20DB_TH_MASK; 599 val |= (DBG_MSE20DB_TH_DEFAULT << DBG_MSE20DB_TH_SHIFT); 600 alc_miidbg_writereg(sc, MII_DBG_MSE20DB, val); 601 } 602 } 603 } 604 605 static void 606 alc_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 607 { 608 struct alc_softc *sc; 609 struct mii_data *mii; 610 611 sc = ifp->if_softc; 612 ALC_LOCK(sc); 613 if ((ifp->if_flags & IFF_UP) == 0) { 614 ALC_UNLOCK(sc); 615 return; 616 } 617 mii = device_get_softc(sc->alc_miibus); 618 619 mii_pollstat(mii); 620 ifmr->ifm_status = mii->mii_media_status; 621 ifmr->ifm_active = mii->mii_media_active; 622 ALC_UNLOCK(sc); 623 } 624 625 static int 626 alc_mediachange(struct ifnet *ifp) 627 { 628 struct alc_softc *sc; 629 int error; 630 631 sc = ifp->if_softc; 632 ALC_LOCK(sc); 633 error = alc_mediachange_locked(sc); 634 ALC_UNLOCK(sc); 635 636 return (error); 637 } 638 639 static int 640 alc_mediachange_locked(struct alc_softc *sc) 641 { 642 struct mii_data *mii; 643 struct mii_softc *miisc; 644 int error; 645 646 ALC_LOCK_ASSERT(sc); 647 648 mii = device_get_softc(sc->alc_miibus); 649 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 650 PHY_RESET(miisc); 651 error = mii_mediachg(mii); 652 653 return (error); 654 } 655 656 static struct alc_ident * 657 alc_find_ident(device_t dev) 658 { 659 struct alc_ident *ident; 660 uint16_t vendor, devid; 661 662 vendor = pci_get_vendor(dev); 663 devid = pci_get_device(dev); 664 for (ident = alc_ident_table; ident->name != NULL; ident++) { 665 if (vendor == ident->vendorid && devid == ident->deviceid) 666 return (ident); 667 } 668 669 return (NULL); 670 } 671 672 static int 673 alc_probe(device_t dev) 674 { 675 struct alc_ident *ident; 676 677 ident = alc_find_ident(dev); 678 if (ident != NULL) { 679 device_set_desc(dev, ident->name); 680 return (BUS_PROBE_DEFAULT); 681 } 682 683 return (ENXIO); 684 } 685 686 static void 687 alc_get_macaddr(struct alc_softc *sc) 688 { 689 690 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 691 alc_get_macaddr_816x(sc); 692 else 693 alc_get_macaddr_813x(sc); 694 } 695 696 static void 697 alc_get_macaddr_813x(struct alc_softc *sc) 698 { 699 uint32_t opt; 700 uint16_t val; 701 int eeprom, i; 702 703 eeprom = 0; 704 opt = CSR_READ_4(sc, ALC_OPT_CFG); 705 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_OTP_SEL) != 0 && 706 (CSR_READ_4(sc, ALC_TWSI_DEBUG) & TWSI_DEBUG_DEV_EXIST) != 0) { 707 /* 708 * EEPROM found, let TWSI reload EEPROM configuration. 709 * This will set ethernet address of controller. 710 */ 711 eeprom++; 712 switch (sc->alc_ident->deviceid) { 713 case DEVICEID_ATHEROS_AR8131: 714 case DEVICEID_ATHEROS_AR8132: 715 if ((opt & OPT_CFG_CLK_ENB) == 0) { 716 opt |= OPT_CFG_CLK_ENB; 717 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 718 CSR_READ_4(sc, ALC_OPT_CFG); 719 DELAY(1000); 720 } 721 break; 722 case DEVICEID_ATHEROS_AR8151: 723 case DEVICEID_ATHEROS_AR8151_V2: 724 case DEVICEID_ATHEROS_AR8152_B: 725 case DEVICEID_ATHEROS_AR8152_B2: 726 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 727 ALC_MII_DBG_ADDR, 0x00); 728 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 729 ALC_MII_DBG_DATA); 730 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 731 ALC_MII_DBG_DATA, val & 0xFF7F); 732 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 733 ALC_MII_DBG_ADDR, 0x3B); 734 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 735 ALC_MII_DBG_DATA); 736 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 737 ALC_MII_DBG_DATA, val | 0x0008); 738 DELAY(20); 739 break; 740 } 741 742 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 743 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 744 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 745 CSR_READ_4(sc, ALC_WOL_CFG); 746 747 CSR_WRITE_4(sc, ALC_TWSI_CFG, CSR_READ_4(sc, ALC_TWSI_CFG) | 748 TWSI_CFG_SW_LD_START); 749 for (i = 100; i > 0; i--) { 750 DELAY(1000); 751 if ((CSR_READ_4(sc, ALC_TWSI_CFG) & 752 TWSI_CFG_SW_LD_START) == 0) 753 break; 754 } 755 if (i == 0) 756 device_printf(sc->alc_dev, 757 "reloading EEPROM timeout!\n"); 758 } else { 759 if (bootverbose) 760 device_printf(sc->alc_dev, "EEPROM not found!\n"); 761 } 762 if (eeprom != 0) { 763 switch (sc->alc_ident->deviceid) { 764 case DEVICEID_ATHEROS_AR8131: 765 case DEVICEID_ATHEROS_AR8132: 766 if ((opt & OPT_CFG_CLK_ENB) != 0) { 767 opt &= ~OPT_CFG_CLK_ENB; 768 CSR_WRITE_4(sc, ALC_OPT_CFG, opt); 769 CSR_READ_4(sc, ALC_OPT_CFG); 770 DELAY(1000); 771 } 772 break; 773 case DEVICEID_ATHEROS_AR8151: 774 case DEVICEID_ATHEROS_AR8151_V2: 775 case DEVICEID_ATHEROS_AR8152_B: 776 case DEVICEID_ATHEROS_AR8152_B2: 777 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 778 ALC_MII_DBG_ADDR, 0x00); 779 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 780 ALC_MII_DBG_DATA); 781 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 782 ALC_MII_DBG_DATA, val | 0x0080); 783 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 784 ALC_MII_DBG_ADDR, 0x3B); 785 val = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 786 ALC_MII_DBG_DATA); 787 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 788 ALC_MII_DBG_DATA, val & 0xFFF7); 789 DELAY(20); 790 break; 791 } 792 } 793 794 alc_get_macaddr_par(sc); 795 } 796 797 static void 798 alc_get_macaddr_816x(struct alc_softc *sc) 799 { 800 uint32_t reg; 801 int i, reloaded; 802 803 reloaded = 0; 804 /* Try to reload station address via TWSI. */ 805 for (i = 100; i > 0; i--) { 806 reg = CSR_READ_4(sc, ALC_SLD); 807 if ((reg & (SLD_PROGRESS | SLD_START)) == 0) 808 break; 809 DELAY(1000); 810 } 811 if (i != 0) { 812 CSR_WRITE_4(sc, ALC_SLD, reg | SLD_START); 813 for (i = 100; i > 0; i--) { 814 DELAY(1000); 815 reg = CSR_READ_4(sc, ALC_SLD); 816 if ((reg & SLD_START) == 0) 817 break; 818 } 819 if (i != 0) 820 reloaded++; 821 else if (bootverbose) 822 device_printf(sc->alc_dev, 823 "reloading station address via TWSI timed out!\n"); 824 } 825 826 /* Try to reload station address from EEPROM or FLASH. */ 827 if (reloaded == 0) { 828 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 829 if ((reg & (EEPROM_LD_EEPROM_EXIST | 830 EEPROM_LD_FLASH_EXIST)) != 0) { 831 for (i = 100; i > 0; i--) { 832 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 833 if ((reg & (EEPROM_LD_PROGRESS | 834 EEPROM_LD_START)) == 0) 835 break; 836 DELAY(1000); 837 } 838 if (i != 0) { 839 CSR_WRITE_4(sc, ALC_EEPROM_LD, reg | 840 EEPROM_LD_START); 841 for (i = 100; i > 0; i--) { 842 DELAY(1000); 843 reg = CSR_READ_4(sc, ALC_EEPROM_LD); 844 if ((reg & EEPROM_LD_START) == 0) 845 break; 846 } 847 } else if (bootverbose) 848 device_printf(sc->alc_dev, 849 "reloading EEPROM/FLASH timed out!\n"); 850 } 851 } 852 853 alc_get_macaddr_par(sc); 854 } 855 856 static void 857 alc_get_macaddr_par(struct alc_softc *sc) 858 { 859 uint32_t ea[2]; 860 861 ea[0] = CSR_READ_4(sc, ALC_PAR0); 862 ea[1] = CSR_READ_4(sc, ALC_PAR1); 863 sc->alc_eaddr[0] = (ea[1] >> 8) & 0xFF; 864 sc->alc_eaddr[1] = (ea[1] >> 0) & 0xFF; 865 sc->alc_eaddr[2] = (ea[0] >> 24) & 0xFF; 866 sc->alc_eaddr[3] = (ea[0] >> 16) & 0xFF; 867 sc->alc_eaddr[4] = (ea[0] >> 8) & 0xFF; 868 sc->alc_eaddr[5] = (ea[0] >> 0) & 0xFF; 869 } 870 871 static void 872 alc_disable_l0s_l1(struct alc_softc *sc) 873 { 874 uint32_t pmcfg; 875 876 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 877 /* Another magic from vendor. */ 878 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 879 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_CLK_SWH_L1 | 880 PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 881 PM_CFG_MAC_ASPM_CHK | PM_CFG_SERDES_PD_EX_L1); 882 pmcfg |= PM_CFG_SERDES_BUDS_RX_L1_ENB | 883 PM_CFG_SERDES_PLL_L1_ENB | PM_CFG_SERDES_L1_ENB; 884 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 885 } 886 } 887 888 static void 889 alc_phy_reset(struct alc_softc *sc) 890 { 891 892 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 893 alc_phy_reset_816x(sc); 894 else 895 alc_phy_reset_813x(sc); 896 } 897 898 static void 899 alc_phy_reset_813x(struct alc_softc *sc) 900 { 901 uint16_t data; 902 903 /* Reset magic from Linux. */ 904 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_SEL_ANA_RESET); 905 CSR_READ_2(sc, ALC_GPHY_CFG); 906 DELAY(10 * 1000); 907 908 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 909 GPHY_CFG_SEL_ANA_RESET); 910 CSR_READ_2(sc, ALC_GPHY_CFG); 911 DELAY(10 * 1000); 912 913 /* DSP fixup, Vendor magic. */ 914 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 915 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 916 ALC_MII_DBG_ADDR, 0x000A); 917 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 918 ALC_MII_DBG_DATA); 919 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 920 ALC_MII_DBG_DATA, data & 0xDFFF); 921 } 922 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 923 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 924 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 925 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 926 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 927 ALC_MII_DBG_ADDR, 0x003B); 928 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 929 ALC_MII_DBG_DATA); 930 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 931 ALC_MII_DBG_DATA, data & 0xFFF7); 932 DELAY(20 * 1000); 933 } 934 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151) { 935 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 936 ALC_MII_DBG_ADDR, 0x0029); 937 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 938 ALC_MII_DBG_DATA, 0x929D); 939 } 940 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 941 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132 || 942 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 943 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) { 944 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 945 ALC_MII_DBG_ADDR, 0x0029); 946 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 947 ALC_MII_DBG_DATA, 0xB6DD); 948 } 949 950 /* Load DSP codes, vendor magic. */ 951 data = ANA_LOOP_SEL_10BT | ANA_EN_MASK_TB | ANA_EN_10BT_IDLE | 952 ((1 << ANA_INTERVAL_SEL_TIMER_SHIFT) & ANA_INTERVAL_SEL_TIMER_MASK); 953 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 954 ALC_MII_DBG_ADDR, MII_ANA_CFG18); 955 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 956 ALC_MII_DBG_DATA, data); 957 958 data = ((2 << ANA_SERDES_CDR_BW_SHIFT) & ANA_SERDES_CDR_BW_MASK) | 959 ANA_SERDES_EN_DEEM | ANA_SERDES_SEL_HSP | ANA_SERDES_EN_PLL | 960 ANA_SERDES_EN_LCKDT; 961 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 962 ALC_MII_DBG_ADDR, MII_ANA_CFG5); 963 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 964 ALC_MII_DBG_DATA, data); 965 966 data = ((44 << ANA_LONG_CABLE_TH_100_SHIFT) & 967 ANA_LONG_CABLE_TH_100_MASK) | 968 ((33 << ANA_SHORT_CABLE_TH_100_SHIFT) & 969 ANA_SHORT_CABLE_TH_100_SHIFT) | 970 ANA_BP_BAD_LINK_ACCUM | ANA_BP_SMALL_BW; 971 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 972 ALC_MII_DBG_ADDR, MII_ANA_CFG54); 973 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 974 ALC_MII_DBG_DATA, data); 975 976 data = ((11 << ANA_IECHO_ADJ_3_SHIFT) & ANA_IECHO_ADJ_3_MASK) | 977 ((11 << ANA_IECHO_ADJ_2_SHIFT) & ANA_IECHO_ADJ_2_MASK) | 978 ((8 << ANA_IECHO_ADJ_1_SHIFT) & ANA_IECHO_ADJ_1_MASK) | 979 ((8 << ANA_IECHO_ADJ_0_SHIFT) & ANA_IECHO_ADJ_0_MASK); 980 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 981 ALC_MII_DBG_ADDR, MII_ANA_CFG4); 982 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 983 ALC_MII_DBG_DATA, data); 984 985 data = ((7 & ANA_MANUL_SWICH_ON_SHIFT) & ANA_MANUL_SWICH_ON_MASK) | 986 ANA_RESTART_CAL | ANA_MAN_ENABLE | ANA_SEL_HSP | ANA_EN_HB | 987 ANA_OEN_125M; 988 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 989 ALC_MII_DBG_ADDR, MII_ANA_CFG0); 990 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 991 ALC_MII_DBG_DATA, data); 992 DELAY(1000); 993 994 /* Disable hibernation. */ 995 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 996 0x0029); 997 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 998 ALC_MII_DBG_DATA); 999 data &= ~0x8000; 1000 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1001 data); 1002 1003 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_ADDR, 1004 0x000B); 1005 data = alc_miibus_readreg(sc->alc_dev, sc->alc_phyaddr, 1006 ALC_MII_DBG_DATA); 1007 data &= ~0x8000; 1008 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, ALC_MII_DBG_DATA, 1009 data); 1010 } 1011 1012 static void 1013 alc_phy_reset_816x(struct alc_softc *sc) 1014 { 1015 uint32_t val; 1016 1017 val = CSR_READ_4(sc, ALC_GPHY_CFG); 1018 val &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1019 GPHY_CFG_GATE_25M_ENB | GPHY_CFG_PHY_IDDQ | GPHY_CFG_PHY_PLL_ON | 1020 GPHY_CFG_PWDOWN_HW | GPHY_CFG_100AB_ENB); 1021 val |= GPHY_CFG_SEL_ANA_RESET; 1022 #ifdef notyet 1023 val |= GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN | GPHY_CFG_SEL_ANA_RESET; 1024 #else 1025 /* Disable PHY hibernation. */ 1026 val &= ~(GPHY_CFG_HIB_PULSE | GPHY_CFG_HIB_EN); 1027 #endif 1028 CSR_WRITE_4(sc, ALC_GPHY_CFG, val); 1029 DELAY(10); 1030 CSR_WRITE_4(sc, ALC_GPHY_CFG, val | GPHY_CFG_EXT_RESET); 1031 DELAY(800); 1032 1033 /* Vendor PHY magic. */ 1034 #ifdef notyet 1035 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, DBG_LEGCYPS_DEFAULT); 1036 alc_miidbg_writereg(sc, MII_DBG_SYSMODCTL, DBG_SYSMODCTL_DEFAULT); 1037 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_VDRVBIAS, 1038 EXT_VDRVBIAS_DEFAULT); 1039 #else 1040 /* Disable PHY hibernation. */ 1041 alc_miidbg_writereg(sc, MII_DBG_LEGCYPS, 1042 DBG_LEGCYPS_DEFAULT & ~DBG_LEGCYPS_ENB); 1043 alc_miidbg_writereg(sc, MII_DBG_HIBNEG, 1044 DBG_HIBNEG_DEFAULT & ~(DBG_HIBNEG_PSHIB_EN | DBG_HIBNEG_HIB_PULSE)); 1045 alc_miidbg_writereg(sc, MII_DBG_GREENCFG, DBG_GREENCFG_DEFAULT); 1046 #endif 1047 1048 /* XXX Disable EEE. */ 1049 val = CSR_READ_4(sc, ALC_LPI_CTL); 1050 val &= ~LPI_CTL_ENB; 1051 CSR_WRITE_4(sc, ALC_LPI_CTL, val); 1052 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_LOCAL_EEEADV, 0); 1053 1054 /* PHY power saving. */ 1055 alc_miidbg_writereg(sc, MII_DBG_TST10BTCFG, DBG_TST10BTCFG_DEFAULT); 1056 alc_miidbg_writereg(sc, MII_DBG_SRDSYSMOD, DBG_SRDSYSMOD_DEFAULT); 1057 alc_miidbg_writereg(sc, MII_DBG_TST100BTCFG, DBG_TST100BTCFG_DEFAULT); 1058 alc_miidbg_writereg(sc, MII_DBG_ANACTL, DBG_ANACTL_DEFAULT); 1059 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1060 val &= ~DBG_GREENCFG2_GATE_DFSE_EN; 1061 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1062 1063 /* RTL8139C, 120m issue. */ 1064 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_NLP78, 1065 ANEG_NLP78_120M_DEFAULT); 1066 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 1067 ANEG_S3DIG10_DEFAULT); 1068 1069 if ((sc->alc_flags & ALC_FLAG_LINK_WAR) != 0) { 1070 /* Turn off half amplitude. */ 1071 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3); 1072 val |= EXT_CLDCTL3_BP_CABLE1TH_DET_GT; 1073 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL3, val); 1074 /* Turn off Green feature. */ 1075 val = alc_miidbg_readreg(sc, MII_DBG_GREENCFG2); 1076 val |= DBG_GREENCFG2_BP_GREEN; 1077 alc_miidbg_writereg(sc, MII_DBG_GREENCFG2, val); 1078 /* Turn off half bias. */ 1079 val = alc_miiext_readreg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5); 1080 val |= EXT_CLDCTL5_BP_VD_HLFBIAS; 1081 alc_miiext_writereg(sc, MII_EXT_PCS, MII_EXT_CLDCTL5, val); 1082 } 1083 } 1084 1085 static void 1086 alc_phy_down(struct alc_softc *sc) 1087 { 1088 uint32_t gphy; 1089 1090 switch (sc->alc_ident->deviceid) { 1091 case DEVICEID_ATHEROS_AR8161: 1092 case DEVICEID_ATHEROS_E2200: 1093 case DEVICEID_ATHEROS_E2400: 1094 case DEVICEID_ATHEROS_E2500: 1095 case DEVICEID_ATHEROS_AR8162: 1096 case DEVICEID_ATHEROS_AR8171: 1097 case DEVICEID_ATHEROS_AR8172: 1098 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 1099 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | 1100 GPHY_CFG_100AB_ENB | GPHY_CFG_PHY_PLL_ON); 1101 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | 1102 GPHY_CFG_SEL_ANA_RESET; 1103 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 1104 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 1105 break; 1106 case DEVICEID_ATHEROS_AR8151: 1107 case DEVICEID_ATHEROS_AR8151_V2: 1108 case DEVICEID_ATHEROS_AR8152_B: 1109 case DEVICEID_ATHEROS_AR8152_B2: 1110 /* 1111 * GPHY power down caused more problems on AR8151 v2.0. 1112 * When driver is reloaded after GPHY power down, 1113 * accesses to PHY/MAC registers hung the system. Only 1114 * cold boot recovered from it. I'm not sure whether 1115 * AR8151 v1.0 also requires this one though. I don't 1116 * have AR8151 v1.0 controller in hand. 1117 * The only option left is to isolate the PHY and 1118 * initiates power down the PHY which in turn saves 1119 * more power when driver is unloaded. 1120 */ 1121 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 1122 MII_BMCR, BMCR_ISO | BMCR_PDOWN); 1123 break; 1124 default: 1125 /* Force PHY down. */ 1126 CSR_WRITE_2(sc, ALC_GPHY_CFG, GPHY_CFG_EXT_RESET | 1127 GPHY_CFG_SEL_ANA_RESET | GPHY_CFG_PHY_IDDQ | 1128 GPHY_CFG_PWDOWN_HW); 1129 DELAY(1000); 1130 break; 1131 } 1132 } 1133 1134 static void 1135 alc_aspm(struct alc_softc *sc, int init, int media) 1136 { 1137 1138 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1139 alc_aspm_816x(sc, init); 1140 else 1141 alc_aspm_813x(sc, media); 1142 } 1143 1144 static void 1145 alc_aspm_813x(struct alc_softc *sc, int media) 1146 { 1147 uint32_t pmcfg; 1148 uint16_t linkcfg; 1149 1150 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) 1151 return; 1152 1153 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1154 if ((sc->alc_flags & (ALC_FLAG_APS | ALC_FLAG_PCIE)) == 1155 (ALC_FLAG_APS | ALC_FLAG_PCIE)) 1156 linkcfg = CSR_READ_2(sc, sc->alc_expcap + 1157 PCIER_LINK_CTL); 1158 else 1159 linkcfg = 0; 1160 pmcfg &= ~PM_CFG_SERDES_PD_EX_L1; 1161 pmcfg &= ~(PM_CFG_L1_ENTRY_TIMER_MASK | PM_CFG_LCKDET_TIMER_MASK); 1162 pmcfg |= PM_CFG_MAC_ASPM_CHK; 1163 pmcfg |= (PM_CFG_LCKDET_TIMER_DEFAULT << PM_CFG_LCKDET_TIMER_SHIFT); 1164 pmcfg &= ~(PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1165 1166 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1167 /* Disable extended sync except AR8152 B v1.0 */ 1168 linkcfg &= ~PCIEM_LINK_CTL_EXTENDED_SYNC; 1169 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1170 sc->alc_rev == ATHEROS_AR8152_B_V10) 1171 linkcfg |= PCIEM_LINK_CTL_EXTENDED_SYNC; 1172 CSR_WRITE_2(sc, sc->alc_expcap + PCIER_LINK_CTL, 1173 linkcfg); 1174 pmcfg &= ~(PM_CFG_EN_BUFS_RX_L0S | PM_CFG_SA_DLY_ENB | 1175 PM_CFG_HOTRST); 1176 pmcfg |= (PM_CFG_L1_ENTRY_TIMER_DEFAULT << 1177 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1178 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1179 pmcfg |= (PM_CFG_PM_REQ_TIMER_DEFAULT << 1180 PM_CFG_PM_REQ_TIMER_SHIFT); 1181 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_PCIE_RECV; 1182 } 1183 1184 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1185 if ((sc->alc_flags & ALC_FLAG_L0S) != 0) 1186 pmcfg |= PM_CFG_ASPM_L0S_ENB; 1187 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1188 pmcfg |= PM_CFG_ASPM_L1_ENB; 1189 if ((sc->alc_flags & ALC_FLAG_APS) != 0) { 1190 if (sc->alc_ident->deviceid == 1191 DEVICEID_ATHEROS_AR8152_B) 1192 pmcfg &= ~PM_CFG_ASPM_L0S_ENB; 1193 pmcfg &= ~(PM_CFG_SERDES_L1_ENB | 1194 PM_CFG_SERDES_PLL_L1_ENB | 1195 PM_CFG_SERDES_BUDS_RX_L1_ENB); 1196 pmcfg |= PM_CFG_CLK_SWH_L1; 1197 if (media == IFM_100_TX || media == IFM_1000_T) { 1198 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_MASK; 1199 switch (sc->alc_ident->deviceid) { 1200 case DEVICEID_ATHEROS_AR8152_B: 1201 pmcfg |= (7 << 1202 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1203 break; 1204 case DEVICEID_ATHEROS_AR8152_B2: 1205 case DEVICEID_ATHEROS_AR8151_V2: 1206 pmcfg |= (4 << 1207 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1208 break; 1209 default: 1210 pmcfg |= (15 << 1211 PM_CFG_L1_ENTRY_TIMER_SHIFT); 1212 break; 1213 } 1214 } 1215 } else { 1216 pmcfg |= PM_CFG_SERDES_L1_ENB | 1217 PM_CFG_SERDES_PLL_L1_ENB | 1218 PM_CFG_SERDES_BUDS_RX_L1_ENB; 1219 pmcfg &= ~(PM_CFG_CLK_SWH_L1 | 1220 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB); 1221 } 1222 } else { 1223 pmcfg &= ~(PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SERDES_L1_ENB | 1224 PM_CFG_SERDES_PLL_L1_ENB); 1225 pmcfg |= PM_CFG_CLK_SWH_L1; 1226 if ((sc->alc_flags & ALC_FLAG_L1S) != 0) 1227 pmcfg |= PM_CFG_ASPM_L1_ENB; 1228 } 1229 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1230 } 1231 1232 static void 1233 alc_aspm_816x(struct alc_softc *sc, int init) 1234 { 1235 uint32_t pmcfg; 1236 1237 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 1238 pmcfg &= ~PM_CFG_L1_ENTRY_TIMER_816X_MASK; 1239 pmcfg |= PM_CFG_L1_ENTRY_TIMER_816X_DEFAULT; 1240 pmcfg &= ~PM_CFG_PM_REQ_TIMER_MASK; 1241 pmcfg |= PM_CFG_PM_REQ_TIMER_816X_DEFAULT; 1242 pmcfg &= ~PM_CFG_LCKDET_TIMER_MASK; 1243 pmcfg |= PM_CFG_LCKDET_TIMER_DEFAULT; 1244 pmcfg |= PM_CFG_SERDES_PD_EX_L1 | PM_CFG_CLK_SWH_L1 | PM_CFG_PCIE_RECV; 1245 pmcfg &= ~(PM_CFG_RX_L1_AFTER_L0S | PM_CFG_TX_L1_AFTER_L0S | 1246 PM_CFG_ASPM_L1_ENB | PM_CFG_ASPM_L0S_ENB | 1247 PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB | 1248 PM_CFG_SERDES_BUDS_RX_L1_ENB | PM_CFG_SA_DLY_ENB | 1249 PM_CFG_MAC_ASPM_CHK | PM_CFG_HOTRST); 1250 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1251 (sc->alc_rev & 0x01) != 0) 1252 pmcfg |= PM_CFG_SERDES_L1_ENB | PM_CFG_SERDES_PLL_L1_ENB; 1253 if ((sc->alc_flags & ALC_FLAG_LINK) != 0) { 1254 /* Link up, enable both L0s, L1s. */ 1255 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1256 PM_CFG_MAC_ASPM_CHK; 1257 } else { 1258 if (init != 0) 1259 pmcfg |= PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB | 1260 PM_CFG_MAC_ASPM_CHK; 1261 else if ((sc->alc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1262 pmcfg |= PM_CFG_ASPM_L1_ENB | PM_CFG_MAC_ASPM_CHK; 1263 } 1264 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 1265 } 1266 1267 static void 1268 alc_init_pcie(struct alc_softc *sc) 1269 { 1270 const char *aspm_state[] = { "L0s/L1", "L0s", "L1", "L0s/L1" }; 1271 uint32_t cap, ctl, val; 1272 int state; 1273 1274 /* Clear data link and flow-control protocol error. */ 1275 val = CSR_READ_4(sc, ALC_PEX_UNC_ERR_SEV); 1276 val &= ~(PEX_UNC_ERR_SEV_DLP | PEX_UNC_ERR_SEV_FCP); 1277 CSR_WRITE_4(sc, ALC_PEX_UNC_ERR_SEV, val); 1278 1279 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1280 CSR_WRITE_4(sc, ALC_LTSSM_ID_CFG, 1281 CSR_READ_4(sc, ALC_LTSSM_ID_CFG) & ~LTSSM_ID_WRO_ENB); 1282 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, 1283 CSR_READ_4(sc, ALC_PCIE_PHYMISC) | 1284 PCIE_PHYMISC_FORCE_RCV_DET); 1285 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B && 1286 sc->alc_rev == ATHEROS_AR8152_B_V10) { 1287 val = CSR_READ_4(sc, ALC_PCIE_PHYMISC2); 1288 val &= ~(PCIE_PHYMISC2_SERDES_CDR_MASK | 1289 PCIE_PHYMISC2_SERDES_TH_MASK); 1290 val |= 3 << PCIE_PHYMISC2_SERDES_CDR_SHIFT; 1291 val |= 3 << PCIE_PHYMISC2_SERDES_TH_SHIFT; 1292 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC2, val); 1293 } 1294 /* Disable ASPM L0S and L1. */ 1295 cap = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CAP); 1296 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1297 ctl = CSR_READ_2(sc, sc->alc_expcap + PCIER_LINK_CTL); 1298 if ((ctl & PCIEM_LINK_CTL_RCB) != 0) 1299 sc->alc_rcb = DMA_CFG_RCB_128; 1300 if (bootverbose) 1301 device_printf(sc->alc_dev, "RCB %u bytes\n", 1302 sc->alc_rcb == DMA_CFG_RCB_64 ? 64 : 128); 1303 state = ctl & PCIEM_LINK_CTL_ASPMC; 1304 if (state & PCIEM_LINK_CTL_ASPMC_L0S) 1305 sc->alc_flags |= ALC_FLAG_L0S; 1306 if (state & PCIEM_LINK_CTL_ASPMC_L1) 1307 sc->alc_flags |= ALC_FLAG_L1S; 1308 if (bootverbose) 1309 device_printf(sc->alc_dev, "ASPM %s %s\n", 1310 aspm_state[state], 1311 state == 0 ? "disabled" : "enabled"); 1312 alc_disable_l0s_l1(sc); 1313 } else { 1314 if (bootverbose) 1315 device_printf(sc->alc_dev, 1316 "no ASPM support\n"); 1317 } 1318 } else { 1319 val = CSR_READ_4(sc, ALC_PDLL_TRNS1); 1320 val &= ~PDLL_TRNS1_D3PLLOFF_ENB; 1321 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, val); 1322 val = CSR_READ_4(sc, ALC_MASTER_CFG); 1323 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 1324 (sc->alc_rev & 0x01) != 0) { 1325 if ((val & MASTER_WAKEN_25M) == 0 || 1326 (val & MASTER_CLK_SEL_DIS) == 0) { 1327 val |= MASTER_WAKEN_25M | MASTER_CLK_SEL_DIS; 1328 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1329 } 1330 } else { 1331 if ((val & MASTER_WAKEN_25M) == 0 || 1332 (val & MASTER_CLK_SEL_DIS) != 0) { 1333 val |= MASTER_WAKEN_25M; 1334 val &= ~MASTER_CLK_SEL_DIS; 1335 CSR_WRITE_4(sc, ALC_MASTER_CFG, val); 1336 } 1337 } 1338 } 1339 alc_aspm(sc, 1, IFM_UNKNOWN); 1340 } 1341 1342 static void 1343 alc_config_msi(struct alc_softc *sc) 1344 { 1345 uint32_t ctl, mod; 1346 1347 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 1348 /* 1349 * It seems interrupt moderation is controlled by 1350 * ALC_MSI_RETRANS_TIMER register if MSI/MSIX is active. 1351 * Driver uses RX interrupt moderation parameter to 1352 * program ALC_MSI_RETRANS_TIMER register. 1353 */ 1354 ctl = CSR_READ_4(sc, ALC_MSI_RETRANS_TIMER); 1355 ctl &= ~MSI_RETRANS_TIMER_MASK; 1356 ctl &= ~MSI_RETRANS_MASK_SEL_LINE; 1357 mod = ALC_USECS(sc->alc_int_rx_mod); 1358 if (mod == 0) 1359 mod = 1; 1360 ctl |= mod; 1361 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1362 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1363 MSI_RETRANS_MASK_SEL_STD); 1364 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1365 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, ctl | 1366 MSI_RETRANS_MASK_SEL_LINE); 1367 else 1368 CSR_WRITE_4(sc, ALC_MSI_RETRANS_TIMER, 0); 1369 } 1370 } 1371 1372 static int 1373 alc_attach(device_t dev) 1374 { 1375 struct alc_softc *sc; 1376 struct ifnet *ifp; 1377 int base, error, i, msic, msixc; 1378 uint16_t burst; 1379 1380 error = 0; 1381 sc = device_get_softc(dev); 1382 sc->alc_dev = dev; 1383 sc->alc_rev = pci_get_revid(dev); 1384 1385 mtx_init(&sc->alc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1386 MTX_DEF); 1387 callout_init_mtx(&sc->alc_tick_ch, &sc->alc_mtx, 0); 1388 TASK_INIT(&sc->alc_int_task, 0, alc_int_task, sc); 1389 sc->alc_ident = alc_find_ident(dev); 1390 1391 /* Map the device. */ 1392 pci_enable_busmaster(dev); 1393 sc->alc_res_spec = alc_res_spec_mem; 1394 sc->alc_irq_spec = alc_irq_spec_legacy; 1395 error = bus_alloc_resources(dev, sc->alc_res_spec, sc->alc_res); 1396 if (error != 0) { 1397 device_printf(dev, "cannot allocate memory resources.\n"); 1398 goto fail; 1399 } 1400 1401 /* Set PHY address. */ 1402 sc->alc_phyaddr = ALC_PHY_ADDR; 1403 1404 /* 1405 * One odd thing is AR8132 uses the same PHY hardware(F1 1406 * gigabit PHY) of AR8131. So atphy(4) of AR8132 reports 1407 * the PHY supports 1000Mbps but that's not true. The PHY 1408 * used in AR8132 can't establish gigabit link even if it 1409 * shows the same PHY model/revision number of AR8131. 1410 */ 1411 switch (sc->alc_ident->deviceid) { 1412 case DEVICEID_ATHEROS_E2200: 1413 case DEVICEID_ATHEROS_E2400: 1414 case DEVICEID_ATHEROS_E2500: 1415 sc->alc_flags |= ALC_FLAG_E2X00; 1416 /* FALLTHROUGH */ 1417 case DEVICEID_ATHEROS_AR8161: 1418 if (pci_get_subvendor(dev) == VENDORID_ATHEROS && 1419 pci_get_subdevice(dev) == 0x0091 && sc->alc_rev == 0) 1420 sc->alc_flags |= ALC_FLAG_LINK_WAR; 1421 /* FALLTHROUGH */ 1422 case DEVICEID_ATHEROS_AR8171: 1423 sc->alc_flags |= ALC_FLAG_AR816X_FAMILY; 1424 break; 1425 case DEVICEID_ATHEROS_AR8162: 1426 case DEVICEID_ATHEROS_AR8172: 1427 sc->alc_flags |= ALC_FLAG_FASTETHER | ALC_FLAG_AR816X_FAMILY; 1428 break; 1429 case DEVICEID_ATHEROS_AR8152_B: 1430 case DEVICEID_ATHEROS_AR8152_B2: 1431 sc->alc_flags |= ALC_FLAG_APS; 1432 /* FALLTHROUGH */ 1433 case DEVICEID_ATHEROS_AR8132: 1434 sc->alc_flags |= ALC_FLAG_FASTETHER; 1435 break; 1436 case DEVICEID_ATHEROS_AR8151: 1437 case DEVICEID_ATHEROS_AR8151_V2: 1438 sc->alc_flags |= ALC_FLAG_APS; 1439 /* FALLTHROUGH */ 1440 default: 1441 break; 1442 } 1443 sc->alc_flags |= ALC_FLAG_JUMBO; 1444 1445 /* 1446 * It seems that AR813x/AR815x has silicon bug for SMB. In 1447 * addition, Atheros said that enabling SMB wouldn't improve 1448 * performance. However I think it's bad to access lots of 1449 * registers to extract MAC statistics. 1450 */ 1451 sc->alc_flags |= ALC_FLAG_SMB_BUG; 1452 /* 1453 * Don't use Tx CMB. It is known to have silicon bug. 1454 */ 1455 sc->alc_flags |= ALC_FLAG_CMB_BUG; 1456 sc->alc_chip_rev = CSR_READ_4(sc, ALC_MASTER_CFG) >> 1457 MASTER_CHIP_REV_SHIFT; 1458 if (bootverbose) { 1459 device_printf(dev, "PCI device revision : 0x%04x\n", 1460 sc->alc_rev); 1461 device_printf(dev, "Chip id/revision : 0x%04x\n", 1462 sc->alc_chip_rev); 1463 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 1464 device_printf(dev, "AR816x revision : 0x%x\n", 1465 AR816X_REV(sc->alc_rev)); 1466 } 1467 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", 1468 CSR_READ_4(sc, ALC_SRAM_TX_FIFO_LEN) * 8, 1469 CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN) * 8); 1470 1471 /* Initialize DMA parameters. */ 1472 sc->alc_dma_rd_burst = 0; 1473 sc->alc_dma_wr_burst = 0; 1474 sc->alc_rcb = DMA_CFG_RCB_64; 1475 if (pci_find_cap(dev, PCIY_EXPRESS, &base) == 0) { 1476 sc->alc_flags |= ALC_FLAG_PCIE; 1477 sc->alc_expcap = base; 1478 burst = CSR_READ_2(sc, base + PCIER_DEVICE_CTL); 1479 sc->alc_dma_rd_burst = 1480 (burst & PCIEM_CTL_MAX_READ_REQUEST) >> 12; 1481 sc->alc_dma_wr_burst = (burst & PCIEM_CTL_MAX_PAYLOAD) >> 5; 1482 if (bootverbose) { 1483 device_printf(dev, "Read request size : %u bytes.\n", 1484 alc_dma_burst[sc->alc_dma_rd_burst]); 1485 device_printf(dev, "TLP payload size : %u bytes.\n", 1486 alc_dma_burst[sc->alc_dma_wr_burst]); 1487 } 1488 if (alc_dma_burst[sc->alc_dma_rd_burst] > 1024) 1489 sc->alc_dma_rd_burst = 3; 1490 if (alc_dma_burst[sc->alc_dma_wr_burst] > 1024) 1491 sc->alc_dma_wr_burst = 3; 1492 /* 1493 * Force maximum payload size to 128 bytes for 1494 * E2200/E2400/E2500. 1495 * Otherwise it triggers DMA write error. 1496 */ 1497 if ((sc->alc_flags & ALC_FLAG_E2X00) != 0) 1498 sc->alc_dma_wr_burst = 0; 1499 alc_init_pcie(sc); 1500 } 1501 1502 /* Reset PHY. */ 1503 alc_phy_reset(sc); 1504 1505 /* Reset the ethernet controller. */ 1506 alc_stop_mac(sc); 1507 alc_reset(sc); 1508 1509 /* Allocate IRQ resources. */ 1510 msixc = pci_msix_count(dev); 1511 msic = pci_msi_count(dev); 1512 if (bootverbose) { 1513 device_printf(dev, "MSIX count : %d\n", msixc); 1514 device_printf(dev, "MSI count : %d\n", msic); 1515 } 1516 if (msixc > 1) 1517 msixc = 1; 1518 if (msic > 1) 1519 msic = 1; 1520 /* 1521 * Prefer MSIX over MSI. 1522 * AR816x controller has a silicon bug that MSI interrupt 1523 * does not assert if PCIM_CMD_INTxDIS bit of command 1524 * register is set. pci(4) was taught to handle that case. 1525 */ 1526 if (msix_disable == 0 || msi_disable == 0) { 1527 if (msix_disable == 0 && msixc > 0 && 1528 pci_alloc_msix(dev, &msixc) == 0) { 1529 if (msic == 1) { 1530 device_printf(dev, 1531 "Using %d MSIX message(s).\n", msixc); 1532 sc->alc_flags |= ALC_FLAG_MSIX; 1533 sc->alc_irq_spec = alc_irq_spec_msix; 1534 } else 1535 pci_release_msi(dev); 1536 } 1537 if (msi_disable == 0 && (sc->alc_flags & ALC_FLAG_MSIX) == 0 && 1538 msic > 0 && pci_alloc_msi(dev, &msic) == 0) { 1539 if (msic == 1) { 1540 device_printf(dev, 1541 "Using %d MSI message(s).\n", msic); 1542 sc->alc_flags |= ALC_FLAG_MSI; 1543 sc->alc_irq_spec = alc_irq_spec_msi; 1544 } else 1545 pci_release_msi(dev); 1546 } 1547 } 1548 1549 error = bus_alloc_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1550 if (error != 0) { 1551 device_printf(dev, "cannot allocate IRQ resources.\n"); 1552 goto fail; 1553 } 1554 1555 /* Create device sysctl node. */ 1556 alc_sysctl_node(sc); 1557 1558 if ((error = alc_dma_alloc(sc)) != 0) 1559 goto fail; 1560 1561 /* Load station address. */ 1562 alc_get_macaddr(sc); 1563 1564 ifp = sc->alc_ifp = if_alloc(IFT_ETHER); 1565 if (ifp == NULL) { 1566 device_printf(dev, "cannot allocate ifnet structure.\n"); 1567 error = ENXIO; 1568 goto fail; 1569 } 1570 1571 ifp->if_softc = sc; 1572 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1573 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1574 ifp->if_ioctl = alc_ioctl; 1575 ifp->if_start = alc_start; 1576 ifp->if_init = alc_init; 1577 ifp->if_snd.ifq_drv_maxlen = ALC_TX_RING_CNT - 1; 1578 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 1579 IFQ_SET_READY(&ifp->if_snd); 1580 ifp->if_capabilities = IFCAP_TXCSUM | IFCAP_TSO4; 1581 ifp->if_hwassist = ALC_CSUM_FEATURES | CSUM_TSO; 1582 if (pci_find_cap(dev, PCIY_PMG, &base) == 0) { 1583 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 1584 sc->alc_flags |= ALC_FLAG_PM; 1585 sc->alc_pmcap = base; 1586 } 1587 ifp->if_capenable = ifp->if_capabilities; 1588 1589 /* Set up MII bus. */ 1590 error = mii_attach(dev, &sc->alc_miibus, ifp, alc_mediachange, 1591 alc_mediastatus, BMSR_DEFCAPMASK, sc->alc_phyaddr, MII_OFFSET_ANY, 1592 MIIF_DOPAUSE); 1593 if (error != 0) { 1594 device_printf(dev, "attaching PHYs failed\n"); 1595 goto fail; 1596 } 1597 1598 ether_ifattach(ifp, sc->alc_eaddr); 1599 1600 /* VLAN capability setup. */ 1601 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 1602 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 1603 ifp->if_capenable = ifp->if_capabilities; 1604 /* 1605 * XXX 1606 * It seems enabling Tx checksum offloading makes more trouble. 1607 * Sometimes the controller does not receive any frames when 1608 * Tx checksum offloading is enabled. I'm not sure whether this 1609 * is a bug in Tx checksum offloading logic or I got broken 1610 * sample boards. To safety, don't enable Tx checksum offloading 1611 * by default but give chance to users to toggle it if they know 1612 * their controllers work without problems. 1613 * Fortunately, Tx checksum offloading for AR816x family 1614 * seems to work. 1615 */ 1616 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 1617 ifp->if_capenable &= ~IFCAP_TXCSUM; 1618 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 1619 } 1620 1621 /* Tell the upper layer(s) we support long frames. */ 1622 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 1623 1624 /* Create local taskq. */ 1625 sc->alc_tq = taskqueue_create_fast("alc_taskq", M_WAITOK, 1626 taskqueue_thread_enqueue, &sc->alc_tq); 1627 if (sc->alc_tq == NULL) { 1628 device_printf(dev, "could not create taskqueue.\n"); 1629 ether_ifdetach(ifp); 1630 error = ENXIO; 1631 goto fail; 1632 } 1633 taskqueue_start_threads(&sc->alc_tq, 1, PI_NET, "%s taskq", 1634 device_get_nameunit(sc->alc_dev)); 1635 1636 alc_config_msi(sc); 1637 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1638 msic = ALC_MSIX_MESSAGES; 1639 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1640 msic = ALC_MSI_MESSAGES; 1641 else 1642 msic = 1; 1643 for (i = 0; i < msic; i++) { 1644 error = bus_setup_intr(dev, sc->alc_irq[i], 1645 INTR_TYPE_NET | INTR_MPSAFE, alc_intr, NULL, sc, 1646 &sc->alc_intrhand[i]); 1647 if (error != 0) 1648 break; 1649 } 1650 if (error != 0) { 1651 device_printf(dev, "could not set up interrupt handler.\n"); 1652 taskqueue_free(sc->alc_tq); 1653 sc->alc_tq = NULL; 1654 ether_ifdetach(ifp); 1655 goto fail; 1656 } 1657 1658 /* Attach driver netdump methods. */ 1659 NETDUMP_SET(ifp, alc); 1660 1661 fail: 1662 if (error != 0) 1663 alc_detach(dev); 1664 1665 return (error); 1666 } 1667 1668 static int 1669 alc_detach(device_t dev) 1670 { 1671 struct alc_softc *sc; 1672 struct ifnet *ifp; 1673 int i, msic; 1674 1675 sc = device_get_softc(dev); 1676 1677 ifp = sc->alc_ifp; 1678 if (device_is_attached(dev)) { 1679 ether_ifdetach(ifp); 1680 ALC_LOCK(sc); 1681 alc_stop(sc); 1682 ALC_UNLOCK(sc); 1683 callout_drain(&sc->alc_tick_ch); 1684 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1685 } 1686 1687 if (sc->alc_tq != NULL) { 1688 taskqueue_drain(sc->alc_tq, &sc->alc_int_task); 1689 taskqueue_free(sc->alc_tq); 1690 sc->alc_tq = NULL; 1691 } 1692 1693 if (sc->alc_miibus != NULL) { 1694 device_delete_child(dev, sc->alc_miibus); 1695 sc->alc_miibus = NULL; 1696 } 1697 bus_generic_detach(dev); 1698 alc_dma_free(sc); 1699 1700 if (ifp != NULL) { 1701 if_free(ifp); 1702 sc->alc_ifp = NULL; 1703 } 1704 1705 if ((sc->alc_flags & ALC_FLAG_MSIX) != 0) 1706 msic = ALC_MSIX_MESSAGES; 1707 else if ((sc->alc_flags & ALC_FLAG_MSI) != 0) 1708 msic = ALC_MSI_MESSAGES; 1709 else 1710 msic = 1; 1711 for (i = 0; i < msic; i++) { 1712 if (sc->alc_intrhand[i] != NULL) { 1713 bus_teardown_intr(dev, sc->alc_irq[i], 1714 sc->alc_intrhand[i]); 1715 sc->alc_intrhand[i] = NULL; 1716 } 1717 } 1718 if (sc->alc_res[0] != NULL) 1719 alc_phy_down(sc); 1720 bus_release_resources(dev, sc->alc_irq_spec, sc->alc_irq); 1721 if ((sc->alc_flags & (ALC_FLAG_MSI | ALC_FLAG_MSIX)) != 0) 1722 pci_release_msi(dev); 1723 bus_release_resources(dev, sc->alc_res_spec, sc->alc_res); 1724 mtx_destroy(&sc->alc_mtx); 1725 1726 return (0); 1727 } 1728 1729 #define ALC_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 1730 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 1731 #define ALC_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 1732 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 1733 1734 static void 1735 alc_sysctl_node(struct alc_softc *sc) 1736 { 1737 struct sysctl_ctx_list *ctx; 1738 struct sysctl_oid_list *child, *parent; 1739 struct sysctl_oid *tree; 1740 struct alc_hw_stats *stats; 1741 int error; 1742 1743 stats = &sc->alc_stats; 1744 ctx = device_get_sysctl_ctx(sc->alc_dev); 1745 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->alc_dev)); 1746 1747 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 1748 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_rx_mod, 0, 1749 sysctl_hw_alc_int_mod, "I", "alc Rx interrupt moderation"); 1750 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 1751 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_int_tx_mod, 0, 1752 sysctl_hw_alc_int_mod, "I", "alc Tx interrupt moderation"); 1753 /* Pull in device tunables. */ 1754 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1755 error = resource_int_value(device_get_name(sc->alc_dev), 1756 device_get_unit(sc->alc_dev), "int_rx_mod", &sc->alc_int_rx_mod); 1757 if (error == 0) { 1758 if (sc->alc_int_rx_mod < ALC_IM_TIMER_MIN || 1759 sc->alc_int_rx_mod > ALC_IM_TIMER_MAX) { 1760 device_printf(sc->alc_dev, "int_rx_mod value out of " 1761 "range; using default: %d\n", 1762 ALC_IM_RX_TIMER_DEFAULT); 1763 sc->alc_int_rx_mod = ALC_IM_RX_TIMER_DEFAULT; 1764 } 1765 } 1766 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1767 error = resource_int_value(device_get_name(sc->alc_dev), 1768 device_get_unit(sc->alc_dev), "int_tx_mod", &sc->alc_int_tx_mod); 1769 if (error == 0) { 1770 if (sc->alc_int_tx_mod < ALC_IM_TIMER_MIN || 1771 sc->alc_int_tx_mod > ALC_IM_TIMER_MAX) { 1772 device_printf(sc->alc_dev, "int_tx_mod value out of " 1773 "range; using default: %d\n", 1774 ALC_IM_TX_TIMER_DEFAULT); 1775 sc->alc_int_tx_mod = ALC_IM_TX_TIMER_DEFAULT; 1776 } 1777 } 1778 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 1779 CTLTYPE_INT | CTLFLAG_RW, &sc->alc_process_limit, 0, 1780 sysctl_hw_alc_proc_limit, "I", 1781 "max number of Rx events to process"); 1782 /* Pull in device tunables. */ 1783 sc->alc_process_limit = ALC_PROC_DEFAULT; 1784 error = resource_int_value(device_get_name(sc->alc_dev), 1785 device_get_unit(sc->alc_dev), "process_limit", 1786 &sc->alc_process_limit); 1787 if (error == 0) { 1788 if (sc->alc_process_limit < ALC_PROC_MIN || 1789 sc->alc_process_limit > ALC_PROC_MAX) { 1790 device_printf(sc->alc_dev, 1791 "process_limit value out of range; " 1792 "using default: %d\n", ALC_PROC_DEFAULT); 1793 sc->alc_process_limit = ALC_PROC_DEFAULT; 1794 } 1795 } 1796 1797 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 1798 NULL, "ALC statistics"); 1799 parent = SYSCTL_CHILDREN(tree); 1800 1801 /* Rx statistics. */ 1802 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 1803 NULL, "Rx MAC statistics"); 1804 child = SYSCTL_CHILDREN(tree); 1805 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1806 &stats->rx_frames, "Good frames"); 1807 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1808 &stats->rx_bcast_frames, "Good broadcast frames"); 1809 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1810 &stats->rx_mcast_frames, "Good multicast frames"); 1811 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1812 &stats->rx_pause_frames, "Pause control frames"); 1813 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1814 &stats->rx_control_frames, "Control frames"); 1815 ALC_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 1816 &stats->rx_crcerrs, "CRC errors"); 1817 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1818 &stats->rx_lenerrs, "Frames with length mismatched"); 1819 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1820 &stats->rx_bytes, "Good octets"); 1821 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1822 &stats->rx_bcast_bytes, "Good broadcast octets"); 1823 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1824 &stats->rx_mcast_bytes, "Good multicast octets"); 1825 ALC_SYSCTL_STAT_ADD32(ctx, child, "runts", 1826 &stats->rx_runts, "Too short frames"); 1827 ALC_SYSCTL_STAT_ADD32(ctx, child, "fragments", 1828 &stats->rx_fragments, "Fragmented frames"); 1829 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1830 &stats->rx_pkts_64, "64 bytes frames"); 1831 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1832 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 1833 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1834 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 1835 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1836 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 1837 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1838 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 1839 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1840 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1841 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1842 &stats->rx_pkts_1519_max, "1519 to max frames"); 1843 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1844 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 1845 ALC_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 1846 &stats->rx_fifo_oflows, "FIFO overflows"); 1847 ALC_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 1848 &stats->rx_rrs_errs, "Return status write-back errors"); 1849 ALC_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 1850 &stats->rx_alignerrs, "Alignment errors"); 1851 ALC_SYSCTL_STAT_ADD32(ctx, child, "filtered", 1852 &stats->rx_pkts_filtered, 1853 "Frames dropped due to address filtering"); 1854 1855 /* Tx statistics. */ 1856 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 1857 NULL, "Tx MAC statistics"); 1858 child = SYSCTL_CHILDREN(tree); 1859 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 1860 &stats->tx_frames, "Good frames"); 1861 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 1862 &stats->tx_bcast_frames, "Good broadcast frames"); 1863 ALC_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 1864 &stats->tx_mcast_frames, "Good multicast frames"); 1865 ALC_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 1866 &stats->tx_pause_frames, "Pause control frames"); 1867 ALC_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 1868 &stats->tx_control_frames, "Control frames"); 1869 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 1870 &stats->tx_excess_defer, "Frames with excessive derferrals"); 1871 ALC_SYSCTL_STAT_ADD32(ctx, child, "defers", 1872 &stats->tx_excess_defer, "Frames with derferrals"); 1873 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 1874 &stats->tx_bytes, "Good octets"); 1875 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 1876 &stats->tx_bcast_bytes, "Good broadcast octets"); 1877 ALC_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 1878 &stats->tx_mcast_bytes, "Good multicast octets"); 1879 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 1880 &stats->tx_pkts_64, "64 bytes frames"); 1881 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 1882 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 1883 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 1884 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 1885 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 1886 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 1887 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 1888 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 1889 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 1890 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 1891 ALC_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 1892 &stats->tx_pkts_1519_max, "1519 to max frames"); 1893 ALC_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 1894 &stats->tx_single_colls, "Single collisions"); 1895 ALC_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 1896 &stats->tx_multi_colls, "Multiple collisions"); 1897 ALC_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 1898 &stats->tx_late_colls, "Late collisions"); 1899 ALC_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 1900 &stats->tx_excess_colls, "Excessive collisions"); 1901 ALC_SYSCTL_STAT_ADD32(ctx, child, "underruns", 1902 &stats->tx_underrun, "FIFO underruns"); 1903 ALC_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 1904 &stats->tx_desc_underrun, "Descriptor write-back errors"); 1905 ALC_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 1906 &stats->tx_lenerrs, "Frames with length mismatched"); 1907 ALC_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 1908 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 1909 } 1910 1911 #undef ALC_SYSCTL_STAT_ADD32 1912 #undef ALC_SYSCTL_STAT_ADD64 1913 1914 struct alc_dmamap_arg { 1915 bus_addr_t alc_busaddr; 1916 }; 1917 1918 static void 1919 alc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 1920 { 1921 struct alc_dmamap_arg *ctx; 1922 1923 if (error != 0) 1924 return; 1925 1926 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1927 1928 ctx = (struct alc_dmamap_arg *)arg; 1929 ctx->alc_busaddr = segs[0].ds_addr; 1930 } 1931 1932 /* 1933 * Normal and high Tx descriptors shares single Tx high address. 1934 * Four Rx descriptor/return rings and CMB shares the same Rx 1935 * high address. 1936 */ 1937 static int 1938 alc_check_boundary(struct alc_softc *sc) 1939 { 1940 bus_addr_t cmb_end, rx_ring_end, rr_ring_end, tx_ring_end; 1941 1942 rx_ring_end = sc->alc_rdata.alc_rx_ring_paddr + ALC_RX_RING_SZ; 1943 rr_ring_end = sc->alc_rdata.alc_rr_ring_paddr + ALC_RR_RING_SZ; 1944 cmb_end = sc->alc_rdata.alc_cmb_paddr + ALC_CMB_SZ; 1945 tx_ring_end = sc->alc_rdata.alc_tx_ring_paddr + ALC_TX_RING_SZ; 1946 1947 /* 4GB boundary crossing is not allowed. */ 1948 if ((ALC_ADDR_HI(rx_ring_end) != 1949 ALC_ADDR_HI(sc->alc_rdata.alc_rx_ring_paddr)) || 1950 (ALC_ADDR_HI(rr_ring_end) != 1951 ALC_ADDR_HI(sc->alc_rdata.alc_rr_ring_paddr)) || 1952 (ALC_ADDR_HI(cmb_end) != 1953 ALC_ADDR_HI(sc->alc_rdata.alc_cmb_paddr)) || 1954 (ALC_ADDR_HI(tx_ring_end) != 1955 ALC_ADDR_HI(sc->alc_rdata.alc_tx_ring_paddr))) 1956 return (EFBIG); 1957 /* 1958 * Make sure Rx return descriptor/Rx descriptor/CMB use 1959 * the same high address. 1960 */ 1961 if ((ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(rr_ring_end)) || 1962 (ALC_ADDR_HI(rx_ring_end) != ALC_ADDR_HI(cmb_end))) 1963 return (EFBIG); 1964 1965 return (0); 1966 } 1967 1968 static int 1969 alc_dma_alloc(struct alc_softc *sc) 1970 { 1971 struct alc_txdesc *txd; 1972 struct alc_rxdesc *rxd; 1973 bus_addr_t lowaddr; 1974 struct alc_dmamap_arg ctx; 1975 int error, i; 1976 1977 lowaddr = BUS_SPACE_MAXADDR; 1978 again: 1979 /* Create parent DMA tag. */ 1980 error = bus_dma_tag_create( 1981 bus_get_dma_tag(sc->alc_dev), /* parent */ 1982 1, 0, /* alignment, boundary */ 1983 lowaddr, /* lowaddr */ 1984 BUS_SPACE_MAXADDR, /* highaddr */ 1985 NULL, NULL, /* filter, filterarg */ 1986 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1987 0, /* nsegments */ 1988 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1989 0, /* flags */ 1990 NULL, NULL, /* lockfunc, lockarg */ 1991 &sc->alc_cdata.alc_parent_tag); 1992 if (error != 0) { 1993 device_printf(sc->alc_dev, 1994 "could not create parent DMA tag.\n"); 1995 goto fail; 1996 } 1997 1998 /* Create DMA tag for Tx descriptor ring. */ 1999 error = bus_dma_tag_create( 2000 sc->alc_cdata.alc_parent_tag, /* parent */ 2001 ALC_TX_RING_ALIGN, 0, /* alignment, boundary */ 2002 BUS_SPACE_MAXADDR, /* lowaddr */ 2003 BUS_SPACE_MAXADDR, /* highaddr */ 2004 NULL, NULL, /* filter, filterarg */ 2005 ALC_TX_RING_SZ, /* maxsize */ 2006 1, /* nsegments */ 2007 ALC_TX_RING_SZ, /* maxsegsize */ 2008 0, /* flags */ 2009 NULL, NULL, /* lockfunc, lockarg */ 2010 &sc->alc_cdata.alc_tx_ring_tag); 2011 if (error != 0) { 2012 device_printf(sc->alc_dev, 2013 "could not create Tx ring DMA tag.\n"); 2014 goto fail; 2015 } 2016 2017 /* Create DMA tag for Rx free descriptor ring. */ 2018 error = bus_dma_tag_create( 2019 sc->alc_cdata.alc_parent_tag, /* parent */ 2020 ALC_RX_RING_ALIGN, 0, /* alignment, boundary */ 2021 BUS_SPACE_MAXADDR, /* lowaddr */ 2022 BUS_SPACE_MAXADDR, /* highaddr */ 2023 NULL, NULL, /* filter, filterarg */ 2024 ALC_RX_RING_SZ, /* maxsize */ 2025 1, /* nsegments */ 2026 ALC_RX_RING_SZ, /* maxsegsize */ 2027 0, /* flags */ 2028 NULL, NULL, /* lockfunc, lockarg */ 2029 &sc->alc_cdata.alc_rx_ring_tag); 2030 if (error != 0) { 2031 device_printf(sc->alc_dev, 2032 "could not create Rx ring DMA tag.\n"); 2033 goto fail; 2034 } 2035 /* Create DMA tag for Rx return descriptor ring. */ 2036 error = bus_dma_tag_create( 2037 sc->alc_cdata.alc_parent_tag, /* parent */ 2038 ALC_RR_RING_ALIGN, 0, /* alignment, boundary */ 2039 BUS_SPACE_MAXADDR, /* lowaddr */ 2040 BUS_SPACE_MAXADDR, /* highaddr */ 2041 NULL, NULL, /* filter, filterarg */ 2042 ALC_RR_RING_SZ, /* maxsize */ 2043 1, /* nsegments */ 2044 ALC_RR_RING_SZ, /* maxsegsize */ 2045 0, /* flags */ 2046 NULL, NULL, /* lockfunc, lockarg */ 2047 &sc->alc_cdata.alc_rr_ring_tag); 2048 if (error != 0) { 2049 device_printf(sc->alc_dev, 2050 "could not create Rx return ring DMA tag.\n"); 2051 goto fail; 2052 } 2053 2054 /* Create DMA tag for coalescing message block. */ 2055 error = bus_dma_tag_create( 2056 sc->alc_cdata.alc_parent_tag, /* parent */ 2057 ALC_CMB_ALIGN, 0, /* alignment, boundary */ 2058 BUS_SPACE_MAXADDR, /* lowaddr */ 2059 BUS_SPACE_MAXADDR, /* highaddr */ 2060 NULL, NULL, /* filter, filterarg */ 2061 ALC_CMB_SZ, /* maxsize */ 2062 1, /* nsegments */ 2063 ALC_CMB_SZ, /* maxsegsize */ 2064 0, /* flags */ 2065 NULL, NULL, /* lockfunc, lockarg */ 2066 &sc->alc_cdata.alc_cmb_tag); 2067 if (error != 0) { 2068 device_printf(sc->alc_dev, 2069 "could not create CMB DMA tag.\n"); 2070 goto fail; 2071 } 2072 /* Create DMA tag for status message block. */ 2073 error = bus_dma_tag_create( 2074 sc->alc_cdata.alc_parent_tag, /* parent */ 2075 ALC_SMB_ALIGN, 0, /* alignment, boundary */ 2076 BUS_SPACE_MAXADDR, /* lowaddr */ 2077 BUS_SPACE_MAXADDR, /* highaddr */ 2078 NULL, NULL, /* filter, filterarg */ 2079 ALC_SMB_SZ, /* maxsize */ 2080 1, /* nsegments */ 2081 ALC_SMB_SZ, /* maxsegsize */ 2082 0, /* flags */ 2083 NULL, NULL, /* lockfunc, lockarg */ 2084 &sc->alc_cdata.alc_smb_tag); 2085 if (error != 0) { 2086 device_printf(sc->alc_dev, 2087 "could not create SMB DMA tag.\n"); 2088 goto fail; 2089 } 2090 2091 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 2092 error = bus_dmamem_alloc(sc->alc_cdata.alc_tx_ring_tag, 2093 (void **)&sc->alc_rdata.alc_tx_ring, 2094 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2095 &sc->alc_cdata.alc_tx_ring_map); 2096 if (error != 0) { 2097 device_printf(sc->alc_dev, 2098 "could not allocate DMA'able memory for Tx ring.\n"); 2099 goto fail; 2100 } 2101 ctx.alc_busaddr = 0; 2102 error = bus_dmamap_load(sc->alc_cdata.alc_tx_ring_tag, 2103 sc->alc_cdata.alc_tx_ring_map, sc->alc_rdata.alc_tx_ring, 2104 ALC_TX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2105 if (error != 0 || ctx.alc_busaddr == 0) { 2106 device_printf(sc->alc_dev, 2107 "could not load DMA'able memory for Tx ring.\n"); 2108 goto fail; 2109 } 2110 sc->alc_rdata.alc_tx_ring_paddr = ctx.alc_busaddr; 2111 2112 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 2113 error = bus_dmamem_alloc(sc->alc_cdata.alc_rx_ring_tag, 2114 (void **)&sc->alc_rdata.alc_rx_ring, 2115 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2116 &sc->alc_cdata.alc_rx_ring_map); 2117 if (error != 0) { 2118 device_printf(sc->alc_dev, 2119 "could not allocate DMA'able memory for Rx ring.\n"); 2120 goto fail; 2121 } 2122 ctx.alc_busaddr = 0; 2123 error = bus_dmamap_load(sc->alc_cdata.alc_rx_ring_tag, 2124 sc->alc_cdata.alc_rx_ring_map, sc->alc_rdata.alc_rx_ring, 2125 ALC_RX_RING_SZ, alc_dmamap_cb, &ctx, 0); 2126 if (error != 0 || ctx.alc_busaddr == 0) { 2127 device_printf(sc->alc_dev, 2128 "could not load DMA'able memory for Rx ring.\n"); 2129 goto fail; 2130 } 2131 sc->alc_rdata.alc_rx_ring_paddr = ctx.alc_busaddr; 2132 2133 /* Allocate DMA'able memory and load the DMA map for Rx return ring. */ 2134 error = bus_dmamem_alloc(sc->alc_cdata.alc_rr_ring_tag, 2135 (void **)&sc->alc_rdata.alc_rr_ring, 2136 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2137 &sc->alc_cdata.alc_rr_ring_map); 2138 if (error != 0) { 2139 device_printf(sc->alc_dev, 2140 "could not allocate DMA'able memory for Rx return ring.\n"); 2141 goto fail; 2142 } 2143 ctx.alc_busaddr = 0; 2144 error = bus_dmamap_load(sc->alc_cdata.alc_rr_ring_tag, 2145 sc->alc_cdata.alc_rr_ring_map, sc->alc_rdata.alc_rr_ring, 2146 ALC_RR_RING_SZ, alc_dmamap_cb, &ctx, 0); 2147 if (error != 0 || ctx.alc_busaddr == 0) { 2148 device_printf(sc->alc_dev, 2149 "could not load DMA'able memory for Tx ring.\n"); 2150 goto fail; 2151 } 2152 sc->alc_rdata.alc_rr_ring_paddr = ctx.alc_busaddr; 2153 2154 /* Allocate DMA'able memory and load the DMA map for CMB. */ 2155 error = bus_dmamem_alloc(sc->alc_cdata.alc_cmb_tag, 2156 (void **)&sc->alc_rdata.alc_cmb, 2157 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2158 &sc->alc_cdata.alc_cmb_map); 2159 if (error != 0) { 2160 device_printf(sc->alc_dev, 2161 "could not allocate DMA'able memory for CMB.\n"); 2162 goto fail; 2163 } 2164 ctx.alc_busaddr = 0; 2165 error = bus_dmamap_load(sc->alc_cdata.alc_cmb_tag, 2166 sc->alc_cdata.alc_cmb_map, sc->alc_rdata.alc_cmb, 2167 ALC_CMB_SZ, alc_dmamap_cb, &ctx, 0); 2168 if (error != 0 || ctx.alc_busaddr == 0) { 2169 device_printf(sc->alc_dev, 2170 "could not load DMA'able memory for CMB.\n"); 2171 goto fail; 2172 } 2173 sc->alc_rdata.alc_cmb_paddr = ctx.alc_busaddr; 2174 2175 /* Allocate DMA'able memory and load the DMA map for SMB. */ 2176 error = bus_dmamem_alloc(sc->alc_cdata.alc_smb_tag, 2177 (void **)&sc->alc_rdata.alc_smb, 2178 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 2179 &sc->alc_cdata.alc_smb_map); 2180 if (error != 0) { 2181 device_printf(sc->alc_dev, 2182 "could not allocate DMA'able memory for SMB.\n"); 2183 goto fail; 2184 } 2185 ctx.alc_busaddr = 0; 2186 error = bus_dmamap_load(sc->alc_cdata.alc_smb_tag, 2187 sc->alc_cdata.alc_smb_map, sc->alc_rdata.alc_smb, 2188 ALC_SMB_SZ, alc_dmamap_cb, &ctx, 0); 2189 if (error != 0 || ctx.alc_busaddr == 0) { 2190 device_printf(sc->alc_dev, 2191 "could not load DMA'able memory for CMB.\n"); 2192 goto fail; 2193 } 2194 sc->alc_rdata.alc_smb_paddr = ctx.alc_busaddr; 2195 2196 /* Make sure we've not crossed 4GB boundary. */ 2197 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 2198 (error = alc_check_boundary(sc)) != 0) { 2199 device_printf(sc->alc_dev, "4GB boundary crossed, " 2200 "switching to 32bit DMA addressing mode.\n"); 2201 alc_dma_free(sc); 2202 /* 2203 * Limit max allowable DMA address space to 32bit 2204 * and try again. 2205 */ 2206 lowaddr = BUS_SPACE_MAXADDR_32BIT; 2207 goto again; 2208 } 2209 2210 /* 2211 * Create Tx buffer parent tag. 2212 * AR81[3567]x allows 64bit DMA addressing of Tx/Rx buffers 2213 * so it needs separate parent DMA tag as parent DMA address 2214 * space could be restricted to be within 32bit address space 2215 * by 4GB boundary crossing. 2216 */ 2217 error = bus_dma_tag_create( 2218 bus_get_dma_tag(sc->alc_dev), /* parent */ 2219 1, 0, /* alignment, boundary */ 2220 BUS_SPACE_MAXADDR, /* lowaddr */ 2221 BUS_SPACE_MAXADDR, /* highaddr */ 2222 NULL, NULL, /* filter, filterarg */ 2223 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 2224 0, /* nsegments */ 2225 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 2226 0, /* flags */ 2227 NULL, NULL, /* lockfunc, lockarg */ 2228 &sc->alc_cdata.alc_buffer_tag); 2229 if (error != 0) { 2230 device_printf(sc->alc_dev, 2231 "could not create parent buffer DMA tag.\n"); 2232 goto fail; 2233 } 2234 2235 /* Create DMA tag for Tx buffers. */ 2236 error = bus_dma_tag_create( 2237 sc->alc_cdata.alc_buffer_tag, /* parent */ 2238 1, 0, /* alignment, boundary */ 2239 BUS_SPACE_MAXADDR, /* lowaddr */ 2240 BUS_SPACE_MAXADDR, /* highaddr */ 2241 NULL, NULL, /* filter, filterarg */ 2242 ALC_TSO_MAXSIZE, /* maxsize */ 2243 ALC_MAXTXSEGS, /* nsegments */ 2244 ALC_TSO_MAXSEGSIZE, /* maxsegsize */ 2245 0, /* flags */ 2246 NULL, NULL, /* lockfunc, lockarg */ 2247 &sc->alc_cdata.alc_tx_tag); 2248 if (error != 0) { 2249 device_printf(sc->alc_dev, "could not create Tx DMA tag.\n"); 2250 goto fail; 2251 } 2252 2253 /* Create DMA tag for Rx buffers. */ 2254 error = bus_dma_tag_create( 2255 sc->alc_cdata.alc_buffer_tag, /* parent */ 2256 ALC_RX_BUF_ALIGN, 0, /* alignment, boundary */ 2257 BUS_SPACE_MAXADDR, /* lowaddr */ 2258 BUS_SPACE_MAXADDR, /* highaddr */ 2259 NULL, NULL, /* filter, filterarg */ 2260 MCLBYTES, /* maxsize */ 2261 1, /* nsegments */ 2262 MCLBYTES, /* maxsegsize */ 2263 0, /* flags */ 2264 NULL, NULL, /* lockfunc, lockarg */ 2265 &sc->alc_cdata.alc_rx_tag); 2266 if (error != 0) { 2267 device_printf(sc->alc_dev, "could not create Rx DMA tag.\n"); 2268 goto fail; 2269 } 2270 /* Create DMA maps for Tx buffers. */ 2271 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2272 txd = &sc->alc_cdata.alc_txdesc[i]; 2273 txd->tx_m = NULL; 2274 txd->tx_dmamap = NULL; 2275 error = bus_dmamap_create(sc->alc_cdata.alc_tx_tag, 0, 2276 &txd->tx_dmamap); 2277 if (error != 0) { 2278 device_printf(sc->alc_dev, 2279 "could not create Tx dmamap.\n"); 2280 goto fail; 2281 } 2282 } 2283 /* Create DMA maps for Rx buffers. */ 2284 if ((error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2285 &sc->alc_cdata.alc_rx_sparemap)) != 0) { 2286 device_printf(sc->alc_dev, 2287 "could not create spare Rx dmamap.\n"); 2288 goto fail; 2289 } 2290 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2291 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2292 rxd->rx_m = NULL; 2293 rxd->rx_dmamap = NULL; 2294 error = bus_dmamap_create(sc->alc_cdata.alc_rx_tag, 0, 2295 &rxd->rx_dmamap); 2296 if (error != 0) { 2297 device_printf(sc->alc_dev, 2298 "could not create Rx dmamap.\n"); 2299 goto fail; 2300 } 2301 } 2302 2303 fail: 2304 return (error); 2305 } 2306 2307 static void 2308 alc_dma_free(struct alc_softc *sc) 2309 { 2310 struct alc_txdesc *txd; 2311 struct alc_rxdesc *rxd; 2312 int i; 2313 2314 /* Tx buffers. */ 2315 if (sc->alc_cdata.alc_tx_tag != NULL) { 2316 for (i = 0; i < ALC_TX_RING_CNT; i++) { 2317 txd = &sc->alc_cdata.alc_txdesc[i]; 2318 if (txd->tx_dmamap != NULL) { 2319 bus_dmamap_destroy(sc->alc_cdata.alc_tx_tag, 2320 txd->tx_dmamap); 2321 txd->tx_dmamap = NULL; 2322 } 2323 } 2324 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_tag); 2325 sc->alc_cdata.alc_tx_tag = NULL; 2326 } 2327 /* Rx buffers */ 2328 if (sc->alc_cdata.alc_rx_tag != NULL) { 2329 for (i = 0; i < ALC_RX_RING_CNT; i++) { 2330 rxd = &sc->alc_cdata.alc_rxdesc[i]; 2331 if (rxd->rx_dmamap != NULL) { 2332 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2333 rxd->rx_dmamap); 2334 rxd->rx_dmamap = NULL; 2335 } 2336 } 2337 if (sc->alc_cdata.alc_rx_sparemap != NULL) { 2338 bus_dmamap_destroy(sc->alc_cdata.alc_rx_tag, 2339 sc->alc_cdata.alc_rx_sparemap); 2340 sc->alc_cdata.alc_rx_sparemap = NULL; 2341 } 2342 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_tag); 2343 sc->alc_cdata.alc_rx_tag = NULL; 2344 } 2345 /* Tx descriptor ring. */ 2346 if (sc->alc_cdata.alc_tx_ring_tag != NULL) { 2347 if (sc->alc_rdata.alc_tx_ring_paddr != 0) 2348 bus_dmamap_unload(sc->alc_cdata.alc_tx_ring_tag, 2349 sc->alc_cdata.alc_tx_ring_map); 2350 if (sc->alc_rdata.alc_tx_ring != NULL) 2351 bus_dmamem_free(sc->alc_cdata.alc_tx_ring_tag, 2352 sc->alc_rdata.alc_tx_ring, 2353 sc->alc_cdata.alc_tx_ring_map); 2354 sc->alc_rdata.alc_tx_ring_paddr = 0; 2355 sc->alc_rdata.alc_tx_ring = NULL; 2356 bus_dma_tag_destroy(sc->alc_cdata.alc_tx_ring_tag); 2357 sc->alc_cdata.alc_tx_ring_tag = NULL; 2358 } 2359 /* Rx ring. */ 2360 if (sc->alc_cdata.alc_rx_ring_tag != NULL) { 2361 if (sc->alc_rdata.alc_rx_ring_paddr != 0) 2362 bus_dmamap_unload(sc->alc_cdata.alc_rx_ring_tag, 2363 sc->alc_cdata.alc_rx_ring_map); 2364 if (sc->alc_rdata.alc_rx_ring != NULL) 2365 bus_dmamem_free(sc->alc_cdata.alc_rx_ring_tag, 2366 sc->alc_rdata.alc_rx_ring, 2367 sc->alc_cdata.alc_rx_ring_map); 2368 sc->alc_rdata.alc_rx_ring_paddr = 0; 2369 sc->alc_rdata.alc_rx_ring = NULL; 2370 bus_dma_tag_destroy(sc->alc_cdata.alc_rx_ring_tag); 2371 sc->alc_cdata.alc_rx_ring_tag = NULL; 2372 } 2373 /* Rx return ring. */ 2374 if (sc->alc_cdata.alc_rr_ring_tag != NULL) { 2375 if (sc->alc_rdata.alc_rr_ring_paddr != 0) 2376 bus_dmamap_unload(sc->alc_cdata.alc_rr_ring_tag, 2377 sc->alc_cdata.alc_rr_ring_map); 2378 if (sc->alc_rdata.alc_rr_ring != NULL) 2379 bus_dmamem_free(sc->alc_cdata.alc_rr_ring_tag, 2380 sc->alc_rdata.alc_rr_ring, 2381 sc->alc_cdata.alc_rr_ring_map); 2382 sc->alc_rdata.alc_rr_ring_paddr = 0; 2383 sc->alc_rdata.alc_rr_ring = NULL; 2384 bus_dma_tag_destroy(sc->alc_cdata.alc_rr_ring_tag); 2385 sc->alc_cdata.alc_rr_ring_tag = NULL; 2386 } 2387 /* CMB block */ 2388 if (sc->alc_cdata.alc_cmb_tag != NULL) { 2389 if (sc->alc_rdata.alc_cmb_paddr != 0) 2390 bus_dmamap_unload(sc->alc_cdata.alc_cmb_tag, 2391 sc->alc_cdata.alc_cmb_map); 2392 if (sc->alc_rdata.alc_cmb != NULL) 2393 bus_dmamem_free(sc->alc_cdata.alc_cmb_tag, 2394 sc->alc_rdata.alc_cmb, 2395 sc->alc_cdata.alc_cmb_map); 2396 sc->alc_rdata.alc_cmb_paddr = 0; 2397 sc->alc_rdata.alc_cmb = NULL; 2398 bus_dma_tag_destroy(sc->alc_cdata.alc_cmb_tag); 2399 sc->alc_cdata.alc_cmb_tag = NULL; 2400 } 2401 /* SMB block */ 2402 if (sc->alc_cdata.alc_smb_tag != NULL) { 2403 if (sc->alc_rdata.alc_smb_paddr != 0) 2404 bus_dmamap_unload(sc->alc_cdata.alc_smb_tag, 2405 sc->alc_cdata.alc_smb_map); 2406 if (sc->alc_rdata.alc_smb != NULL) 2407 bus_dmamem_free(sc->alc_cdata.alc_smb_tag, 2408 sc->alc_rdata.alc_smb, 2409 sc->alc_cdata.alc_smb_map); 2410 sc->alc_rdata.alc_smb_paddr = 0; 2411 sc->alc_rdata.alc_smb = NULL; 2412 bus_dma_tag_destroy(sc->alc_cdata.alc_smb_tag); 2413 sc->alc_cdata.alc_smb_tag = NULL; 2414 } 2415 if (sc->alc_cdata.alc_buffer_tag != NULL) { 2416 bus_dma_tag_destroy(sc->alc_cdata.alc_buffer_tag); 2417 sc->alc_cdata.alc_buffer_tag = NULL; 2418 } 2419 if (sc->alc_cdata.alc_parent_tag != NULL) { 2420 bus_dma_tag_destroy(sc->alc_cdata.alc_parent_tag); 2421 sc->alc_cdata.alc_parent_tag = NULL; 2422 } 2423 } 2424 2425 static int 2426 alc_shutdown(device_t dev) 2427 { 2428 2429 return (alc_suspend(dev)); 2430 } 2431 2432 /* 2433 * Note, this driver resets the link speed to 10/100Mbps by 2434 * restarting auto-negotiation in suspend/shutdown phase but we 2435 * don't know whether that auto-negotiation would succeed or not 2436 * as driver has no control after powering off/suspend operation. 2437 * If the renegotiation fail WOL may not work. Running at 1Gbps 2438 * will draw more power than 375mA at 3.3V which is specified in 2439 * PCI specification and that would result in complete 2440 * shutdowning power to ethernet controller. 2441 * 2442 * TODO 2443 * Save current negotiated media speed/duplex/flow-control to 2444 * softc and restore the same link again after resuming. PHY 2445 * handling such as power down/resetting to 100Mbps may be better 2446 * handled in suspend method in phy driver. 2447 */ 2448 static void 2449 alc_setlinkspeed(struct alc_softc *sc) 2450 { 2451 struct mii_data *mii; 2452 int aneg, i; 2453 2454 mii = device_get_softc(sc->alc_miibus); 2455 mii_pollstat(mii); 2456 aneg = 0; 2457 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2458 (IFM_ACTIVE | IFM_AVALID)) { 2459 switch IFM_SUBTYPE(mii->mii_media_active) { 2460 case IFM_10_T: 2461 case IFM_100_TX: 2462 return; 2463 case IFM_1000_T: 2464 aneg++; 2465 break; 2466 default: 2467 break; 2468 } 2469 } 2470 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, MII_100T2CR, 0); 2471 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2472 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 2473 alc_miibus_writereg(sc->alc_dev, sc->alc_phyaddr, 2474 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 2475 DELAY(1000); 2476 if (aneg != 0) { 2477 /* 2478 * Poll link state until alc(4) get a 10/100Mbps link. 2479 */ 2480 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 2481 mii_pollstat(mii); 2482 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 2483 == (IFM_ACTIVE | IFM_AVALID)) { 2484 switch (IFM_SUBTYPE( 2485 mii->mii_media_active)) { 2486 case IFM_10_T: 2487 case IFM_100_TX: 2488 alc_mac_config(sc); 2489 return; 2490 default: 2491 break; 2492 } 2493 } 2494 ALC_UNLOCK(sc); 2495 pause("alclnk", hz); 2496 ALC_LOCK(sc); 2497 } 2498 if (i == MII_ANEGTICKS_GIGE) 2499 device_printf(sc->alc_dev, 2500 "establishing a link failed, WOL may not work!"); 2501 } 2502 /* 2503 * No link, force MAC to have 100Mbps, full-duplex link. 2504 * This is the last resort and may/may not work. 2505 */ 2506 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 2507 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 2508 alc_mac_config(sc); 2509 } 2510 2511 static void 2512 alc_setwol(struct alc_softc *sc) 2513 { 2514 2515 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2516 alc_setwol_816x(sc); 2517 else 2518 alc_setwol_813x(sc); 2519 } 2520 2521 static void 2522 alc_setwol_813x(struct alc_softc *sc) 2523 { 2524 struct ifnet *ifp; 2525 uint32_t reg, pmcs; 2526 uint16_t pmstat; 2527 2528 ALC_LOCK_ASSERT(sc); 2529 2530 alc_disable_l0s_l1(sc); 2531 ifp = sc->alc_ifp; 2532 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2533 /* Disable WOL. */ 2534 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2535 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2536 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2537 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2538 /* Force PHY power down. */ 2539 alc_phy_down(sc); 2540 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2541 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2542 return; 2543 } 2544 2545 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2546 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2547 alc_setlinkspeed(sc); 2548 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2549 CSR_READ_4(sc, ALC_MASTER_CFG) & ~MASTER_CLK_SEL_DIS); 2550 } 2551 2552 pmcs = 0; 2553 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2554 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2555 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2556 reg = CSR_READ_4(sc, ALC_MAC_CFG); 2557 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2558 MAC_CFG_BCAST); 2559 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2560 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2561 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2562 reg |= MAC_CFG_RX_ENB; 2563 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 2564 2565 reg = CSR_READ_4(sc, ALC_PCIE_PHYMISC); 2566 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 2567 CSR_WRITE_4(sc, ALC_PCIE_PHYMISC, reg); 2568 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 2569 /* WOL disabled, PHY power down. */ 2570 alc_phy_down(sc); 2571 CSR_WRITE_4(sc, ALC_MASTER_CFG, 2572 CSR_READ_4(sc, ALC_MASTER_CFG) | MASTER_CLK_SEL_DIS); 2573 } 2574 /* Request PME. */ 2575 pmstat = pci_read_config(sc->alc_dev, 2576 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2577 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2578 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2579 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2580 pci_write_config(sc->alc_dev, 2581 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2582 } 2583 2584 static void 2585 alc_setwol_816x(struct alc_softc *sc) 2586 { 2587 struct ifnet *ifp; 2588 uint32_t gphy, mac, master, pmcs, reg; 2589 uint16_t pmstat; 2590 2591 ALC_LOCK_ASSERT(sc); 2592 2593 ifp = sc->alc_ifp; 2594 master = CSR_READ_4(sc, ALC_MASTER_CFG); 2595 master &= ~MASTER_CLK_SEL_DIS; 2596 gphy = CSR_READ_4(sc, ALC_GPHY_CFG); 2597 gphy &= ~(GPHY_CFG_EXT_RESET | GPHY_CFG_LED_MODE | GPHY_CFG_100AB_ENB | 2598 GPHY_CFG_PHY_PLL_ON); 2599 gphy |= GPHY_CFG_HIB_EN | GPHY_CFG_HIB_PULSE | GPHY_CFG_SEL_ANA_RESET; 2600 if ((sc->alc_flags & ALC_FLAG_PM) == 0) { 2601 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 2602 gphy |= GPHY_CFG_PHY_IDDQ | GPHY_CFG_PWDOWN_HW; 2603 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2604 } else { 2605 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 2606 gphy |= GPHY_CFG_EXT_RESET; 2607 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 2608 alc_setlinkspeed(sc); 2609 } 2610 pmcs = 0; 2611 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 2612 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 2613 CSR_WRITE_4(sc, ALC_WOL_CFG, pmcs); 2614 mac = CSR_READ_4(sc, ALC_MAC_CFG); 2615 mac &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 2616 MAC_CFG_BCAST); 2617 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 2618 mac |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 2619 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2620 mac |= MAC_CFG_RX_ENB; 2621 alc_miiext_writereg(sc, MII_EXT_ANEG, MII_EXT_ANEG_S3DIG10, 2622 ANEG_S3DIG10_SL); 2623 } 2624 2625 /* Enable OSC. */ 2626 reg = CSR_READ_4(sc, ALC_MISC); 2627 reg &= ~MISC_INTNLOSC_OPEN; 2628 CSR_WRITE_4(sc, ALC_MISC, reg); 2629 reg |= MISC_INTNLOSC_OPEN; 2630 CSR_WRITE_4(sc, ALC_MISC, reg); 2631 CSR_WRITE_4(sc, ALC_MASTER_CFG, master); 2632 CSR_WRITE_4(sc, ALC_MAC_CFG, mac); 2633 CSR_WRITE_4(sc, ALC_GPHY_CFG, gphy); 2634 reg = CSR_READ_4(sc, ALC_PDLL_TRNS1); 2635 reg |= PDLL_TRNS1_D3PLLOFF_ENB; 2636 CSR_WRITE_4(sc, ALC_PDLL_TRNS1, reg); 2637 2638 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2639 /* Request PME. */ 2640 pmstat = pci_read_config(sc->alc_dev, 2641 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2642 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 2643 if ((ifp->if_capenable & IFCAP_WOL) != 0) 2644 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 2645 pci_write_config(sc->alc_dev, 2646 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2647 } 2648 } 2649 2650 static int 2651 alc_suspend(device_t dev) 2652 { 2653 struct alc_softc *sc; 2654 2655 sc = device_get_softc(dev); 2656 2657 ALC_LOCK(sc); 2658 alc_stop(sc); 2659 alc_setwol(sc); 2660 ALC_UNLOCK(sc); 2661 2662 return (0); 2663 } 2664 2665 static int 2666 alc_resume(device_t dev) 2667 { 2668 struct alc_softc *sc; 2669 struct ifnet *ifp; 2670 uint16_t pmstat; 2671 2672 sc = device_get_softc(dev); 2673 2674 ALC_LOCK(sc); 2675 if ((sc->alc_flags & ALC_FLAG_PM) != 0) { 2676 /* Disable PME and clear PME status. */ 2677 pmstat = pci_read_config(sc->alc_dev, 2678 sc->alc_pmcap + PCIR_POWER_STATUS, 2); 2679 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 2680 pmstat &= ~PCIM_PSTAT_PMEENABLE; 2681 pci_write_config(sc->alc_dev, 2682 sc->alc_pmcap + PCIR_POWER_STATUS, pmstat, 2); 2683 } 2684 } 2685 /* Reset PHY. */ 2686 alc_phy_reset(sc); 2687 ifp = sc->alc_ifp; 2688 if ((ifp->if_flags & IFF_UP) != 0) { 2689 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2690 alc_init_locked(sc); 2691 } 2692 ALC_UNLOCK(sc); 2693 2694 return (0); 2695 } 2696 2697 static int 2698 alc_encap(struct alc_softc *sc, struct mbuf **m_head) 2699 { 2700 struct alc_txdesc *txd, *txd_last; 2701 struct tx_desc *desc; 2702 struct mbuf *m; 2703 struct ip *ip; 2704 struct tcphdr *tcp; 2705 bus_dma_segment_t txsegs[ALC_MAXTXSEGS]; 2706 bus_dmamap_t map; 2707 uint32_t cflags, hdrlen, ip_off, poff, vtag; 2708 int error, idx, nsegs, prod; 2709 2710 ALC_LOCK_ASSERT(sc); 2711 2712 M_ASSERTPKTHDR((*m_head)); 2713 2714 m = *m_head; 2715 ip = NULL; 2716 tcp = NULL; 2717 ip_off = poff = 0; 2718 if ((m->m_pkthdr.csum_flags & (ALC_CSUM_FEATURES | CSUM_TSO)) != 0) { 2719 /* 2720 * AR81[3567]x requires offset of TCP/UDP header in its 2721 * Tx descriptor to perform Tx checksum offloading. TSO 2722 * also requires TCP header offset and modification of 2723 * IP/TCP header. This kind of operation takes many CPU 2724 * cycles on FreeBSD so fast host CPU is required to get 2725 * smooth TSO performance. 2726 */ 2727 struct ether_header *eh; 2728 2729 if (M_WRITABLE(m) == 0) { 2730 /* Get a writable copy. */ 2731 m = m_dup(*m_head, M_NOWAIT); 2732 /* Release original mbufs. */ 2733 m_freem(*m_head); 2734 if (m == NULL) { 2735 *m_head = NULL; 2736 return (ENOBUFS); 2737 } 2738 *m_head = m; 2739 } 2740 2741 ip_off = sizeof(struct ether_header); 2742 m = m_pullup(m, ip_off); 2743 if (m == NULL) { 2744 *m_head = NULL; 2745 return (ENOBUFS); 2746 } 2747 eh = mtod(m, struct ether_header *); 2748 /* 2749 * Check if hardware VLAN insertion is off. 2750 * Additional check for LLC/SNAP frame? 2751 */ 2752 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 2753 ip_off = sizeof(struct ether_vlan_header); 2754 m = m_pullup(m, ip_off); 2755 if (m == NULL) { 2756 *m_head = NULL; 2757 return (ENOBUFS); 2758 } 2759 } 2760 m = m_pullup(m, ip_off + sizeof(struct ip)); 2761 if (m == NULL) { 2762 *m_head = NULL; 2763 return (ENOBUFS); 2764 } 2765 ip = (struct ip *)(mtod(m, char *) + ip_off); 2766 poff = ip_off + (ip->ip_hl << 2); 2767 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2768 m = m_pullup(m, poff + sizeof(struct tcphdr)); 2769 if (m == NULL) { 2770 *m_head = NULL; 2771 return (ENOBUFS); 2772 } 2773 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2774 m = m_pullup(m, poff + (tcp->th_off << 2)); 2775 if (m == NULL) { 2776 *m_head = NULL; 2777 return (ENOBUFS); 2778 } 2779 /* 2780 * Due to strict adherence of Microsoft NDIS 2781 * Large Send specification, hardware expects 2782 * a pseudo TCP checksum inserted by upper 2783 * stack. Unfortunately the pseudo TCP 2784 * checksum that NDIS refers to does not include 2785 * TCP payload length so driver should recompute 2786 * the pseudo checksum here. Hopefully this 2787 * wouldn't be much burden on modern CPUs. 2788 * 2789 * Reset IP checksum and recompute TCP pseudo 2790 * checksum as NDIS specification said. 2791 */ 2792 ip = (struct ip *)(mtod(m, char *) + ip_off); 2793 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 2794 ip->ip_sum = 0; 2795 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 2796 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 2797 } 2798 *m_head = m; 2799 } 2800 2801 prod = sc->alc_cdata.alc_tx_prod; 2802 txd = &sc->alc_cdata.alc_txdesc[prod]; 2803 txd_last = txd; 2804 map = txd->tx_dmamap; 2805 2806 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2807 *m_head, txsegs, &nsegs, 0); 2808 if (error == EFBIG) { 2809 m = m_collapse(*m_head, M_NOWAIT, ALC_MAXTXSEGS); 2810 if (m == NULL) { 2811 m_freem(*m_head); 2812 *m_head = NULL; 2813 return (ENOMEM); 2814 } 2815 *m_head = m; 2816 error = bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_tx_tag, map, 2817 *m_head, txsegs, &nsegs, 0); 2818 if (error != 0) { 2819 m_freem(*m_head); 2820 *m_head = NULL; 2821 return (error); 2822 } 2823 } else if (error != 0) 2824 return (error); 2825 if (nsegs == 0) { 2826 m_freem(*m_head); 2827 *m_head = NULL; 2828 return (EIO); 2829 } 2830 2831 /* Check descriptor overrun. */ 2832 if (sc->alc_cdata.alc_tx_cnt + nsegs >= ALC_TX_RING_CNT - 3) { 2833 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, map); 2834 return (ENOBUFS); 2835 } 2836 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, map, BUS_DMASYNC_PREWRITE); 2837 2838 m = *m_head; 2839 cflags = TD_ETHERNET; 2840 vtag = 0; 2841 desc = NULL; 2842 idx = 0; 2843 /* Configure VLAN hardware tag insertion. */ 2844 if ((m->m_flags & M_VLANTAG) != 0) { 2845 vtag = htons(m->m_pkthdr.ether_vtag); 2846 vtag = (vtag << TD_VLAN_SHIFT) & TD_VLAN_MASK; 2847 cflags |= TD_INS_VLAN_TAG; 2848 } 2849 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2850 /* Request TSO and set MSS. */ 2851 cflags |= TD_TSO | TD_TSO_DESCV1; 2852 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << TD_MSS_SHIFT) & 2853 TD_MSS_MASK; 2854 /* Set TCP header offset. */ 2855 cflags |= (poff << TD_TCPHDR_OFFSET_SHIFT) & 2856 TD_TCPHDR_OFFSET_MASK; 2857 /* 2858 * AR81[3567]x requires the first buffer should 2859 * only hold IP/TCP header data. Payload should 2860 * be handled in other descriptors. 2861 */ 2862 hdrlen = poff + (tcp->th_off << 2); 2863 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2864 desc->len = htole32(TX_BYTES(hdrlen | vtag)); 2865 desc->flags = htole32(cflags); 2866 desc->addr = htole64(txsegs[0].ds_addr); 2867 sc->alc_cdata.alc_tx_cnt++; 2868 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2869 if (m->m_len - hdrlen > 0) { 2870 /* Handle remaining payload of the first fragment. */ 2871 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2872 desc->len = htole32(TX_BYTES((m->m_len - hdrlen) | 2873 vtag)); 2874 desc->flags = htole32(cflags); 2875 desc->addr = htole64(txsegs[0].ds_addr + hdrlen); 2876 sc->alc_cdata.alc_tx_cnt++; 2877 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2878 } 2879 /* Handle remaining fragments. */ 2880 idx = 1; 2881 } else if ((m->m_pkthdr.csum_flags & ALC_CSUM_FEATURES) != 0) { 2882 /* Configure Tx checksum offload. */ 2883 #ifdef ALC_USE_CUSTOM_CSUM 2884 cflags |= TD_CUSTOM_CSUM; 2885 /* Set checksum start offset. */ 2886 cflags |= ((poff >> 1) << TD_PLOAD_OFFSET_SHIFT) & 2887 TD_PLOAD_OFFSET_MASK; 2888 /* Set checksum insertion position of TCP/UDP. */ 2889 cflags |= (((poff + m->m_pkthdr.csum_data) >> 1) << 2890 TD_CUSTOM_CSUM_OFFSET_SHIFT) & TD_CUSTOM_CSUM_OFFSET_MASK; 2891 #else 2892 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 2893 cflags |= TD_IPCSUM; 2894 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 2895 cflags |= TD_TCPCSUM; 2896 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 2897 cflags |= TD_UDPCSUM; 2898 /* Set TCP/UDP header offset. */ 2899 cflags |= (poff << TD_L4HDR_OFFSET_SHIFT) & 2900 TD_L4HDR_OFFSET_MASK; 2901 #endif 2902 } 2903 for (; idx < nsegs; idx++) { 2904 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2905 desc->len = htole32(TX_BYTES(txsegs[idx].ds_len) | vtag); 2906 desc->flags = htole32(cflags); 2907 desc->addr = htole64(txsegs[idx].ds_addr); 2908 sc->alc_cdata.alc_tx_cnt++; 2909 ALC_DESC_INC(prod, ALC_TX_RING_CNT); 2910 } 2911 /* Update producer index. */ 2912 sc->alc_cdata.alc_tx_prod = prod; 2913 2914 /* Finally set EOP on the last descriptor. */ 2915 prod = (prod + ALC_TX_RING_CNT - 1) % ALC_TX_RING_CNT; 2916 desc = &sc->alc_rdata.alc_tx_ring[prod]; 2917 desc->flags |= htole32(TD_EOP); 2918 2919 /* Swap dmamap of the first and the last. */ 2920 txd = &sc->alc_cdata.alc_txdesc[prod]; 2921 map = txd_last->tx_dmamap; 2922 txd_last->tx_dmamap = txd->tx_dmamap; 2923 txd->tx_dmamap = map; 2924 txd->tx_m = m; 2925 2926 return (0); 2927 } 2928 2929 static void 2930 alc_start(struct ifnet *ifp) 2931 { 2932 struct alc_softc *sc; 2933 2934 sc = ifp->if_softc; 2935 ALC_LOCK(sc); 2936 alc_start_locked(ifp); 2937 ALC_UNLOCK(sc); 2938 } 2939 2940 static void 2941 alc_start_locked(struct ifnet *ifp) 2942 { 2943 struct alc_softc *sc; 2944 struct mbuf *m_head; 2945 int enq; 2946 2947 sc = ifp->if_softc; 2948 2949 ALC_LOCK_ASSERT(sc); 2950 2951 /* Reclaim transmitted frames. */ 2952 if (sc->alc_cdata.alc_tx_cnt >= ALC_TX_DESC_HIWAT) 2953 alc_txeof(sc); 2954 2955 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2956 IFF_DRV_RUNNING || (sc->alc_flags & ALC_FLAG_LINK) == 0) 2957 return; 2958 2959 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 2960 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2961 if (m_head == NULL) 2962 break; 2963 /* 2964 * Pack the data into the transmit ring. If we 2965 * don't have room, set the OACTIVE flag and wait 2966 * for the NIC to drain the ring. 2967 */ 2968 if (alc_encap(sc, &m_head)) { 2969 if (m_head == NULL) 2970 break; 2971 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2972 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2973 break; 2974 } 2975 2976 enq++; 2977 /* 2978 * If there's a BPF listener, bounce a copy of this frame 2979 * to him. 2980 */ 2981 ETHER_BPF_MTAP(ifp, m_head); 2982 } 2983 2984 if (enq > 0) 2985 alc_start_tx(sc); 2986 } 2987 2988 static void 2989 alc_start_tx(struct alc_softc *sc) 2990 { 2991 2992 /* Sync descriptors. */ 2993 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 2994 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 2995 /* Kick. Assume we're using normal Tx priority queue. */ 2996 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 2997 CSR_WRITE_2(sc, ALC_MBOX_TD_PRI0_PROD_IDX, 2998 (uint16_t)sc->alc_cdata.alc_tx_prod); 2999 else 3000 CSR_WRITE_4(sc, ALC_MBOX_TD_PROD_IDX, 3001 (sc->alc_cdata.alc_tx_prod << 3002 MBOX_TD_PROD_LO_IDX_SHIFT) & 3003 MBOX_TD_PROD_LO_IDX_MASK); 3004 /* Set a timeout in case the chip goes out to lunch. */ 3005 sc->alc_watchdog_timer = ALC_TX_TIMEOUT; 3006 } 3007 3008 static void 3009 alc_watchdog(struct alc_softc *sc) 3010 { 3011 struct ifnet *ifp; 3012 3013 ALC_LOCK_ASSERT(sc); 3014 3015 if (sc->alc_watchdog_timer == 0 || --sc->alc_watchdog_timer) 3016 return; 3017 3018 ifp = sc->alc_ifp; 3019 if ((sc->alc_flags & ALC_FLAG_LINK) == 0) { 3020 if_printf(sc->alc_ifp, "watchdog timeout (lost link)\n"); 3021 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3022 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3023 alc_init_locked(sc); 3024 return; 3025 } 3026 if_printf(sc->alc_ifp, "watchdog timeout -- resetting\n"); 3027 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 3028 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3029 alc_init_locked(sc); 3030 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3031 alc_start_locked(ifp); 3032 } 3033 3034 static int 3035 alc_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 3036 { 3037 struct alc_softc *sc; 3038 struct ifreq *ifr; 3039 struct mii_data *mii; 3040 int error, mask; 3041 3042 sc = ifp->if_softc; 3043 ifr = (struct ifreq *)data; 3044 error = 0; 3045 switch (cmd) { 3046 case SIOCSIFMTU: 3047 if (ifr->ifr_mtu < ETHERMIN || 3048 ifr->ifr_mtu > (sc->alc_ident->max_framelen - 3049 sizeof(struct ether_vlan_header) - ETHER_CRC_LEN) || 3050 ((sc->alc_flags & ALC_FLAG_JUMBO) == 0 && 3051 ifr->ifr_mtu > ETHERMTU)) 3052 error = EINVAL; 3053 else if (ifp->if_mtu != ifr->ifr_mtu) { 3054 ALC_LOCK(sc); 3055 ifp->if_mtu = ifr->ifr_mtu; 3056 /* AR81[3567]x has 13 bits MSS field. */ 3057 if (ifp->if_mtu > ALC_TSO_MTU && 3058 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3059 ifp->if_capenable &= ~IFCAP_TSO4; 3060 ifp->if_hwassist &= ~CSUM_TSO; 3061 VLAN_CAPABILITIES(ifp); 3062 } 3063 ALC_UNLOCK(sc); 3064 } 3065 break; 3066 case SIOCSIFFLAGS: 3067 ALC_LOCK(sc); 3068 if ((ifp->if_flags & IFF_UP) != 0) { 3069 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3070 ((ifp->if_flags ^ sc->alc_if_flags) & 3071 (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3072 alc_rxfilter(sc); 3073 else 3074 alc_init_locked(sc); 3075 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3076 alc_stop(sc); 3077 sc->alc_if_flags = ifp->if_flags; 3078 ALC_UNLOCK(sc); 3079 break; 3080 case SIOCADDMULTI: 3081 case SIOCDELMULTI: 3082 ALC_LOCK(sc); 3083 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3084 alc_rxfilter(sc); 3085 ALC_UNLOCK(sc); 3086 break; 3087 case SIOCSIFMEDIA: 3088 case SIOCGIFMEDIA: 3089 mii = device_get_softc(sc->alc_miibus); 3090 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 3091 break; 3092 case SIOCSIFCAP: 3093 ALC_LOCK(sc); 3094 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3095 if ((mask & IFCAP_TXCSUM) != 0 && 3096 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3097 ifp->if_capenable ^= IFCAP_TXCSUM; 3098 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 3099 ifp->if_hwassist |= ALC_CSUM_FEATURES; 3100 else 3101 ifp->if_hwassist &= ~ALC_CSUM_FEATURES; 3102 } 3103 if ((mask & IFCAP_TSO4) != 0 && 3104 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3105 ifp->if_capenable ^= IFCAP_TSO4; 3106 if ((ifp->if_capenable & IFCAP_TSO4) != 0) { 3107 /* AR81[3567]x has 13 bits MSS field. */ 3108 if (ifp->if_mtu > ALC_TSO_MTU) { 3109 ifp->if_capenable &= ~IFCAP_TSO4; 3110 ifp->if_hwassist &= ~CSUM_TSO; 3111 } else 3112 ifp->if_hwassist |= CSUM_TSO; 3113 } else 3114 ifp->if_hwassist &= ~CSUM_TSO; 3115 } 3116 if ((mask & IFCAP_WOL_MCAST) != 0 && 3117 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 3118 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3119 if ((mask & IFCAP_WOL_MAGIC) != 0 && 3120 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 3121 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3122 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3123 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3124 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3125 alc_rxvlan(sc); 3126 } 3127 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 3128 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 3129 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 3130 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3131 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3132 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3133 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3134 ifp->if_capenable &= 3135 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 3136 ALC_UNLOCK(sc); 3137 VLAN_CAPABILITIES(ifp); 3138 break; 3139 default: 3140 error = ether_ioctl(ifp, cmd, data); 3141 break; 3142 } 3143 3144 return (error); 3145 } 3146 3147 static void 3148 alc_mac_config(struct alc_softc *sc) 3149 { 3150 struct mii_data *mii; 3151 uint32_t reg; 3152 3153 ALC_LOCK_ASSERT(sc); 3154 3155 mii = device_get_softc(sc->alc_miibus); 3156 reg = CSR_READ_4(sc, ALC_MAC_CFG); 3157 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 3158 MAC_CFG_SPEED_MASK); 3159 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3160 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 3161 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 3162 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 3163 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 3164 /* Reprogram MAC with resolved speed/duplex. */ 3165 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3166 case IFM_10_T: 3167 case IFM_100_TX: 3168 reg |= MAC_CFG_SPEED_10_100; 3169 break; 3170 case IFM_1000_T: 3171 reg |= MAC_CFG_SPEED_1000; 3172 break; 3173 } 3174 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 3175 reg |= MAC_CFG_FULL_DUPLEX; 3176 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 3177 reg |= MAC_CFG_TX_FC; 3178 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 3179 reg |= MAC_CFG_RX_FC; 3180 } 3181 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 3182 } 3183 3184 static void 3185 alc_stats_clear(struct alc_softc *sc) 3186 { 3187 struct smb sb, *smb; 3188 uint32_t *reg; 3189 int i; 3190 3191 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3192 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3193 sc->alc_cdata.alc_smb_map, 3194 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3195 smb = sc->alc_rdata.alc_smb; 3196 /* Update done, clear. */ 3197 smb->updated = 0; 3198 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3199 sc->alc_cdata.alc_smb_map, 3200 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3201 } else { 3202 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3203 reg++) { 3204 CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3205 i += sizeof(uint32_t); 3206 } 3207 /* Read Tx statistics. */ 3208 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3209 reg++) { 3210 CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3211 i += sizeof(uint32_t); 3212 } 3213 } 3214 } 3215 3216 static void 3217 alc_stats_update(struct alc_softc *sc) 3218 { 3219 struct alc_hw_stats *stat; 3220 struct smb sb, *smb; 3221 struct ifnet *ifp; 3222 uint32_t *reg; 3223 int i; 3224 3225 ALC_LOCK_ASSERT(sc); 3226 3227 ifp = sc->alc_ifp; 3228 stat = &sc->alc_stats; 3229 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3230 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3231 sc->alc_cdata.alc_smb_map, 3232 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3233 smb = sc->alc_rdata.alc_smb; 3234 if (smb->updated == 0) 3235 return; 3236 } else { 3237 smb = &sb; 3238 /* Read Rx statistics. */ 3239 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; 3240 reg++) { 3241 *reg = CSR_READ_4(sc, ALC_RX_MIB_BASE + i); 3242 i += sizeof(uint32_t); 3243 } 3244 /* Read Tx statistics. */ 3245 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; 3246 reg++) { 3247 *reg = CSR_READ_4(sc, ALC_TX_MIB_BASE + i); 3248 i += sizeof(uint32_t); 3249 } 3250 } 3251 3252 /* Rx stats. */ 3253 stat->rx_frames += smb->rx_frames; 3254 stat->rx_bcast_frames += smb->rx_bcast_frames; 3255 stat->rx_mcast_frames += smb->rx_mcast_frames; 3256 stat->rx_pause_frames += smb->rx_pause_frames; 3257 stat->rx_control_frames += smb->rx_control_frames; 3258 stat->rx_crcerrs += smb->rx_crcerrs; 3259 stat->rx_lenerrs += smb->rx_lenerrs; 3260 stat->rx_bytes += smb->rx_bytes; 3261 stat->rx_runts += smb->rx_runts; 3262 stat->rx_fragments += smb->rx_fragments; 3263 stat->rx_pkts_64 += smb->rx_pkts_64; 3264 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 3265 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 3266 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 3267 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 3268 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 3269 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 3270 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 3271 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 3272 stat->rx_rrs_errs += smb->rx_rrs_errs; 3273 stat->rx_alignerrs += smb->rx_alignerrs; 3274 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 3275 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 3276 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 3277 3278 /* Tx stats. */ 3279 stat->tx_frames += smb->tx_frames; 3280 stat->tx_bcast_frames += smb->tx_bcast_frames; 3281 stat->tx_mcast_frames += smb->tx_mcast_frames; 3282 stat->tx_pause_frames += smb->tx_pause_frames; 3283 stat->tx_excess_defer += smb->tx_excess_defer; 3284 stat->tx_control_frames += smb->tx_control_frames; 3285 stat->tx_deferred += smb->tx_deferred; 3286 stat->tx_bytes += smb->tx_bytes; 3287 stat->tx_pkts_64 += smb->tx_pkts_64; 3288 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 3289 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 3290 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 3291 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 3292 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 3293 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 3294 stat->tx_single_colls += smb->tx_single_colls; 3295 stat->tx_multi_colls += smb->tx_multi_colls; 3296 stat->tx_late_colls += smb->tx_late_colls; 3297 stat->tx_excess_colls += smb->tx_excess_colls; 3298 stat->tx_underrun += smb->tx_underrun; 3299 stat->tx_desc_underrun += smb->tx_desc_underrun; 3300 stat->tx_lenerrs += smb->tx_lenerrs; 3301 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 3302 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 3303 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 3304 3305 /* Update counters in ifnet. */ 3306 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 3307 3308 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 3309 smb->tx_multi_colls * 2 + smb->tx_late_colls + 3310 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 3311 3312 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 3313 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 3314 3315 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 3316 3317 if_inc_counter(ifp, IFCOUNTER_IERRORS, 3318 smb->rx_crcerrs + smb->rx_lenerrs + 3319 smb->rx_runts + smb->rx_pkts_truncated + 3320 smb->rx_fifo_oflows + smb->rx_rrs_errs + 3321 smb->rx_alignerrs); 3322 3323 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) { 3324 /* Update done, clear. */ 3325 smb->updated = 0; 3326 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, 3327 sc->alc_cdata.alc_smb_map, 3328 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3329 } 3330 } 3331 3332 static int 3333 alc_intr(void *arg) 3334 { 3335 struct alc_softc *sc; 3336 uint32_t status; 3337 3338 sc = (struct alc_softc *)arg; 3339 3340 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3341 if ((status & ALC_INTRS) == 0) 3342 return (FILTER_STRAY); 3343 /* Disable interrupts. */ 3344 CSR_WRITE_4(sc, ALC_INTR_STATUS, INTR_DIS_INT); 3345 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3346 3347 return (FILTER_HANDLED); 3348 } 3349 3350 static void 3351 alc_int_task(void *arg, int pending) 3352 { 3353 struct alc_softc *sc; 3354 struct ifnet *ifp; 3355 uint32_t status; 3356 int more; 3357 3358 sc = (struct alc_softc *)arg; 3359 ifp = sc->alc_ifp; 3360 3361 status = CSR_READ_4(sc, ALC_INTR_STATUS); 3362 ALC_LOCK(sc); 3363 if (sc->alc_morework != 0) { 3364 sc->alc_morework = 0; 3365 status |= INTR_RX_PKT; 3366 } 3367 if ((status & ALC_INTRS) == 0) 3368 goto done; 3369 3370 /* Acknowledge interrupts but still disable interrupts. */ 3371 CSR_WRITE_4(sc, ALC_INTR_STATUS, status | INTR_DIS_INT); 3372 3373 more = 0; 3374 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3375 if ((status & INTR_RX_PKT) != 0) { 3376 more = alc_rxintr(sc, sc->alc_process_limit); 3377 if (more == EAGAIN) 3378 sc->alc_morework = 1; 3379 else if (more == EIO) { 3380 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3381 alc_init_locked(sc); 3382 ALC_UNLOCK(sc); 3383 return; 3384 } 3385 } 3386 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | 3387 INTR_TXQ_TO_RST)) != 0) { 3388 if ((status & INTR_DMA_RD_TO_RST) != 0) 3389 device_printf(sc->alc_dev, 3390 "DMA read error! -- resetting\n"); 3391 if ((status & INTR_DMA_WR_TO_RST) != 0) 3392 device_printf(sc->alc_dev, 3393 "DMA write error! -- resetting\n"); 3394 if ((status & INTR_TXQ_TO_RST) != 0) 3395 device_printf(sc->alc_dev, 3396 "TxQ reset! -- resetting\n"); 3397 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3398 alc_init_locked(sc); 3399 ALC_UNLOCK(sc); 3400 return; 3401 } 3402 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 3403 !IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3404 alc_start_locked(ifp); 3405 } 3406 3407 if (more == EAGAIN || 3408 (CSR_READ_4(sc, ALC_INTR_STATUS) & ALC_INTRS) != 0) { 3409 ALC_UNLOCK(sc); 3410 taskqueue_enqueue(sc->alc_tq, &sc->alc_int_task); 3411 return; 3412 } 3413 3414 done: 3415 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3416 /* Re-enable interrupts if we're running. */ 3417 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0x7FFFFFFF); 3418 } 3419 ALC_UNLOCK(sc); 3420 } 3421 3422 static void 3423 alc_txeof(struct alc_softc *sc) 3424 { 3425 struct ifnet *ifp; 3426 struct alc_txdesc *txd; 3427 uint32_t cons, prod; 3428 int prog; 3429 3430 ALC_LOCK_ASSERT(sc); 3431 3432 ifp = sc->alc_ifp; 3433 3434 if (sc->alc_cdata.alc_tx_cnt == 0) 3435 return; 3436 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 3437 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_POSTWRITE); 3438 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 3439 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3440 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_POSTREAD); 3441 prod = sc->alc_rdata.alc_cmb->cons; 3442 } else { 3443 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3444 prod = CSR_READ_2(sc, ALC_MBOX_TD_PRI0_CONS_IDX); 3445 else { 3446 prod = CSR_READ_4(sc, ALC_MBOX_TD_CONS_IDX); 3447 /* Assume we're using normal Tx priority queue. */ 3448 prod = (prod & MBOX_TD_CONS_LO_IDX_MASK) >> 3449 MBOX_TD_CONS_LO_IDX_SHIFT; 3450 } 3451 } 3452 cons = sc->alc_cdata.alc_tx_cons; 3453 /* 3454 * Go through our Tx list and free mbufs for those 3455 * frames which have been transmitted. 3456 */ 3457 for (prog = 0; cons != prod; prog++, 3458 ALC_DESC_INC(cons, ALC_TX_RING_CNT)) { 3459 if (sc->alc_cdata.alc_tx_cnt <= 0) 3460 break; 3461 prog++; 3462 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3463 sc->alc_cdata.alc_tx_cnt--; 3464 txd = &sc->alc_cdata.alc_txdesc[cons]; 3465 if (txd->tx_m != NULL) { 3466 /* Reclaim transmitted mbufs. */ 3467 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 3468 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3469 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 3470 txd->tx_dmamap); 3471 m_freem(txd->tx_m); 3472 txd->tx_m = NULL; 3473 } 3474 } 3475 3476 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 3477 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, 3478 sc->alc_cdata.alc_cmb_map, BUS_DMASYNC_PREREAD); 3479 sc->alc_cdata.alc_tx_cons = cons; 3480 /* 3481 * Unarm watchdog timer only when there is no pending 3482 * frames in Tx queue. 3483 */ 3484 if (sc->alc_cdata.alc_tx_cnt == 0) 3485 sc->alc_watchdog_timer = 0; 3486 } 3487 3488 static int 3489 alc_newbuf(struct alc_softc *sc, struct alc_rxdesc *rxd) 3490 { 3491 struct mbuf *m; 3492 bus_dma_segment_t segs[1]; 3493 bus_dmamap_t map; 3494 int nsegs; 3495 3496 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 3497 if (m == NULL) 3498 return (ENOBUFS); 3499 m->m_len = m->m_pkthdr.len = RX_BUF_SIZE_MAX; 3500 #ifndef __NO_STRICT_ALIGNMENT 3501 m_adj(m, sizeof(uint64_t)); 3502 #endif 3503 3504 if (bus_dmamap_load_mbuf_sg(sc->alc_cdata.alc_rx_tag, 3505 sc->alc_cdata.alc_rx_sparemap, m, segs, &nsegs, 0) != 0) { 3506 m_freem(m); 3507 return (ENOBUFS); 3508 } 3509 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 3510 3511 if (rxd->rx_m != NULL) { 3512 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3513 BUS_DMASYNC_POSTREAD); 3514 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap); 3515 } 3516 map = rxd->rx_dmamap; 3517 rxd->rx_dmamap = sc->alc_cdata.alc_rx_sparemap; 3518 sc->alc_cdata.alc_rx_sparemap = map; 3519 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, rxd->rx_dmamap, 3520 BUS_DMASYNC_PREREAD); 3521 rxd->rx_m = m; 3522 rxd->rx_desc->addr = htole64(segs[0].ds_addr); 3523 return (0); 3524 } 3525 3526 static int 3527 alc_rxintr(struct alc_softc *sc, int count) 3528 { 3529 struct ifnet *ifp; 3530 struct rx_rdesc *rrd; 3531 uint32_t nsegs, status; 3532 int rr_cons, prog; 3533 3534 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3535 sc->alc_cdata.alc_rr_ring_map, 3536 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 3537 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3538 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_POSTWRITE); 3539 rr_cons = sc->alc_cdata.alc_rr_cons; 3540 ifp = sc->alc_ifp; 3541 for (prog = 0; (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0;) { 3542 if (count-- <= 0) 3543 break; 3544 rrd = &sc->alc_rdata.alc_rr_ring[rr_cons]; 3545 status = le32toh(rrd->status); 3546 if ((status & RRD_VALID) == 0) 3547 break; 3548 nsegs = RRD_RD_CNT(le32toh(rrd->rdinfo)); 3549 if (nsegs == 0) { 3550 /* This should not happen! */ 3551 device_printf(sc->alc_dev, 3552 "unexpected segment count -- resetting\n"); 3553 return (EIO); 3554 } 3555 alc_rxeof(sc, rrd); 3556 /* Clear Rx return status. */ 3557 rrd->status = 0; 3558 ALC_DESC_INC(rr_cons, ALC_RR_RING_CNT); 3559 sc->alc_cdata.alc_rx_cons += nsegs; 3560 sc->alc_cdata.alc_rx_cons %= ALC_RR_RING_CNT; 3561 prog += nsegs; 3562 } 3563 3564 if (prog > 0) { 3565 /* Update the consumer index. */ 3566 sc->alc_cdata.alc_rr_cons = rr_cons; 3567 /* Sync Rx return descriptors. */ 3568 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 3569 sc->alc_cdata.alc_rr_ring_map, 3570 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3571 /* 3572 * Sync updated Rx descriptors such that controller see 3573 * modified buffer addresses. 3574 */ 3575 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 3576 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 3577 /* 3578 * Let controller know availability of new Rx buffers. 3579 * Since alc(4) use RXQ_CFG_RD_BURST_DEFAULT descriptors 3580 * it may be possible to update ALC_MBOX_RD0_PROD_IDX 3581 * only when Rx buffer pre-fetching is required. In 3582 * addition we already set ALC_RX_RD_FREE_THRESH to 3583 * RX_RD_FREE_THRESH_LO_DEFAULT descriptors. However 3584 * it still seems that pre-fetching needs more 3585 * experimentation. 3586 */ 3587 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 3588 CSR_WRITE_2(sc, ALC_MBOX_RD0_PROD_IDX, 3589 (uint16_t)sc->alc_cdata.alc_rx_cons); 3590 else 3591 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 3592 sc->alc_cdata.alc_rx_cons); 3593 } 3594 3595 return (count > 0 ? 0 : EAGAIN); 3596 } 3597 3598 #ifndef __NO_STRICT_ALIGNMENT 3599 static struct mbuf * 3600 alc_fixup_rx(struct ifnet *ifp, struct mbuf *m) 3601 { 3602 struct mbuf *n; 3603 int i; 3604 uint16_t *src, *dst; 3605 3606 src = mtod(m, uint16_t *); 3607 dst = src - 3; 3608 3609 if (m->m_next == NULL) { 3610 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 3611 *dst++ = *src++; 3612 m->m_data -= 6; 3613 return (m); 3614 } 3615 /* 3616 * Append a new mbuf to received mbuf chain and copy ethernet 3617 * header from the mbuf chain. This can save lots of CPU 3618 * cycles for jumbo frame. 3619 */ 3620 MGETHDR(n, M_NOWAIT, MT_DATA); 3621 if (n == NULL) { 3622 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3623 m_freem(m); 3624 return (NULL); 3625 } 3626 bcopy(m->m_data, n->m_data, ETHER_HDR_LEN); 3627 m->m_data += ETHER_HDR_LEN; 3628 m->m_len -= ETHER_HDR_LEN; 3629 n->m_len = ETHER_HDR_LEN; 3630 M_MOVE_PKTHDR(n, m); 3631 n->m_next = m; 3632 return (n); 3633 } 3634 #endif 3635 3636 /* Receive a frame. */ 3637 static void 3638 alc_rxeof(struct alc_softc *sc, struct rx_rdesc *rrd) 3639 { 3640 struct alc_rxdesc *rxd; 3641 struct ifnet *ifp; 3642 struct mbuf *mp, *m; 3643 uint32_t rdinfo, status, vtag; 3644 int count, nsegs, rx_cons; 3645 3646 ifp = sc->alc_ifp; 3647 status = le32toh(rrd->status); 3648 rdinfo = le32toh(rrd->rdinfo); 3649 rx_cons = RRD_RD_IDX(rdinfo); 3650 nsegs = RRD_RD_CNT(rdinfo); 3651 3652 sc->alc_cdata.alc_rxlen = RRD_BYTES(status); 3653 if ((status & (RRD_ERR_SUM | RRD_ERR_LENGTH)) != 0) { 3654 /* 3655 * We want to pass the following frames to upper 3656 * layer regardless of error status of Rx return 3657 * ring. 3658 * 3659 * o IP/TCP/UDP checksum is bad. 3660 * o frame length and protocol specific length 3661 * does not match. 3662 * 3663 * Force network stack compute checksum for 3664 * errored frames. 3665 */ 3666 status |= RRD_TCP_UDPCSUM_NOK | RRD_IPCSUM_NOK; 3667 if ((status & (RRD_ERR_CRC | RRD_ERR_ALIGN | 3668 RRD_ERR_TRUNC | RRD_ERR_RUNT)) != 0) 3669 return; 3670 } 3671 3672 for (count = 0; count < nsegs; count++, 3673 ALC_DESC_INC(rx_cons, ALC_RX_RING_CNT)) { 3674 rxd = &sc->alc_cdata.alc_rxdesc[rx_cons]; 3675 mp = rxd->rx_m; 3676 /* Add a new receive buffer to the ring. */ 3677 if (alc_newbuf(sc, rxd) != 0) { 3678 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 3679 /* Reuse Rx buffers. */ 3680 if (sc->alc_cdata.alc_rxhead != NULL) 3681 m_freem(sc->alc_cdata.alc_rxhead); 3682 break; 3683 } 3684 3685 /* 3686 * Assume we've received a full sized frame. 3687 * Actual size is fixed when we encounter the end of 3688 * multi-segmented frame. 3689 */ 3690 mp->m_len = sc->alc_buf_size; 3691 3692 /* Chain received mbufs. */ 3693 if (sc->alc_cdata.alc_rxhead == NULL) { 3694 sc->alc_cdata.alc_rxhead = mp; 3695 sc->alc_cdata.alc_rxtail = mp; 3696 } else { 3697 mp->m_flags &= ~M_PKTHDR; 3698 sc->alc_cdata.alc_rxprev_tail = 3699 sc->alc_cdata.alc_rxtail; 3700 sc->alc_cdata.alc_rxtail->m_next = mp; 3701 sc->alc_cdata.alc_rxtail = mp; 3702 } 3703 3704 if (count == nsegs - 1) { 3705 /* Last desc. for this frame. */ 3706 m = sc->alc_cdata.alc_rxhead; 3707 m->m_flags |= M_PKTHDR; 3708 /* 3709 * It seems that L1C/L2C controller has no way 3710 * to tell hardware to strip CRC bytes. 3711 */ 3712 m->m_pkthdr.len = 3713 sc->alc_cdata.alc_rxlen - ETHER_CRC_LEN; 3714 if (nsegs > 1) { 3715 /* Set last mbuf size. */ 3716 mp->m_len = sc->alc_cdata.alc_rxlen - 3717 (nsegs - 1) * sc->alc_buf_size; 3718 /* Remove the CRC bytes in chained mbufs. */ 3719 if (mp->m_len <= ETHER_CRC_LEN) { 3720 sc->alc_cdata.alc_rxtail = 3721 sc->alc_cdata.alc_rxprev_tail; 3722 sc->alc_cdata.alc_rxtail->m_len -= 3723 (ETHER_CRC_LEN - mp->m_len); 3724 sc->alc_cdata.alc_rxtail->m_next = NULL; 3725 m_freem(mp); 3726 } else { 3727 mp->m_len -= ETHER_CRC_LEN; 3728 } 3729 } else 3730 m->m_len = m->m_pkthdr.len; 3731 m->m_pkthdr.rcvif = ifp; 3732 /* 3733 * Due to hardware bugs, Rx checksum offloading 3734 * was intentionally disabled. 3735 */ 3736 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 3737 (status & RRD_VLAN_TAG) != 0) { 3738 vtag = RRD_VLAN(le32toh(rrd->vtag)); 3739 m->m_pkthdr.ether_vtag = ntohs(vtag); 3740 m->m_flags |= M_VLANTAG; 3741 } 3742 #ifndef __NO_STRICT_ALIGNMENT 3743 m = alc_fixup_rx(ifp, m); 3744 if (m != NULL) 3745 #endif 3746 { 3747 /* Pass it on. */ 3748 ALC_UNLOCK(sc); 3749 (*ifp->if_input)(ifp, m); 3750 ALC_LOCK(sc); 3751 } 3752 } 3753 } 3754 /* Reset mbuf chains. */ 3755 ALC_RXCHAIN_RESET(sc); 3756 } 3757 3758 static void 3759 alc_tick(void *arg) 3760 { 3761 struct alc_softc *sc; 3762 struct mii_data *mii; 3763 3764 sc = (struct alc_softc *)arg; 3765 3766 ALC_LOCK_ASSERT(sc); 3767 3768 mii = device_get_softc(sc->alc_miibus); 3769 mii_tick(mii); 3770 alc_stats_update(sc); 3771 /* 3772 * alc(4) does not rely on Tx completion interrupts to reclaim 3773 * transferred buffers. Instead Tx completion interrupts are 3774 * used to hint for scheduling Tx task. So it's necessary to 3775 * release transmitted buffers by kicking Tx completion 3776 * handler. This limits the maximum reclamation delay to a hz. 3777 */ 3778 alc_txeof(sc); 3779 alc_watchdog(sc); 3780 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 3781 } 3782 3783 static void 3784 alc_osc_reset(struct alc_softc *sc) 3785 { 3786 uint32_t reg; 3787 3788 reg = CSR_READ_4(sc, ALC_MISC3); 3789 reg &= ~MISC3_25M_BY_SW; 3790 reg |= MISC3_25M_NOTO_INTNL; 3791 CSR_WRITE_4(sc, ALC_MISC3, reg); 3792 3793 reg = CSR_READ_4(sc, ALC_MISC); 3794 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) { 3795 /* 3796 * Restore over-current protection default value. 3797 * This value could be reset by MAC reset. 3798 */ 3799 reg &= ~MISC_PSW_OCP_MASK; 3800 reg |= (MISC_PSW_OCP_DEFAULT << MISC_PSW_OCP_SHIFT); 3801 reg &= ~MISC_INTNLOSC_OPEN; 3802 CSR_WRITE_4(sc, ALC_MISC, reg); 3803 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3804 reg = CSR_READ_4(sc, ALC_MISC2); 3805 reg &= ~MISC2_CALB_START; 3806 CSR_WRITE_4(sc, ALC_MISC2, reg); 3807 CSR_WRITE_4(sc, ALC_MISC2, reg | MISC2_CALB_START); 3808 3809 } else { 3810 reg &= ~MISC_INTNLOSC_OPEN; 3811 /* Disable isolate for revision A devices. */ 3812 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3813 reg &= ~MISC_ISO_ENB; 3814 CSR_WRITE_4(sc, ALC_MISC, reg | MISC_INTNLOSC_OPEN); 3815 CSR_WRITE_4(sc, ALC_MISC, reg); 3816 } 3817 3818 DELAY(20); 3819 } 3820 3821 static void 3822 alc_reset(struct alc_softc *sc) 3823 { 3824 uint32_t pmcfg, reg; 3825 int i; 3826 3827 pmcfg = 0; 3828 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3829 /* Reset workaround. */ 3830 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, 1); 3831 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3832 (sc->alc_rev & 0x01) != 0) { 3833 /* Disable L0s/L1s before reset. */ 3834 pmcfg = CSR_READ_4(sc, ALC_PM_CFG); 3835 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3836 != 0) { 3837 pmcfg &= ~(PM_CFG_ASPM_L0S_ENB | 3838 PM_CFG_ASPM_L1_ENB); 3839 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3840 } 3841 } 3842 } 3843 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3844 reg |= MASTER_OOB_DIS_OFF | MASTER_RESET; 3845 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3846 3847 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3848 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3849 DELAY(10); 3850 if (CSR_READ_4(sc, ALC_MBOX_RD0_PROD_IDX) == 0) 3851 break; 3852 } 3853 if (i == 0) 3854 device_printf(sc->alc_dev, "MAC reset timeout!\n"); 3855 } 3856 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3857 DELAY(10); 3858 if ((CSR_READ_4(sc, ALC_MASTER_CFG) & MASTER_RESET) == 0) 3859 break; 3860 } 3861 if (i == 0) 3862 device_printf(sc->alc_dev, "master reset timeout!\n"); 3863 3864 for (i = ALC_RESET_TIMEOUT; i > 0; i--) { 3865 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 3866 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC | 3867 IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 3868 break; 3869 DELAY(10); 3870 } 3871 if (i == 0) 3872 device_printf(sc->alc_dev, "reset timeout(0x%08x)!\n", reg); 3873 3874 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3875 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1 && 3876 (sc->alc_rev & 0x01) != 0) { 3877 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 3878 reg |= MASTER_CLK_SEL_DIS; 3879 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 3880 /* Restore L0s/L1s config. */ 3881 if ((pmcfg & (PM_CFG_ASPM_L0S_ENB | PM_CFG_ASPM_L1_ENB)) 3882 != 0) 3883 CSR_WRITE_4(sc, ALC_PM_CFG, pmcfg); 3884 } 3885 3886 alc_osc_reset(sc); 3887 reg = CSR_READ_4(sc, ALC_MISC3); 3888 reg &= ~MISC3_25M_BY_SW; 3889 reg |= MISC3_25M_NOTO_INTNL; 3890 CSR_WRITE_4(sc, ALC_MISC3, reg); 3891 reg = CSR_READ_4(sc, ALC_MISC); 3892 reg &= ~MISC_INTNLOSC_OPEN; 3893 if (AR816X_REV(sc->alc_rev) <= AR816X_REV_A1) 3894 reg &= ~MISC_ISO_ENB; 3895 CSR_WRITE_4(sc, ALC_MISC, reg); 3896 DELAY(20); 3897 } 3898 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 3899 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 3900 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2) 3901 CSR_WRITE_4(sc, ALC_SERDES_LOCK, 3902 CSR_READ_4(sc, ALC_SERDES_LOCK) | SERDES_MAC_CLK_SLOWDOWN | 3903 SERDES_PHY_CLK_SLOWDOWN); 3904 } 3905 3906 static void 3907 alc_init(void *xsc) 3908 { 3909 struct alc_softc *sc; 3910 3911 sc = (struct alc_softc *)xsc; 3912 ALC_LOCK(sc); 3913 alc_init_locked(sc); 3914 ALC_UNLOCK(sc); 3915 } 3916 3917 static void 3918 alc_init_locked(struct alc_softc *sc) 3919 { 3920 struct ifnet *ifp; 3921 struct mii_data *mii; 3922 uint8_t eaddr[ETHER_ADDR_LEN]; 3923 bus_addr_t paddr; 3924 uint32_t reg, rxf_hi, rxf_lo; 3925 3926 ALC_LOCK_ASSERT(sc); 3927 3928 ifp = sc->alc_ifp; 3929 mii = device_get_softc(sc->alc_miibus); 3930 3931 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3932 return; 3933 /* 3934 * Cancel any pending I/O. 3935 */ 3936 alc_stop(sc); 3937 /* 3938 * Reset the chip to a known state. 3939 */ 3940 alc_reset(sc); 3941 3942 /* Initialize Rx descriptors. */ 3943 if (alc_init_rx_ring(sc) != 0) { 3944 device_printf(sc->alc_dev, "no memory for Rx buffers.\n"); 3945 alc_stop(sc); 3946 return; 3947 } 3948 alc_init_rr_ring(sc); 3949 alc_init_tx_ring(sc); 3950 alc_init_cmb(sc); 3951 alc_init_smb(sc); 3952 3953 /* Enable all clocks. */ 3954 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 3955 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, CLK_GATING_DMAW_ENB | 3956 CLK_GATING_DMAR_ENB | CLK_GATING_TXQ_ENB | 3957 CLK_GATING_RXQ_ENB | CLK_GATING_TXMAC_ENB | 3958 CLK_GATING_RXMAC_ENB); 3959 if (AR816X_REV(sc->alc_rev) >= AR816X_REV_B0) 3960 CSR_WRITE_4(sc, ALC_IDLE_DECISN_TIMER, 3961 IDLE_DECISN_TIMER_DEFAULT_1MS); 3962 } else 3963 CSR_WRITE_4(sc, ALC_CLK_GATING_CFG, 0); 3964 3965 /* Reprogram the station address. */ 3966 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 3967 CSR_WRITE_4(sc, ALC_PAR0, 3968 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 3969 CSR_WRITE_4(sc, ALC_PAR1, eaddr[0] << 8 | eaddr[1]); 3970 /* 3971 * Clear WOL status and disable all WOL feature as WOL 3972 * would interfere Rx operation under normal environments. 3973 */ 3974 CSR_READ_4(sc, ALC_WOL_CFG); 3975 CSR_WRITE_4(sc, ALC_WOL_CFG, 0); 3976 /* Set Tx descriptor base addresses. */ 3977 paddr = sc->alc_rdata.alc_tx_ring_paddr; 3978 CSR_WRITE_4(sc, ALC_TX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3979 CSR_WRITE_4(sc, ALC_TDL_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3980 /* We don't use high priority ring. */ 3981 CSR_WRITE_4(sc, ALC_TDH_HEAD_ADDR_LO, 0); 3982 /* Set Tx descriptor counter. */ 3983 CSR_WRITE_4(sc, ALC_TD_RING_CNT, 3984 (ALC_TX_RING_CNT << TD_RING_CNT_SHIFT) & TD_RING_CNT_MASK); 3985 /* Set Rx descriptor base addresses. */ 3986 paddr = sc->alc_rdata.alc_rx_ring_paddr; 3987 CSR_WRITE_4(sc, ALC_RX_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 3988 CSR_WRITE_4(sc, ALC_RD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 3989 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 3990 /* We use one Rx ring. */ 3991 CSR_WRITE_4(sc, ALC_RD1_HEAD_ADDR_LO, 0); 3992 CSR_WRITE_4(sc, ALC_RD2_HEAD_ADDR_LO, 0); 3993 CSR_WRITE_4(sc, ALC_RD3_HEAD_ADDR_LO, 0); 3994 } 3995 /* Set Rx descriptor counter. */ 3996 CSR_WRITE_4(sc, ALC_RD_RING_CNT, 3997 (ALC_RX_RING_CNT << RD_RING_CNT_SHIFT) & RD_RING_CNT_MASK); 3998 3999 /* 4000 * Let hardware split jumbo frames into alc_max_buf_sized chunks. 4001 * if it do not fit the buffer size. Rx return descriptor holds 4002 * a counter that indicates how many fragments were made by the 4003 * hardware. The buffer size should be multiple of 8 bytes. 4004 * Since hardware has limit on the size of buffer size, always 4005 * use the maximum value. 4006 * For strict-alignment architectures make sure to reduce buffer 4007 * size by 8 bytes to make room for alignment fixup. 4008 */ 4009 #ifndef __NO_STRICT_ALIGNMENT 4010 sc->alc_buf_size = RX_BUF_SIZE_MAX - sizeof(uint64_t); 4011 #else 4012 sc->alc_buf_size = RX_BUF_SIZE_MAX; 4013 #endif 4014 CSR_WRITE_4(sc, ALC_RX_BUF_SIZE, sc->alc_buf_size); 4015 4016 paddr = sc->alc_rdata.alc_rr_ring_paddr; 4017 /* Set Rx return descriptor base addresses. */ 4018 CSR_WRITE_4(sc, ALC_RRD0_HEAD_ADDR_LO, ALC_ADDR_LO(paddr)); 4019 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4020 /* We use one Rx return ring. */ 4021 CSR_WRITE_4(sc, ALC_RRD1_HEAD_ADDR_LO, 0); 4022 CSR_WRITE_4(sc, ALC_RRD2_HEAD_ADDR_LO, 0); 4023 CSR_WRITE_4(sc, ALC_RRD3_HEAD_ADDR_LO, 0); 4024 } 4025 /* Set Rx return descriptor counter. */ 4026 CSR_WRITE_4(sc, ALC_RRD_RING_CNT, 4027 (ALC_RR_RING_CNT << RRD_RING_CNT_SHIFT) & RRD_RING_CNT_MASK); 4028 paddr = sc->alc_rdata.alc_cmb_paddr; 4029 CSR_WRITE_4(sc, ALC_CMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4030 paddr = sc->alc_rdata.alc_smb_paddr; 4031 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_HI, ALC_ADDR_HI(paddr)); 4032 CSR_WRITE_4(sc, ALC_SMB_BASE_ADDR_LO, ALC_ADDR_LO(paddr)); 4033 4034 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B) { 4035 /* Reconfigure SRAM - Vendor magic. */ 4036 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_LEN, 0x000002A0); 4037 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_LEN, 0x00000100); 4038 CSR_WRITE_4(sc, ALC_SRAM_RX_FIFO_ADDR, 0x029F0000); 4039 CSR_WRITE_4(sc, ALC_SRAM_RD0_ADDR, 0x02BF02A0); 4040 CSR_WRITE_4(sc, ALC_SRAM_TX_FIFO_ADDR, 0x03BF02C0); 4041 CSR_WRITE_4(sc, ALC_SRAM_TD_ADDR, 0x03DF03C0); 4042 CSR_WRITE_4(sc, ALC_TXF_WATER_MARK, 0x00000000); 4043 CSR_WRITE_4(sc, ALC_RD_DMA_CFG, 0x00000000); 4044 } 4045 4046 /* Tell hardware that we're ready to load DMA blocks. */ 4047 CSR_WRITE_4(sc, ALC_DMA_BLOCK, DMA_BLOCK_LOAD); 4048 4049 /* Configure interrupt moderation timer. */ 4050 reg = ALC_USECS(sc->alc_int_rx_mod) << IM_TIMER_RX_SHIFT; 4051 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) 4052 reg |= ALC_USECS(sc->alc_int_tx_mod) << IM_TIMER_TX_SHIFT; 4053 CSR_WRITE_4(sc, ALC_IM_TIMER, reg); 4054 /* 4055 * We don't want to automatic interrupt clear as task queue 4056 * for the interrupt should know interrupt status. 4057 */ 4058 reg = CSR_READ_4(sc, ALC_MASTER_CFG); 4059 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 4060 reg |= MASTER_SA_TIMER_ENB; 4061 if (ALC_USECS(sc->alc_int_rx_mod) != 0) 4062 reg |= MASTER_IM_RX_TIMER_ENB; 4063 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0 && 4064 ALC_USECS(sc->alc_int_tx_mod) != 0) 4065 reg |= MASTER_IM_TX_TIMER_ENB; 4066 CSR_WRITE_4(sc, ALC_MASTER_CFG, reg); 4067 /* 4068 * Disable interrupt re-trigger timer. We don't want automatic 4069 * re-triggering of un-ACKed interrupts. 4070 */ 4071 CSR_WRITE_4(sc, ALC_INTR_RETRIG_TIMER, ALC_USECS(0)); 4072 /* Configure CMB. */ 4073 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4074 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, ALC_TX_RING_CNT / 3); 4075 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, 4076 ALC_USECS(sc->alc_int_tx_mod)); 4077 } else { 4078 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) { 4079 CSR_WRITE_4(sc, ALC_CMB_TD_THRESH, 4); 4080 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(5000)); 4081 } else 4082 CSR_WRITE_4(sc, ALC_CMB_TX_TIMER, ALC_USECS(0)); 4083 } 4084 /* 4085 * Hardware can be configured to issue SMB interrupt based 4086 * on programmed interval. Since there is a callout that is 4087 * invoked for every hz in driver we use that instead of 4088 * relying on periodic SMB interrupt. 4089 */ 4090 CSR_WRITE_4(sc, ALC_SMB_STAT_TIMER, ALC_USECS(0)); 4091 /* Clear MAC statistics. */ 4092 alc_stats_clear(sc); 4093 4094 /* 4095 * Always use maximum frame size that controller can support. 4096 * Otherwise received frames that has larger frame length 4097 * than alc(4) MTU would be silently dropped in hardware. This 4098 * would make path-MTU discovery hard as sender wouldn't get 4099 * any responses from receiver. alc(4) supports 4100 * multi-fragmented frames on Rx path so it has no issue on 4101 * assembling fragmented frames. Using maximum frame size also 4102 * removes the need to reinitialize hardware when interface 4103 * MTU configuration was changed. 4104 * 4105 * Be conservative in what you do, be liberal in what you 4106 * accept from others - RFC 793. 4107 */ 4108 CSR_WRITE_4(sc, ALC_FRAME_SIZE, sc->alc_ident->max_framelen); 4109 4110 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4111 /* Disable header split(?) */ 4112 CSR_WRITE_4(sc, ALC_HDS_CFG, 0); 4113 4114 /* Configure IPG/IFG parameters. */ 4115 CSR_WRITE_4(sc, ALC_IPG_IFG_CFG, 4116 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & 4117 IPG_IFG_IPGT_MASK) | 4118 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & 4119 IPG_IFG_MIFG_MASK) | 4120 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & 4121 IPG_IFG_IPG1_MASK) | 4122 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & 4123 IPG_IFG_IPG2_MASK)); 4124 /* Set parameters for half-duplex media. */ 4125 CSR_WRITE_4(sc, ALC_HDPX_CFG, 4126 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 4127 HDPX_CFG_LCOL_MASK) | 4128 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 4129 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 4130 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 4131 HDPX_CFG_ABEBT_MASK) | 4132 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 4133 HDPX_CFG_JAMIPG_MASK)); 4134 } 4135 4136 /* 4137 * Set TSO/checksum offload threshold. For frames that is 4138 * larger than this threshold, hardware wouldn't do 4139 * TSO/checksum offloading. 4140 */ 4141 reg = (sc->alc_ident->max_framelen >> TSO_OFFLOAD_THRESH_UNIT_SHIFT) & 4142 TSO_OFFLOAD_THRESH_MASK; 4143 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) 4144 reg |= TSO_OFFLOAD_ERRLGPKT_DROP_ENB; 4145 CSR_WRITE_4(sc, ALC_TSO_OFFLOAD_THRESH, reg); 4146 /* Configure TxQ. */ 4147 reg = (alc_dma_burst[sc->alc_dma_rd_burst] << 4148 TXQ_CFG_TX_FIFO_BURST_SHIFT) & TXQ_CFG_TX_FIFO_BURST_MASK; 4149 if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B || 4150 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4151 reg >>= 1; 4152 reg |= (TXQ_CFG_TD_BURST_DEFAULT << TXQ_CFG_TD_BURST_SHIFT) & 4153 TXQ_CFG_TD_BURST_MASK; 4154 reg |= TXQ_CFG_IP_OPTION_ENB | TXQ_CFG_8023_ENB; 4155 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE); 4156 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4157 reg = (TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q1_BURST_SHIFT | 4158 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q2_BURST_SHIFT | 4159 TXQ_CFG_TD_BURST_DEFAULT << HQTD_CFG_Q3_BURST_SHIFT | 4160 HQTD_CFG_BURST_ENB); 4161 CSR_WRITE_4(sc, ALC_HQTD_CFG, reg); 4162 reg = WRR_PRI_RESTRICT_NONE; 4163 reg |= (WRR_PRI_DEFAULT << WRR_PRI0_SHIFT | 4164 WRR_PRI_DEFAULT << WRR_PRI1_SHIFT | 4165 WRR_PRI_DEFAULT << WRR_PRI2_SHIFT | 4166 WRR_PRI_DEFAULT << WRR_PRI3_SHIFT); 4167 CSR_WRITE_4(sc, ALC_WRR, reg); 4168 } else { 4169 /* Configure Rx free descriptor pre-fetching. */ 4170 CSR_WRITE_4(sc, ALC_RX_RD_FREE_THRESH, 4171 ((RX_RD_FREE_THRESH_HI_DEFAULT << 4172 RX_RD_FREE_THRESH_HI_SHIFT) & RX_RD_FREE_THRESH_HI_MASK) | 4173 ((RX_RD_FREE_THRESH_LO_DEFAULT << 4174 RX_RD_FREE_THRESH_LO_SHIFT) & RX_RD_FREE_THRESH_LO_MASK)); 4175 } 4176 4177 /* 4178 * Configure flow control parameters. 4179 * XON : 80% of Rx FIFO 4180 * XOFF : 30% of Rx FIFO 4181 */ 4182 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4183 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4184 reg &= SRAM_RX_FIFO_LEN_MASK; 4185 reg *= 8; 4186 if (reg > 8 * 1024) 4187 reg -= RX_FIFO_PAUSE_816X_RSVD; 4188 else 4189 reg -= RX_BUF_SIZE_MAX; 4190 reg /= 8; 4191 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4192 ((reg << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4193 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4194 (((RX_FIFO_PAUSE_816X_RSVD / 8) << 4195 RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4196 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4197 } else if (sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8131 || 4198 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8132) { 4199 reg = CSR_READ_4(sc, ALC_SRAM_RX_FIFO_LEN); 4200 rxf_hi = (reg * 8) / 10; 4201 rxf_lo = (reg * 3) / 10; 4202 CSR_WRITE_4(sc, ALC_RX_FIFO_PAUSE_THRESH, 4203 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 4204 RX_FIFO_PAUSE_THRESH_LO_MASK) | 4205 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 4206 RX_FIFO_PAUSE_THRESH_HI_MASK)); 4207 } 4208 4209 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4210 /* Disable RSS until I understand L1C/L2C's RSS logic. */ 4211 CSR_WRITE_4(sc, ALC_RSS_IDT_TABLE0, 0); 4212 CSR_WRITE_4(sc, ALC_RSS_CPU, 0); 4213 } 4214 4215 /* Configure RxQ. */ 4216 reg = (RXQ_CFG_RD_BURST_DEFAULT << RXQ_CFG_RD_BURST_SHIFT) & 4217 RXQ_CFG_RD_BURST_MASK; 4218 reg |= RXQ_CFG_RSS_MODE_DIS; 4219 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4220 reg |= (RXQ_CFG_816X_IDT_TBL_SIZE_DEFAULT << 4221 RXQ_CFG_816X_IDT_TBL_SIZE_SHIFT) & 4222 RXQ_CFG_816X_IDT_TBL_SIZE_MASK; 4223 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0) 4224 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4225 } else { 4226 if ((sc->alc_flags & ALC_FLAG_FASTETHER) == 0 && 4227 sc->alc_ident->deviceid != DEVICEID_ATHEROS_AR8151_V2) 4228 reg |= RXQ_CFG_ASPM_THROUGHPUT_LIMIT_100M; 4229 } 4230 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4231 4232 /* Configure DMA parameters. */ 4233 reg = DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI; 4234 reg |= sc->alc_rcb; 4235 if ((sc->alc_flags & ALC_FLAG_CMB_BUG) == 0) 4236 reg |= DMA_CFG_CMB_ENB; 4237 if ((sc->alc_flags & ALC_FLAG_SMB_BUG) == 0) 4238 reg |= DMA_CFG_SMB_ENB; 4239 else 4240 reg |= DMA_CFG_SMB_DIS; 4241 reg |= (sc->alc_dma_rd_burst & DMA_CFG_RD_BURST_MASK) << 4242 DMA_CFG_RD_BURST_SHIFT; 4243 reg |= (sc->alc_dma_wr_burst & DMA_CFG_WR_BURST_MASK) << 4244 DMA_CFG_WR_BURST_SHIFT; 4245 reg |= (DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 4246 DMA_CFG_RD_DELAY_CNT_MASK; 4247 reg |= (DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 4248 DMA_CFG_WR_DELAY_CNT_MASK; 4249 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0) { 4250 switch (AR816X_REV(sc->alc_rev)) { 4251 case AR816X_REV_A0: 4252 case AR816X_REV_A1: 4253 reg |= DMA_CFG_RD_CHNL_SEL_2; 4254 break; 4255 case AR816X_REV_B0: 4256 /* FALLTHROUGH */ 4257 default: 4258 reg |= DMA_CFG_RD_CHNL_SEL_4; 4259 break; 4260 } 4261 } 4262 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4263 4264 /* 4265 * Configure Tx/Rx MACs. 4266 * - Auto-padding for short frames. 4267 * - Enable CRC generation. 4268 * Actual reconfiguration of MAC for resolved speed/duplex 4269 * is followed after detection of link establishment. 4270 * AR813x/AR815x always does checksum computation regardless 4271 * of MAC_CFG_RXCSUM_ENB bit. Also the controller is known to 4272 * have bug in protocol field in Rx return structure so 4273 * these controllers can't handle fragmented frames. Disable 4274 * Rx checksum offloading until there is a newer controller 4275 * that has sane implementation. 4276 */ 4277 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 4278 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 4279 MAC_CFG_PREAMBLE_MASK); 4280 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) != 0 || 4281 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151 || 4282 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8151_V2 || 4283 sc->alc_ident->deviceid == DEVICEID_ATHEROS_AR8152_B2) 4284 reg |= MAC_CFG_HASH_ALG_CRC32 | MAC_CFG_SPEED_MODE_SW; 4285 if ((sc->alc_flags & ALC_FLAG_FASTETHER) != 0) 4286 reg |= MAC_CFG_SPEED_10_100; 4287 else 4288 reg |= MAC_CFG_SPEED_1000; 4289 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4290 4291 /* Set up the receive filter. */ 4292 alc_rxfilter(sc); 4293 alc_rxvlan(sc); 4294 4295 /* Acknowledge all pending interrupts and clear it. */ 4296 CSR_WRITE_4(sc, ALC_INTR_MASK, ALC_INTRS); 4297 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4298 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0); 4299 4300 ifp->if_drv_flags |= IFF_DRV_RUNNING; 4301 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 4302 4303 sc->alc_flags &= ~ALC_FLAG_LINK; 4304 /* Switch to the current media. */ 4305 alc_mediachange_locked(sc); 4306 4307 callout_reset(&sc->alc_tick_ch, hz, alc_tick, sc); 4308 } 4309 4310 static void 4311 alc_stop(struct alc_softc *sc) 4312 { 4313 struct ifnet *ifp; 4314 struct alc_txdesc *txd; 4315 struct alc_rxdesc *rxd; 4316 uint32_t reg; 4317 int i; 4318 4319 ALC_LOCK_ASSERT(sc); 4320 /* 4321 * Mark the interface down and cancel the watchdog timer. 4322 */ 4323 ifp = sc->alc_ifp; 4324 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 4325 sc->alc_flags &= ~ALC_FLAG_LINK; 4326 callout_stop(&sc->alc_tick_ch); 4327 sc->alc_watchdog_timer = 0; 4328 alc_stats_update(sc); 4329 /* Disable interrupts. */ 4330 CSR_WRITE_4(sc, ALC_INTR_MASK, 0); 4331 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4332 /* Disable DMA. */ 4333 reg = CSR_READ_4(sc, ALC_DMA_CFG); 4334 reg &= ~(DMA_CFG_CMB_ENB | DMA_CFG_SMB_ENB); 4335 reg |= DMA_CFG_SMB_DIS; 4336 CSR_WRITE_4(sc, ALC_DMA_CFG, reg); 4337 DELAY(1000); 4338 /* Stop Rx/Tx MACs. */ 4339 alc_stop_mac(sc); 4340 /* Disable interrupts which might be touched in taskq handler. */ 4341 CSR_WRITE_4(sc, ALC_INTR_STATUS, 0xFFFFFFFF); 4342 /* Disable L0s/L1s */ 4343 alc_aspm(sc, 0, IFM_UNKNOWN); 4344 /* Reclaim Rx buffers that have been processed. */ 4345 if (sc->alc_cdata.alc_rxhead != NULL) 4346 m_freem(sc->alc_cdata.alc_rxhead); 4347 ALC_RXCHAIN_RESET(sc); 4348 /* 4349 * Free Tx/Rx mbufs still in the queues. 4350 */ 4351 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4352 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4353 if (rxd->rx_m != NULL) { 4354 bus_dmamap_sync(sc->alc_cdata.alc_rx_tag, 4355 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 4356 bus_dmamap_unload(sc->alc_cdata.alc_rx_tag, 4357 rxd->rx_dmamap); 4358 m_freem(rxd->rx_m); 4359 rxd->rx_m = NULL; 4360 } 4361 } 4362 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4363 txd = &sc->alc_cdata.alc_txdesc[i]; 4364 if (txd->tx_m != NULL) { 4365 bus_dmamap_sync(sc->alc_cdata.alc_tx_tag, 4366 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 4367 bus_dmamap_unload(sc->alc_cdata.alc_tx_tag, 4368 txd->tx_dmamap); 4369 m_freem(txd->tx_m); 4370 txd->tx_m = NULL; 4371 } 4372 } 4373 } 4374 4375 static void 4376 alc_stop_mac(struct alc_softc *sc) 4377 { 4378 uint32_t reg; 4379 int i; 4380 4381 alc_stop_queue(sc); 4382 /* Disable Rx/Tx MAC. */ 4383 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4384 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 4385 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 4386 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4387 } 4388 for (i = ALC_TIMEOUT; i > 0; i--) { 4389 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4390 if ((reg & (IDLE_STATUS_RXMAC | IDLE_STATUS_TXMAC)) == 0) 4391 break; 4392 DELAY(10); 4393 } 4394 if (i == 0) 4395 device_printf(sc->alc_dev, 4396 "could not disable Rx/Tx MAC(0x%08x)!\n", reg); 4397 } 4398 4399 static void 4400 alc_start_queue(struct alc_softc *sc) 4401 { 4402 uint32_t qcfg[] = { 4403 0, 4404 RXQ_CFG_QUEUE0_ENB, 4405 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB, 4406 RXQ_CFG_QUEUE0_ENB | RXQ_CFG_QUEUE1_ENB | RXQ_CFG_QUEUE2_ENB, 4407 RXQ_CFG_ENB 4408 }; 4409 uint32_t cfg; 4410 4411 ALC_LOCK_ASSERT(sc); 4412 4413 /* Enable RxQ. */ 4414 cfg = CSR_READ_4(sc, ALC_RXQ_CFG); 4415 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4416 cfg &= ~RXQ_CFG_ENB; 4417 cfg |= qcfg[1]; 4418 } else 4419 cfg |= RXQ_CFG_QUEUE0_ENB; 4420 CSR_WRITE_4(sc, ALC_RXQ_CFG, cfg); 4421 /* Enable TxQ. */ 4422 cfg = CSR_READ_4(sc, ALC_TXQ_CFG); 4423 cfg |= TXQ_CFG_ENB; 4424 CSR_WRITE_4(sc, ALC_TXQ_CFG, cfg); 4425 } 4426 4427 static void 4428 alc_stop_queue(struct alc_softc *sc) 4429 { 4430 uint32_t reg; 4431 int i; 4432 4433 /* Disable RxQ. */ 4434 reg = CSR_READ_4(sc, ALC_RXQ_CFG); 4435 if ((sc->alc_flags & ALC_FLAG_AR816X_FAMILY) == 0) { 4436 if ((reg & RXQ_CFG_ENB) != 0) { 4437 reg &= ~RXQ_CFG_ENB; 4438 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4439 } 4440 } else { 4441 if ((reg & RXQ_CFG_QUEUE0_ENB) != 0) { 4442 reg &= ~RXQ_CFG_QUEUE0_ENB; 4443 CSR_WRITE_4(sc, ALC_RXQ_CFG, reg); 4444 } 4445 } 4446 /* Disable TxQ. */ 4447 reg = CSR_READ_4(sc, ALC_TXQ_CFG); 4448 if ((reg & TXQ_CFG_ENB) != 0) { 4449 reg &= ~TXQ_CFG_ENB; 4450 CSR_WRITE_4(sc, ALC_TXQ_CFG, reg); 4451 } 4452 DELAY(40); 4453 for (i = ALC_TIMEOUT; i > 0; i--) { 4454 reg = CSR_READ_4(sc, ALC_IDLE_STATUS); 4455 if ((reg & (IDLE_STATUS_RXQ | IDLE_STATUS_TXQ)) == 0) 4456 break; 4457 DELAY(10); 4458 } 4459 if (i == 0) 4460 device_printf(sc->alc_dev, 4461 "could not disable RxQ/TxQ (0x%08x)!\n", reg); 4462 } 4463 4464 static void 4465 alc_init_tx_ring(struct alc_softc *sc) 4466 { 4467 struct alc_ring_data *rd; 4468 struct alc_txdesc *txd; 4469 int i; 4470 4471 ALC_LOCK_ASSERT(sc); 4472 4473 sc->alc_cdata.alc_tx_prod = 0; 4474 sc->alc_cdata.alc_tx_cons = 0; 4475 sc->alc_cdata.alc_tx_cnt = 0; 4476 4477 rd = &sc->alc_rdata; 4478 bzero(rd->alc_tx_ring, ALC_TX_RING_SZ); 4479 for (i = 0; i < ALC_TX_RING_CNT; i++) { 4480 txd = &sc->alc_cdata.alc_txdesc[i]; 4481 txd->tx_m = NULL; 4482 } 4483 4484 bus_dmamap_sync(sc->alc_cdata.alc_tx_ring_tag, 4485 sc->alc_cdata.alc_tx_ring_map, BUS_DMASYNC_PREWRITE); 4486 } 4487 4488 static int 4489 alc_init_rx_ring(struct alc_softc *sc) 4490 { 4491 struct alc_ring_data *rd; 4492 struct alc_rxdesc *rxd; 4493 int i; 4494 4495 ALC_LOCK_ASSERT(sc); 4496 4497 sc->alc_cdata.alc_rx_cons = ALC_RX_RING_CNT - 1; 4498 sc->alc_morework = 0; 4499 rd = &sc->alc_rdata; 4500 bzero(rd->alc_rx_ring, ALC_RX_RING_SZ); 4501 for (i = 0; i < ALC_RX_RING_CNT; i++) { 4502 rxd = &sc->alc_cdata.alc_rxdesc[i]; 4503 rxd->rx_m = NULL; 4504 rxd->rx_desc = &rd->alc_rx_ring[i]; 4505 if (alc_newbuf(sc, rxd) != 0) 4506 return (ENOBUFS); 4507 } 4508 4509 /* 4510 * Since controller does not update Rx descriptors, driver 4511 * does have to read Rx descriptors back so BUS_DMASYNC_PREWRITE 4512 * is enough to ensure coherence. 4513 */ 4514 bus_dmamap_sync(sc->alc_cdata.alc_rx_ring_tag, 4515 sc->alc_cdata.alc_rx_ring_map, BUS_DMASYNC_PREWRITE); 4516 /* Let controller know availability of new Rx buffers. */ 4517 CSR_WRITE_4(sc, ALC_MBOX_RD0_PROD_IDX, sc->alc_cdata.alc_rx_cons); 4518 4519 return (0); 4520 } 4521 4522 static void 4523 alc_init_rr_ring(struct alc_softc *sc) 4524 { 4525 struct alc_ring_data *rd; 4526 4527 ALC_LOCK_ASSERT(sc); 4528 4529 sc->alc_cdata.alc_rr_cons = 0; 4530 ALC_RXCHAIN_RESET(sc); 4531 4532 rd = &sc->alc_rdata; 4533 bzero(rd->alc_rr_ring, ALC_RR_RING_SZ); 4534 bus_dmamap_sync(sc->alc_cdata.alc_rr_ring_tag, 4535 sc->alc_cdata.alc_rr_ring_map, 4536 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4537 } 4538 4539 static void 4540 alc_init_cmb(struct alc_softc *sc) 4541 { 4542 struct alc_ring_data *rd; 4543 4544 ALC_LOCK_ASSERT(sc); 4545 4546 rd = &sc->alc_rdata; 4547 bzero(rd->alc_cmb, ALC_CMB_SZ); 4548 bus_dmamap_sync(sc->alc_cdata.alc_cmb_tag, sc->alc_cdata.alc_cmb_map, 4549 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4550 } 4551 4552 static void 4553 alc_init_smb(struct alc_softc *sc) 4554 { 4555 struct alc_ring_data *rd; 4556 4557 ALC_LOCK_ASSERT(sc); 4558 4559 rd = &sc->alc_rdata; 4560 bzero(rd->alc_smb, ALC_SMB_SZ); 4561 bus_dmamap_sync(sc->alc_cdata.alc_smb_tag, sc->alc_cdata.alc_smb_map, 4562 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 4563 } 4564 4565 static void 4566 alc_rxvlan(struct alc_softc *sc) 4567 { 4568 struct ifnet *ifp; 4569 uint32_t reg; 4570 4571 ALC_LOCK_ASSERT(sc); 4572 4573 ifp = sc->alc_ifp; 4574 reg = CSR_READ_4(sc, ALC_MAC_CFG); 4575 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 4576 reg |= MAC_CFG_VLAN_TAG_STRIP; 4577 else 4578 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 4579 CSR_WRITE_4(sc, ALC_MAC_CFG, reg); 4580 } 4581 4582 static void 4583 alc_rxfilter(struct alc_softc *sc) 4584 { 4585 struct ifnet *ifp; 4586 struct ifmultiaddr *ifma; 4587 uint32_t crc; 4588 uint32_t mchash[2]; 4589 uint32_t rxcfg; 4590 4591 ALC_LOCK_ASSERT(sc); 4592 4593 ifp = sc->alc_ifp; 4594 4595 bzero(mchash, sizeof(mchash)); 4596 rxcfg = CSR_READ_4(sc, ALC_MAC_CFG); 4597 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 4598 if ((ifp->if_flags & IFF_BROADCAST) != 0) 4599 rxcfg |= MAC_CFG_BCAST; 4600 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 4601 if ((ifp->if_flags & IFF_PROMISC) != 0) 4602 rxcfg |= MAC_CFG_PROMISC; 4603 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 4604 rxcfg |= MAC_CFG_ALLMULTI; 4605 mchash[0] = 0xFFFFFFFF; 4606 mchash[1] = 0xFFFFFFFF; 4607 goto chipit; 4608 } 4609 4610 if_maddr_rlock(ifp); 4611 TAILQ_FOREACH(ifma, &sc->alc_ifp->if_multiaddrs, ifma_link) { 4612 if (ifma->ifma_addr->sa_family != AF_LINK) 4613 continue; 4614 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 4615 ifma->ifma_addr), ETHER_ADDR_LEN); 4616 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 4617 } 4618 if_maddr_runlock(ifp); 4619 4620 chipit: 4621 CSR_WRITE_4(sc, ALC_MAR0, mchash[0]); 4622 CSR_WRITE_4(sc, ALC_MAR1, mchash[1]); 4623 CSR_WRITE_4(sc, ALC_MAC_CFG, rxcfg); 4624 } 4625 4626 static int 4627 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4628 { 4629 int error, value; 4630 4631 if (arg1 == NULL) 4632 return (EINVAL); 4633 value = *(int *)arg1; 4634 error = sysctl_handle_int(oidp, &value, 0, req); 4635 if (error || req->newptr == NULL) 4636 return (error); 4637 if (value < low || value > high) 4638 return (EINVAL); 4639 *(int *)arg1 = value; 4640 4641 return (0); 4642 } 4643 4644 static int 4645 sysctl_hw_alc_proc_limit(SYSCTL_HANDLER_ARGS) 4646 { 4647 return (sysctl_int_range(oidp, arg1, arg2, req, 4648 ALC_PROC_MIN, ALC_PROC_MAX)); 4649 } 4650 4651 static int 4652 sysctl_hw_alc_int_mod(SYSCTL_HANDLER_ARGS) 4653 { 4654 4655 return (sysctl_int_range(oidp, arg1, arg2, req, 4656 ALC_IM_TIMER_MIN, ALC_IM_TIMER_MAX)); 4657 } 4658 4659 #ifdef NETDUMP 4660 static void 4661 alc_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 4662 { 4663 struct alc_softc *sc; 4664 4665 sc = if_getsoftc(ifp); 4666 KASSERT(sc->alc_buf_size <= MCLBYTES, ("incorrect cluster size")); 4667 4668 *nrxr = ALC_RX_RING_CNT; 4669 *ncl = NETDUMP_MAX_IN_FLIGHT; 4670 *clsize = MCLBYTES; 4671 } 4672 4673 static void 4674 alc_netdump_event(struct ifnet *ifp __unused, enum netdump_ev event __unused) 4675 { 4676 } 4677 4678 static int 4679 alc_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 4680 { 4681 struct alc_softc *sc; 4682 int error; 4683 4684 sc = if_getsoftc(ifp); 4685 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4686 IFF_DRV_RUNNING) 4687 return (EBUSY); 4688 4689 error = alc_encap(sc, &m); 4690 if (error == 0) 4691 alc_start_tx(sc); 4692 return (error); 4693 } 4694 4695 static int 4696 alc_netdump_poll(struct ifnet *ifp, int count) 4697 { 4698 struct alc_softc *sc; 4699 4700 sc = if_getsoftc(ifp); 4701 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 4702 IFF_DRV_RUNNING) 4703 return (EBUSY); 4704 4705 alc_txeof(sc); 4706 return (alc_rxintr(sc, count)); 4707 } 4708 #endif /* NETDUMP */ 4709