1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/mbuf.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/ale/if_alereg.h> 76 #include <dev/ale/if_alevar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 /* For more information about Tx checksum offload issues see ale_encap(). */ 82 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 84 MODULE_DEPEND(ale, pci, 1, 1, 1); 85 MODULE_DEPEND(ale, ether, 1, 1, 1); 86 MODULE_DEPEND(ale, miibus, 1, 1, 1); 87 88 /* Tunables. */ 89 static int msi_disable = 0; 90 static int msix_disable = 0; 91 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 92 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 93 94 /* 95 * Devices supported by this driver. 96 */ 97 static const struct ale_dev { 98 uint16_t ale_vendorid; 99 uint16_t ale_deviceid; 100 const char *ale_name; 101 } ale_devs[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 103 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 104 }; 105 106 static int ale_attach(device_t); 107 static int ale_check_boundary(struct ale_softc *); 108 static int ale_detach(device_t); 109 static int ale_dma_alloc(struct ale_softc *); 110 static void ale_dma_free(struct ale_softc *); 111 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 112 static int ale_encap(struct ale_softc *, struct mbuf **); 113 static void ale_get_macaddr(struct ale_softc *); 114 static void ale_init(void *); 115 static void ale_init_locked(struct ale_softc *); 116 static void ale_init_rx_pages(struct ale_softc *); 117 static void ale_init_tx_ring(struct ale_softc *); 118 static void ale_int_task(void *, int); 119 static int ale_intr(void *); 120 static int ale_ioctl(struct ifnet *, u_long, caddr_t); 121 static void ale_mac_config(struct ale_softc *); 122 static int ale_miibus_readreg(device_t, int, int); 123 static void ale_miibus_statchg(device_t); 124 static int ale_miibus_writereg(device_t, int, int, int); 125 static int ale_mediachange(struct ifnet *); 126 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 127 static void ale_phy_reset(struct ale_softc *); 128 static int ale_probe(device_t); 129 static void ale_reset(struct ale_softc *); 130 static int ale_resume(device_t); 131 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 132 uint32_t, uint32_t *); 133 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 134 static int ale_rxeof(struct ale_softc *sc, int); 135 static void ale_rxfilter(struct ale_softc *); 136 static void ale_rxvlan(struct ale_softc *); 137 static void ale_setlinkspeed(struct ale_softc *); 138 static void ale_setwol(struct ale_softc *); 139 static int ale_shutdown(device_t); 140 static void ale_start(struct ifnet *); 141 static void ale_start_locked(struct ifnet *); 142 static void ale_stats_clear(struct ale_softc *); 143 static void ale_stats_update(struct ale_softc *); 144 static void ale_stop(struct ale_softc *); 145 static void ale_stop_mac(struct ale_softc *); 146 static int ale_suspend(device_t); 147 static void ale_sysctl_node(struct ale_softc *); 148 static void ale_tick(void *); 149 static void ale_txeof(struct ale_softc *); 150 static void ale_watchdog(struct ale_softc *); 151 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 152 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 153 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 154 155 static device_method_t ale_methods[] = { 156 /* Device interface. */ 157 DEVMETHOD(device_probe, ale_probe), 158 DEVMETHOD(device_attach, ale_attach), 159 DEVMETHOD(device_detach, ale_detach), 160 DEVMETHOD(device_shutdown, ale_shutdown), 161 DEVMETHOD(device_suspend, ale_suspend), 162 DEVMETHOD(device_resume, ale_resume), 163 164 /* MII interface. */ 165 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 166 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 167 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 168 169 DEVMETHOD_END 170 }; 171 172 static driver_t ale_driver = { 173 "ale", 174 ale_methods, 175 sizeof(struct ale_softc) 176 }; 177 178 static devclass_t ale_devclass; 179 180 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 181 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 182 183 static struct resource_spec ale_res_spec_mem[] = { 184 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 185 { -1, 0, 0 } 186 }; 187 188 static struct resource_spec ale_irq_spec_legacy[] = { 189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 190 { -1, 0, 0 } 191 }; 192 193 static struct resource_spec ale_irq_spec_msi[] = { 194 { SYS_RES_IRQ, 1, RF_ACTIVE }, 195 { -1, 0, 0 } 196 }; 197 198 static struct resource_spec ale_irq_spec_msix[] = { 199 { SYS_RES_IRQ, 1, RF_ACTIVE }, 200 { -1, 0, 0 } 201 }; 202 203 static int 204 ale_miibus_readreg(device_t dev, int phy, int reg) 205 { 206 struct ale_softc *sc; 207 uint32_t v; 208 int i; 209 210 sc = device_get_softc(dev); 211 212 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 213 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 214 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 215 DELAY(5); 216 v = CSR_READ_4(sc, ALE_MDIO); 217 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 218 break; 219 } 220 221 if (i == 0) { 222 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 223 return (0); 224 } 225 226 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 227 } 228 229 static int 230 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 231 { 232 struct ale_softc *sc; 233 uint32_t v; 234 int i; 235 236 sc = device_get_softc(dev); 237 238 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 239 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 240 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 241 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 242 DELAY(5); 243 v = CSR_READ_4(sc, ALE_MDIO); 244 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 245 break; 246 } 247 248 if (i == 0) 249 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 250 251 return (0); 252 } 253 254 static void 255 ale_miibus_statchg(device_t dev) 256 { 257 struct ale_softc *sc; 258 struct mii_data *mii; 259 struct ifnet *ifp; 260 uint32_t reg; 261 262 sc = device_get_softc(dev); 263 mii = device_get_softc(sc->ale_miibus); 264 ifp = sc->ale_ifp; 265 if (mii == NULL || ifp == NULL || 266 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 267 return; 268 269 sc->ale_flags &= ~ALE_FLAG_LINK; 270 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 271 (IFM_ACTIVE | IFM_AVALID)) { 272 switch (IFM_SUBTYPE(mii->mii_media_active)) { 273 case IFM_10_T: 274 case IFM_100_TX: 275 sc->ale_flags |= ALE_FLAG_LINK; 276 break; 277 case IFM_1000_T: 278 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 279 sc->ale_flags |= ALE_FLAG_LINK; 280 break; 281 default: 282 break; 283 } 284 } 285 286 /* Stop Rx/Tx MACs. */ 287 ale_stop_mac(sc); 288 289 /* Program MACs with resolved speed/duplex/flow-control. */ 290 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 291 ale_mac_config(sc); 292 /* Reenable Tx/Rx MACs. */ 293 reg = CSR_READ_4(sc, ALE_MAC_CFG); 294 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 295 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 296 } 297 } 298 299 static void 300 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 301 { 302 struct ale_softc *sc; 303 struct mii_data *mii; 304 305 sc = ifp->if_softc; 306 ALE_LOCK(sc); 307 if ((ifp->if_flags & IFF_UP) == 0) { 308 ALE_UNLOCK(sc); 309 return; 310 } 311 mii = device_get_softc(sc->ale_miibus); 312 313 mii_pollstat(mii); 314 ifmr->ifm_status = mii->mii_media_status; 315 ifmr->ifm_active = mii->mii_media_active; 316 ALE_UNLOCK(sc); 317 } 318 319 static int 320 ale_mediachange(struct ifnet *ifp) 321 { 322 struct ale_softc *sc; 323 struct mii_data *mii; 324 struct mii_softc *miisc; 325 int error; 326 327 sc = ifp->if_softc; 328 ALE_LOCK(sc); 329 mii = device_get_softc(sc->ale_miibus); 330 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 331 PHY_RESET(miisc); 332 error = mii_mediachg(mii); 333 ALE_UNLOCK(sc); 334 335 return (error); 336 } 337 338 static int 339 ale_probe(device_t dev) 340 { 341 const struct ale_dev *sp; 342 int i; 343 uint16_t vendor, devid; 344 345 vendor = pci_get_vendor(dev); 346 devid = pci_get_device(dev); 347 sp = ale_devs; 348 for (i = 0; i < nitems(ale_devs); i++) { 349 if (vendor == sp->ale_vendorid && 350 devid == sp->ale_deviceid) { 351 device_set_desc(dev, sp->ale_name); 352 return (BUS_PROBE_DEFAULT); 353 } 354 sp++; 355 } 356 357 return (ENXIO); 358 } 359 360 static void 361 ale_get_macaddr(struct ale_softc *sc) 362 { 363 uint32_t ea[2], reg; 364 int i, vpdc; 365 366 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 367 if ((reg & SPI_VPD_ENB) != 0) { 368 reg &= ~SPI_VPD_ENB; 369 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 370 } 371 372 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 373 /* 374 * PCI VPD capability found, let TWSI reload EEPROM. 375 * This will set ethernet address of controller. 376 */ 377 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 378 TWSI_CTRL_SW_LD_START); 379 for (i = 100; i > 0; i--) { 380 DELAY(1000); 381 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 382 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 383 break; 384 } 385 if (i == 0) 386 device_printf(sc->ale_dev, 387 "reloading EEPROM timeout!\n"); 388 } else { 389 if (bootverbose) 390 device_printf(sc->ale_dev, 391 "PCI VPD capability not found!\n"); 392 } 393 394 ea[0] = CSR_READ_4(sc, ALE_PAR0); 395 ea[1] = CSR_READ_4(sc, ALE_PAR1); 396 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 397 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 398 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 399 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 400 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 401 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 402 } 403 404 static void 405 ale_phy_reset(struct ale_softc *sc) 406 { 407 408 /* Reset magic from Linux. */ 409 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 410 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 411 GPHY_CTRL_PHY_PLL_ON); 412 DELAY(1000); 413 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 414 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 415 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 416 DELAY(1000); 417 418 #define ATPHY_DBG_ADDR 0x1D 419 #define ATPHY_DBG_DATA 0x1E 420 421 /* Enable hibernation mode. */ 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_ADDR, 0x0B); 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_DATA, 0xBC00); 426 /* Set Class A/B for all modes. */ 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_ADDR, 0x00); 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_DATA, 0x02EF); 431 /* Enable 10BT power saving. */ 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_ADDR, 0x12); 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_DATA, 0x4C04); 436 /* Adjust 1000T power. */ 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x04); 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x8BBB); 441 /* 10BT center tap voltage. */ 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x05); 444 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 445 ATPHY_DBG_ADDR, 0x2C46); 446 447 #undef ATPHY_DBG_ADDR 448 #undef ATPHY_DBG_DATA 449 DELAY(1000); 450 } 451 452 static int 453 ale_attach(device_t dev) 454 { 455 struct ale_softc *sc; 456 struct ifnet *ifp; 457 uint16_t burst; 458 int error, i, msic, msixc, pmc; 459 uint32_t rxf_len, txf_len; 460 461 error = 0; 462 sc = device_get_softc(dev); 463 sc->ale_dev = dev; 464 465 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 466 MTX_DEF); 467 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 468 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 469 470 /* Map the device. */ 471 pci_enable_busmaster(dev); 472 sc->ale_res_spec = ale_res_spec_mem; 473 sc->ale_irq_spec = ale_irq_spec_legacy; 474 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 475 if (error != 0) { 476 device_printf(dev, "cannot allocate memory resources.\n"); 477 goto fail; 478 } 479 480 /* Set PHY address. */ 481 sc->ale_phyaddr = ALE_PHY_ADDR; 482 483 /* Reset PHY. */ 484 ale_phy_reset(sc); 485 486 /* Reset the ethernet controller. */ 487 ale_reset(sc); 488 489 /* Get PCI and chip id/revision. */ 490 sc->ale_rev = pci_get_revid(dev); 491 if (sc->ale_rev >= 0xF0) { 492 /* L2E Rev. B. AR8114 */ 493 sc->ale_flags |= ALE_FLAG_FASTETHER; 494 } else { 495 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 496 /* L1E AR8121 */ 497 sc->ale_flags |= ALE_FLAG_JUMBO; 498 } else { 499 /* L2E Rev. A. AR8113 */ 500 sc->ale_flags |= ALE_FLAG_FASTETHER; 501 } 502 } 503 /* 504 * All known controllers seems to require 4 bytes alignment 505 * of Tx buffers to make Tx checksum offload with custom 506 * checksum generation method work. 507 */ 508 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 509 /* 510 * All known controllers seems to have issues on Rx checksum 511 * offload for fragmented IP datagrams. 512 */ 513 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 514 /* 515 * Don't use Tx CMB. It is known to cause RRS update failure 516 * under certain circumstances. Typical phenomenon of the 517 * issue would be unexpected sequence number encountered in 518 * Rx handler. 519 */ 520 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 521 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 522 MASTER_CHIP_REV_SHIFT; 523 if (bootverbose) { 524 device_printf(dev, "PCI device revision : 0x%04x\n", 525 sc->ale_rev); 526 device_printf(dev, "Chip id/revision : 0x%04x\n", 527 sc->ale_chip_rev); 528 } 529 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 530 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 531 /* 532 * Uninitialized hardware returns an invalid chip id/revision 533 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 534 */ 535 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 536 rxf_len == 0xFFFFFFF) { 537 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 538 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 539 txf_len, rxf_len); 540 error = ENXIO; 541 goto fail; 542 } 543 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 544 545 /* Allocate IRQ resources. */ 546 msixc = pci_msix_count(dev); 547 msic = pci_msi_count(dev); 548 if (bootverbose) { 549 device_printf(dev, "MSIX count : %d\n", msixc); 550 device_printf(dev, "MSI count : %d\n", msic); 551 } 552 553 /* Prefer MSIX over MSI. */ 554 if (msix_disable == 0 || msi_disable == 0) { 555 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 556 pci_alloc_msix(dev, &msixc) == 0) { 557 if (msixc == ALE_MSIX_MESSAGES) { 558 device_printf(dev, "Using %d MSIX messages.\n", 559 msixc); 560 sc->ale_flags |= ALE_FLAG_MSIX; 561 sc->ale_irq_spec = ale_irq_spec_msix; 562 } else 563 pci_release_msi(dev); 564 } 565 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 566 msic == ALE_MSI_MESSAGES && 567 pci_alloc_msi(dev, &msic) == 0) { 568 if (msic == ALE_MSI_MESSAGES) { 569 device_printf(dev, "Using %d MSI messages.\n", 570 msic); 571 sc->ale_flags |= ALE_FLAG_MSI; 572 sc->ale_irq_spec = ale_irq_spec_msi; 573 } else 574 pci_release_msi(dev); 575 } 576 } 577 578 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 579 if (error != 0) { 580 device_printf(dev, "cannot allocate IRQ resources.\n"); 581 goto fail; 582 } 583 584 /* Get DMA parameters from PCIe device control register. */ 585 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 586 sc->ale_flags |= ALE_FLAG_PCIE; 587 burst = pci_read_config(dev, i + 0x08, 2); 588 /* Max read request size. */ 589 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 590 DMA_CFG_RD_BURST_SHIFT; 591 /* Max payload size. */ 592 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 593 DMA_CFG_WR_BURST_SHIFT; 594 if (bootverbose) { 595 device_printf(dev, "Read request size : %d bytes.\n", 596 128 << ((burst >> 12) & 0x07)); 597 device_printf(dev, "TLP payload size : %d bytes.\n", 598 128 << ((burst >> 5) & 0x07)); 599 } 600 } else { 601 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 602 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 603 } 604 605 /* Create device sysctl node. */ 606 ale_sysctl_node(sc); 607 608 if ((error = ale_dma_alloc(sc)) != 0) 609 goto fail; 610 611 /* Load station address. */ 612 ale_get_macaddr(sc); 613 614 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 615 if (ifp == NULL) { 616 device_printf(dev, "cannot allocate ifnet structure.\n"); 617 error = ENXIO; 618 goto fail; 619 } 620 621 ifp->if_softc = sc; 622 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 623 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 624 ifp->if_ioctl = ale_ioctl; 625 ifp->if_start = ale_start; 626 ifp->if_init = ale_init; 627 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 628 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 629 IFQ_SET_READY(&ifp->if_snd); 630 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 631 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 632 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 633 sc->ale_flags |= ALE_FLAG_PMCAP; 634 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 635 } 636 ifp->if_capenable = ifp->if_capabilities; 637 638 /* Set up MII bus. */ 639 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 640 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 641 MIIF_DOPAUSE); 642 if (error != 0) { 643 device_printf(dev, "attaching PHYs failed\n"); 644 goto fail; 645 } 646 647 ether_ifattach(ifp, sc->ale_eaddr); 648 649 /* VLAN capability setup. */ 650 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 651 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 652 ifp->if_capenable = ifp->if_capabilities; 653 /* 654 * Even though controllers supported by ale(3) have Rx checksum 655 * offload bug the workaround for fragmented frames seemed to 656 * work so far. However it seems Rx checksum offload does not 657 * work under certain conditions. So disable Rx checksum offload 658 * until I find more clue about it but allow users to override it. 659 */ 660 ifp->if_capenable &= ~IFCAP_RXCSUM; 661 662 /* Tell the upper layer(s) we support long frames. */ 663 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 664 665 /* Create local taskq. */ 666 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 667 taskqueue_thread_enqueue, &sc->ale_tq); 668 if (sc->ale_tq == NULL) { 669 device_printf(dev, "could not create taskqueue.\n"); 670 ether_ifdetach(ifp); 671 error = ENXIO; 672 goto fail; 673 } 674 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 675 device_get_nameunit(sc->ale_dev)); 676 677 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 678 msic = ALE_MSIX_MESSAGES; 679 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 680 msic = ALE_MSI_MESSAGES; 681 else 682 msic = 1; 683 for (i = 0; i < msic; i++) { 684 error = bus_setup_intr(dev, sc->ale_irq[i], 685 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 686 &sc->ale_intrhand[i]); 687 if (error != 0) 688 break; 689 } 690 if (error != 0) { 691 device_printf(dev, "could not set up interrupt handler.\n"); 692 taskqueue_free(sc->ale_tq); 693 sc->ale_tq = NULL; 694 ether_ifdetach(ifp); 695 goto fail; 696 } 697 698 fail: 699 if (error != 0) 700 ale_detach(dev); 701 702 return (error); 703 } 704 705 static int 706 ale_detach(device_t dev) 707 { 708 struct ale_softc *sc; 709 struct ifnet *ifp; 710 int i, msic; 711 712 sc = device_get_softc(dev); 713 714 ifp = sc->ale_ifp; 715 if (device_is_attached(dev)) { 716 ether_ifdetach(ifp); 717 ALE_LOCK(sc); 718 ale_stop(sc); 719 ALE_UNLOCK(sc); 720 callout_drain(&sc->ale_tick_ch); 721 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 722 } 723 724 if (sc->ale_tq != NULL) { 725 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 726 taskqueue_free(sc->ale_tq); 727 sc->ale_tq = NULL; 728 } 729 730 if (sc->ale_miibus != NULL) { 731 device_delete_child(dev, sc->ale_miibus); 732 sc->ale_miibus = NULL; 733 } 734 bus_generic_detach(dev); 735 ale_dma_free(sc); 736 737 if (ifp != NULL) { 738 if_free(ifp); 739 sc->ale_ifp = NULL; 740 } 741 742 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 743 msic = ALE_MSIX_MESSAGES; 744 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 745 msic = ALE_MSI_MESSAGES; 746 else 747 msic = 1; 748 for (i = 0; i < msic; i++) { 749 if (sc->ale_intrhand[i] != NULL) { 750 bus_teardown_intr(dev, sc->ale_irq[i], 751 sc->ale_intrhand[i]); 752 sc->ale_intrhand[i] = NULL; 753 } 754 } 755 756 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 757 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 758 pci_release_msi(dev); 759 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 760 mtx_destroy(&sc->ale_mtx); 761 762 return (0); 763 } 764 765 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 766 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 767 768 #if __FreeBSD_version >= 900030 769 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 770 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 771 #elif __FreeBSD_version > 800000 772 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 773 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 774 #else 775 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 776 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 777 #endif 778 779 static void 780 ale_sysctl_node(struct ale_softc *sc) 781 { 782 struct sysctl_ctx_list *ctx; 783 struct sysctl_oid_list *child, *parent; 784 struct sysctl_oid *tree; 785 struct ale_hw_stats *stats; 786 int error; 787 788 stats = &sc->ale_stats; 789 ctx = device_get_sysctl_ctx(sc->ale_dev); 790 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 791 792 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 793 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 794 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 795 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 796 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 797 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 798 /* Pull in device tunables. */ 799 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 800 error = resource_int_value(device_get_name(sc->ale_dev), 801 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 802 if (error == 0) { 803 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 804 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 805 device_printf(sc->ale_dev, "int_rx_mod value out of " 806 "range; using default: %d\n", 807 ALE_IM_RX_TIMER_DEFAULT); 808 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 809 } 810 } 811 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 812 error = resource_int_value(device_get_name(sc->ale_dev), 813 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 814 if (error == 0) { 815 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 816 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 817 device_printf(sc->ale_dev, "int_tx_mod value out of " 818 "range; using default: %d\n", 819 ALE_IM_TX_TIMER_DEFAULT); 820 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 821 } 822 } 823 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 824 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 825 sysctl_hw_ale_proc_limit, "I", 826 "max number of Rx events to process"); 827 /* Pull in device tunables. */ 828 sc->ale_process_limit = ALE_PROC_DEFAULT; 829 error = resource_int_value(device_get_name(sc->ale_dev), 830 device_get_unit(sc->ale_dev), "process_limit", 831 &sc->ale_process_limit); 832 if (error == 0) { 833 if (sc->ale_process_limit < ALE_PROC_MIN || 834 sc->ale_process_limit > ALE_PROC_MAX) { 835 device_printf(sc->ale_dev, 836 "process_limit value out of range; " 837 "using default: %d\n", ALE_PROC_DEFAULT); 838 sc->ale_process_limit = ALE_PROC_DEFAULT; 839 } 840 } 841 842 /* Misc statistics. */ 843 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 844 &stats->reset_brk_seq, 845 "Controller resets due to broken Rx sequnce number"); 846 847 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 848 NULL, "ATE statistics"); 849 parent = SYSCTL_CHILDREN(tree); 850 851 /* Rx statistics. */ 852 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 853 NULL, "Rx MAC statistics"); 854 child = SYSCTL_CHILDREN(tree); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 856 &stats->rx_frames, "Good frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 858 &stats->rx_bcast_frames, "Good broadcast frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 860 &stats->rx_mcast_frames, "Good multicast frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 862 &stats->rx_pause_frames, "Pause control frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 864 &stats->rx_control_frames, "Control frames"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 866 &stats->rx_crcerrs, "CRC errors"); 867 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 868 &stats->rx_lenerrs, "Frames with length mismatched"); 869 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 870 &stats->rx_bytes, "Good octets"); 871 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 872 &stats->rx_bcast_bytes, "Good broadcast octets"); 873 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 874 &stats->rx_mcast_bytes, "Good multicast octets"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 876 &stats->rx_runts, "Too short frames"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 878 &stats->rx_fragments, "Fragmented frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 880 &stats->rx_pkts_64, "64 bytes frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 882 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 884 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 886 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 888 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 890 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 892 &stats->rx_pkts_1519_max, "1519 to max frames"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 894 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 896 &stats->rx_fifo_oflows, "FIFO overflows"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 898 &stats->rx_rrs_errs, "Return status write-back errors"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 900 &stats->rx_alignerrs, "Alignment errors"); 901 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 902 &stats->rx_pkts_filtered, 903 "Frames dropped due to address filtering"); 904 905 /* Tx statistics. */ 906 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 907 NULL, "Tx MAC statistics"); 908 child = SYSCTL_CHILDREN(tree); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 910 &stats->tx_frames, "Good frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 912 &stats->tx_bcast_frames, "Good broadcast frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 914 &stats->tx_mcast_frames, "Good multicast frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 916 &stats->tx_pause_frames, "Pause control frames"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 918 &stats->tx_control_frames, "Control frames"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 920 &stats->tx_excess_defer, "Frames with excessive derferrals"); 921 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 922 &stats->tx_excess_defer, "Frames with derferrals"); 923 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 924 &stats->tx_bytes, "Good octets"); 925 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 926 &stats->tx_bcast_bytes, "Good broadcast octets"); 927 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 928 &stats->tx_mcast_bytes, "Good multicast octets"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 930 &stats->tx_pkts_64, "64 bytes frames"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 932 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 934 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 936 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 938 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 940 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 941 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 942 &stats->tx_pkts_1519_max, "1519 to max frames"); 943 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 944 &stats->tx_single_colls, "Single collisions"); 945 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 946 &stats->tx_multi_colls, "Multiple collisions"); 947 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 948 &stats->tx_late_colls, "Late collisions"); 949 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 950 &stats->tx_excess_colls, "Excessive collisions"); 951 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 952 &stats->tx_underrun, "FIFO underruns"); 953 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 954 &stats->tx_desc_underrun, "Descriptor write-back errors"); 955 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 956 &stats->tx_lenerrs, "Frames with length mismatched"); 957 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 958 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 959 } 960 961 #undef ALE_SYSCTL_STAT_ADD32 962 #undef ALE_SYSCTL_STAT_ADD64 963 964 struct ale_dmamap_arg { 965 bus_addr_t ale_busaddr; 966 }; 967 968 static void 969 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 970 { 971 struct ale_dmamap_arg *ctx; 972 973 if (error != 0) 974 return; 975 976 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 977 978 ctx = (struct ale_dmamap_arg *)arg; 979 ctx->ale_busaddr = segs[0].ds_addr; 980 } 981 982 /* 983 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 984 * which specifies high address region of DMA blocks. Therefore these 985 * blocks should have the same high address of given 4GB address 986 * space(i.e. crossing 4GB boundary is not allowed). 987 */ 988 static int 989 ale_check_boundary(struct ale_softc *sc) 990 { 991 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 992 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 993 994 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 995 sc->ale_pagesize; 996 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 997 sc->ale_pagesize; 998 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 999 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 1000 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 1001 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 1002 1003 if ((ALE_ADDR_HI(tx_ring_end) != 1004 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1005 (ALE_ADDR_HI(rx_page_end[0]) != 1006 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1007 (ALE_ADDR_HI(rx_page_end[1]) != 1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1009 (ALE_ADDR_HI(tx_cmb_end) != 1010 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1011 (ALE_ADDR_HI(rx_cmb_end[0]) != 1012 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1013 (ALE_ADDR_HI(rx_cmb_end[1]) != 1014 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1015 return (EFBIG); 1016 1017 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1021 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1022 return (EFBIG); 1023 1024 return (0); 1025 } 1026 1027 static int 1028 ale_dma_alloc(struct ale_softc *sc) 1029 { 1030 struct ale_txdesc *txd; 1031 bus_addr_t lowaddr; 1032 struct ale_dmamap_arg ctx; 1033 int error, guard_size, i; 1034 1035 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1036 guard_size = ALE_JUMBO_FRAMELEN; 1037 else 1038 guard_size = ALE_MAX_FRAMELEN; 1039 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1040 ALE_RX_PAGE_ALIGN); 1041 lowaddr = BUS_SPACE_MAXADDR; 1042 again: 1043 /* Create parent DMA tag. */ 1044 error = bus_dma_tag_create( 1045 bus_get_dma_tag(sc->ale_dev), /* parent */ 1046 1, 0, /* alignment, boundary */ 1047 lowaddr, /* lowaddr */ 1048 BUS_SPACE_MAXADDR, /* highaddr */ 1049 NULL, NULL, /* filter, filterarg */ 1050 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1051 0, /* nsegments */ 1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1053 0, /* flags */ 1054 NULL, NULL, /* lockfunc, lockarg */ 1055 &sc->ale_cdata.ale_parent_tag); 1056 if (error != 0) { 1057 device_printf(sc->ale_dev, 1058 "could not create parent DMA tag.\n"); 1059 goto fail; 1060 } 1061 1062 /* Create DMA tag for Tx descriptor ring. */ 1063 error = bus_dma_tag_create( 1064 sc->ale_cdata.ale_parent_tag, /* parent */ 1065 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1066 BUS_SPACE_MAXADDR, /* lowaddr */ 1067 BUS_SPACE_MAXADDR, /* highaddr */ 1068 NULL, NULL, /* filter, filterarg */ 1069 ALE_TX_RING_SZ, /* maxsize */ 1070 1, /* nsegments */ 1071 ALE_TX_RING_SZ, /* maxsegsize */ 1072 0, /* flags */ 1073 NULL, NULL, /* lockfunc, lockarg */ 1074 &sc->ale_cdata.ale_tx_ring_tag); 1075 if (error != 0) { 1076 device_printf(sc->ale_dev, 1077 "could not create Tx ring DMA tag.\n"); 1078 goto fail; 1079 } 1080 1081 /* Create DMA tag for Rx pages. */ 1082 for (i = 0; i < ALE_RX_PAGES; i++) { 1083 error = bus_dma_tag_create( 1084 sc->ale_cdata.ale_parent_tag, /* parent */ 1085 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1086 BUS_SPACE_MAXADDR, /* lowaddr */ 1087 BUS_SPACE_MAXADDR, /* highaddr */ 1088 NULL, NULL, /* filter, filterarg */ 1089 sc->ale_pagesize, /* maxsize */ 1090 1, /* nsegments */ 1091 sc->ale_pagesize, /* maxsegsize */ 1092 0, /* flags */ 1093 NULL, NULL, /* lockfunc, lockarg */ 1094 &sc->ale_cdata.ale_rx_page[i].page_tag); 1095 if (error != 0) { 1096 device_printf(sc->ale_dev, 1097 "could not create Rx page %d DMA tag.\n", i); 1098 goto fail; 1099 } 1100 } 1101 1102 /* Create DMA tag for Tx coalescing message block. */ 1103 error = bus_dma_tag_create( 1104 sc->ale_cdata.ale_parent_tag, /* parent */ 1105 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 ALE_TX_CMB_SZ, /* maxsize */ 1110 1, /* nsegments */ 1111 ALE_TX_CMB_SZ, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ale_cdata.ale_tx_cmb_tag); 1115 if (error != 0) { 1116 device_printf(sc->ale_dev, 1117 "could not create Tx CMB DMA tag.\n"); 1118 goto fail; 1119 } 1120 1121 /* Create DMA tag for Rx coalescing message block. */ 1122 for (i = 0; i < ALE_RX_PAGES; i++) { 1123 error = bus_dma_tag_create( 1124 sc->ale_cdata.ale_parent_tag, /* parent */ 1125 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1126 BUS_SPACE_MAXADDR, /* lowaddr */ 1127 BUS_SPACE_MAXADDR, /* highaddr */ 1128 NULL, NULL, /* filter, filterarg */ 1129 ALE_RX_CMB_SZ, /* maxsize */ 1130 1, /* nsegments */ 1131 ALE_RX_CMB_SZ, /* maxsegsize */ 1132 0, /* flags */ 1133 NULL, NULL, /* lockfunc, lockarg */ 1134 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1135 if (error != 0) { 1136 device_printf(sc->ale_dev, 1137 "could not create Rx page %d CMB DMA tag.\n", i); 1138 goto fail; 1139 } 1140 } 1141 1142 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1143 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1144 (void **)&sc->ale_cdata.ale_tx_ring, 1145 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1146 &sc->ale_cdata.ale_tx_ring_map); 1147 if (error != 0) { 1148 device_printf(sc->ale_dev, 1149 "could not allocate DMA'able memory for Tx ring.\n"); 1150 goto fail; 1151 } 1152 ctx.ale_busaddr = 0; 1153 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1154 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1155 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1156 if (error != 0 || ctx.ale_busaddr == 0) { 1157 device_printf(sc->ale_dev, 1158 "could not load DMA'able memory for Tx ring.\n"); 1159 goto fail; 1160 } 1161 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1162 1163 /* Rx pages. */ 1164 for (i = 0; i < ALE_RX_PAGES; i++) { 1165 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1166 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1167 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1168 &sc->ale_cdata.ale_rx_page[i].page_map); 1169 if (error != 0) { 1170 device_printf(sc->ale_dev, 1171 "could not allocate DMA'able memory for " 1172 "Rx page %d.\n", i); 1173 goto fail; 1174 } 1175 ctx.ale_busaddr = 0; 1176 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1177 sc->ale_cdata.ale_rx_page[i].page_map, 1178 sc->ale_cdata.ale_rx_page[i].page_addr, 1179 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1180 if (error != 0 || ctx.ale_busaddr == 0) { 1181 device_printf(sc->ale_dev, 1182 "could not load DMA'able memory for " 1183 "Rx page %d.\n", i); 1184 goto fail; 1185 } 1186 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1187 } 1188 1189 /* Tx CMB. */ 1190 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1191 (void **)&sc->ale_cdata.ale_tx_cmb, 1192 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1193 &sc->ale_cdata.ale_tx_cmb_map); 1194 if (error != 0) { 1195 device_printf(sc->ale_dev, 1196 "could not allocate DMA'able memory for Tx CMB.\n"); 1197 goto fail; 1198 } 1199 ctx.ale_busaddr = 0; 1200 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1201 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1202 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1203 if (error != 0 || ctx.ale_busaddr == 0) { 1204 device_printf(sc->ale_dev, 1205 "could not load DMA'able memory for Tx CMB.\n"); 1206 goto fail; 1207 } 1208 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1209 1210 /* Rx CMB. */ 1211 for (i = 0; i < ALE_RX_PAGES; i++) { 1212 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1213 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1214 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1215 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1216 if (error != 0) { 1217 device_printf(sc->ale_dev, "could not allocate " 1218 "DMA'able memory for Rx page %d CMB.\n", i); 1219 goto fail; 1220 } 1221 ctx.ale_busaddr = 0; 1222 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1223 sc->ale_cdata.ale_rx_page[i].cmb_map, 1224 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1225 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1226 if (error != 0 || ctx.ale_busaddr == 0) { 1227 device_printf(sc->ale_dev, "could not load DMA'able " 1228 "memory for Rx page %d CMB.\n", i); 1229 goto fail; 1230 } 1231 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1232 } 1233 1234 /* 1235 * Tx descriptors/RXF0/CMB DMA blocks share the same 1236 * high address region of 64bit DMA address space. 1237 */ 1238 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1239 (error = ale_check_boundary(sc)) != 0) { 1240 device_printf(sc->ale_dev, "4GB boundary crossed, " 1241 "switching to 32bit DMA addressing mode.\n"); 1242 ale_dma_free(sc); 1243 /* 1244 * Limit max allowable DMA address space to 32bit 1245 * and try again. 1246 */ 1247 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1248 goto again; 1249 } 1250 1251 /* 1252 * Create Tx buffer parent tag. 1253 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1254 * needs separate parent DMA tag as parent DMA address space 1255 * could be restricted to be within 32bit address space by 1256 * 4GB boundary crossing. 1257 */ 1258 error = bus_dma_tag_create( 1259 bus_get_dma_tag(sc->ale_dev), /* parent */ 1260 1, 0, /* alignment, boundary */ 1261 BUS_SPACE_MAXADDR, /* lowaddr */ 1262 BUS_SPACE_MAXADDR, /* highaddr */ 1263 NULL, NULL, /* filter, filterarg */ 1264 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1265 0, /* nsegments */ 1266 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1267 0, /* flags */ 1268 NULL, NULL, /* lockfunc, lockarg */ 1269 &sc->ale_cdata.ale_buffer_tag); 1270 if (error != 0) { 1271 device_printf(sc->ale_dev, 1272 "could not create parent buffer DMA tag.\n"); 1273 goto fail; 1274 } 1275 1276 /* Create DMA tag for Tx buffers. */ 1277 error = bus_dma_tag_create( 1278 sc->ale_cdata.ale_buffer_tag, /* parent */ 1279 1, 0, /* alignment, boundary */ 1280 BUS_SPACE_MAXADDR, /* lowaddr */ 1281 BUS_SPACE_MAXADDR, /* highaddr */ 1282 NULL, NULL, /* filter, filterarg */ 1283 ALE_TSO_MAXSIZE, /* maxsize */ 1284 ALE_MAXTXSEGS, /* nsegments */ 1285 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1286 0, /* flags */ 1287 NULL, NULL, /* lockfunc, lockarg */ 1288 &sc->ale_cdata.ale_tx_tag); 1289 if (error != 0) { 1290 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1291 goto fail; 1292 } 1293 1294 /* Create DMA maps for Tx buffers. */ 1295 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1296 txd = &sc->ale_cdata.ale_txdesc[i]; 1297 txd->tx_m = NULL; 1298 txd->tx_dmamap = NULL; 1299 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1300 &txd->tx_dmamap); 1301 if (error != 0) { 1302 device_printf(sc->ale_dev, 1303 "could not create Tx dmamap.\n"); 1304 goto fail; 1305 } 1306 } 1307 1308 fail: 1309 return (error); 1310 } 1311 1312 static void 1313 ale_dma_free(struct ale_softc *sc) 1314 { 1315 struct ale_txdesc *txd; 1316 int i; 1317 1318 /* Tx buffers. */ 1319 if (sc->ale_cdata.ale_tx_tag != NULL) { 1320 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1321 txd = &sc->ale_cdata.ale_txdesc[i]; 1322 if (txd->tx_dmamap != NULL) { 1323 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1324 txd->tx_dmamap); 1325 txd->tx_dmamap = NULL; 1326 } 1327 } 1328 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1329 sc->ale_cdata.ale_tx_tag = NULL; 1330 } 1331 /* Tx descriptor ring. */ 1332 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1333 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1334 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1335 sc->ale_cdata.ale_tx_ring_map); 1336 if (sc->ale_cdata.ale_tx_ring != NULL) 1337 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1338 sc->ale_cdata.ale_tx_ring, 1339 sc->ale_cdata.ale_tx_ring_map); 1340 sc->ale_cdata.ale_tx_ring_paddr = 0; 1341 sc->ale_cdata.ale_tx_ring = NULL; 1342 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1343 sc->ale_cdata.ale_tx_ring_tag = NULL; 1344 } 1345 /* Rx page block. */ 1346 for (i = 0; i < ALE_RX_PAGES; i++) { 1347 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1348 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1349 bus_dmamap_unload( 1350 sc->ale_cdata.ale_rx_page[i].page_tag, 1351 sc->ale_cdata.ale_rx_page[i].page_map); 1352 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1353 bus_dmamem_free( 1354 sc->ale_cdata.ale_rx_page[i].page_tag, 1355 sc->ale_cdata.ale_rx_page[i].page_addr, 1356 sc->ale_cdata.ale_rx_page[i].page_map); 1357 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1358 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1359 bus_dma_tag_destroy( 1360 sc->ale_cdata.ale_rx_page[i].page_tag); 1361 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1362 } 1363 } 1364 /* Rx CMB. */ 1365 for (i = 0; i < ALE_RX_PAGES; i++) { 1366 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1367 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1368 bus_dmamap_unload( 1369 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1370 sc->ale_cdata.ale_rx_page[i].cmb_map); 1371 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1372 bus_dmamem_free( 1373 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1374 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1375 sc->ale_cdata.ale_rx_page[i].cmb_map); 1376 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1377 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1378 bus_dma_tag_destroy( 1379 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1380 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1381 } 1382 } 1383 /* Tx CMB. */ 1384 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1385 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1386 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1387 sc->ale_cdata.ale_tx_cmb_map); 1388 if (sc->ale_cdata.ale_tx_cmb != NULL) 1389 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1390 sc->ale_cdata.ale_tx_cmb, 1391 sc->ale_cdata.ale_tx_cmb_map); 1392 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1393 sc->ale_cdata.ale_tx_cmb = NULL; 1394 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1395 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1396 } 1397 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1398 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1399 sc->ale_cdata.ale_buffer_tag = NULL; 1400 } 1401 if (sc->ale_cdata.ale_parent_tag != NULL) { 1402 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1403 sc->ale_cdata.ale_parent_tag = NULL; 1404 } 1405 } 1406 1407 static int 1408 ale_shutdown(device_t dev) 1409 { 1410 1411 return (ale_suspend(dev)); 1412 } 1413 1414 /* 1415 * Note, this driver resets the link speed to 10/100Mbps by 1416 * restarting auto-negotiation in suspend/shutdown phase but we 1417 * don't know whether that auto-negotiation would succeed or not 1418 * as driver has no control after powering off/suspend operation. 1419 * If the renegotiation fail WOL may not work. Running at 1Gbps 1420 * will draw more power than 375mA at 3.3V which is specified in 1421 * PCI specification and that would result in complete 1422 * shutdowning power to ethernet controller. 1423 * 1424 * TODO 1425 * Save current negotiated media speed/duplex/flow-control to 1426 * softc and restore the same link again after resuming. PHY 1427 * handling such as power down/resetting to 100Mbps may be better 1428 * handled in suspend method in phy driver. 1429 */ 1430 static void 1431 ale_setlinkspeed(struct ale_softc *sc) 1432 { 1433 struct mii_data *mii; 1434 int aneg, i; 1435 1436 mii = device_get_softc(sc->ale_miibus); 1437 mii_pollstat(mii); 1438 aneg = 0; 1439 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1440 (IFM_ACTIVE | IFM_AVALID)) { 1441 switch IFM_SUBTYPE(mii->mii_media_active) { 1442 case IFM_10_T: 1443 case IFM_100_TX: 1444 return; 1445 case IFM_1000_T: 1446 aneg++; 1447 break; 1448 default: 1449 break; 1450 } 1451 } 1452 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1453 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1454 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1455 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1456 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1457 DELAY(1000); 1458 if (aneg != 0) { 1459 /* 1460 * Poll link state until ale(4) get a 10/100Mbps link. 1461 */ 1462 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1463 mii_pollstat(mii); 1464 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1465 == (IFM_ACTIVE | IFM_AVALID)) { 1466 switch (IFM_SUBTYPE( 1467 mii->mii_media_active)) { 1468 case IFM_10_T: 1469 case IFM_100_TX: 1470 ale_mac_config(sc); 1471 return; 1472 default: 1473 break; 1474 } 1475 } 1476 ALE_UNLOCK(sc); 1477 pause("alelnk", hz); 1478 ALE_LOCK(sc); 1479 } 1480 if (i == MII_ANEGTICKS_GIGE) 1481 device_printf(sc->ale_dev, 1482 "establishing a link failed, WOL may not work!"); 1483 } 1484 /* 1485 * No link, force MAC to have 100Mbps, full-duplex link. 1486 * This is the last resort and may/may not work. 1487 */ 1488 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1489 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1490 ale_mac_config(sc); 1491 } 1492 1493 static void 1494 ale_setwol(struct ale_softc *sc) 1495 { 1496 struct ifnet *ifp; 1497 uint32_t reg, pmcs; 1498 uint16_t pmstat; 1499 int pmc; 1500 1501 ALE_LOCK_ASSERT(sc); 1502 1503 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1504 /* Disable WOL. */ 1505 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1506 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1507 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1508 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1509 /* Force PHY power down. */ 1510 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1511 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1512 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1513 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1514 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1515 return; 1516 } 1517 1518 ifp = sc->ale_ifp; 1519 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1520 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1521 ale_setlinkspeed(sc); 1522 } 1523 1524 pmcs = 0; 1525 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1526 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1527 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1528 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1529 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1530 MAC_CFG_BCAST); 1531 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1532 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1533 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1534 reg |= MAC_CFG_RX_ENB; 1535 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1536 1537 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1538 /* WOL disabled, PHY power down. */ 1539 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1540 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1541 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1542 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1543 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1544 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1545 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1546 GPHY_CTRL_PWDOWN_HW); 1547 } 1548 /* Request PME. */ 1549 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1550 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1551 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1552 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1553 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1554 } 1555 1556 static int 1557 ale_suspend(device_t dev) 1558 { 1559 struct ale_softc *sc; 1560 1561 sc = device_get_softc(dev); 1562 1563 ALE_LOCK(sc); 1564 ale_stop(sc); 1565 ale_setwol(sc); 1566 ALE_UNLOCK(sc); 1567 1568 return (0); 1569 } 1570 1571 static int 1572 ale_resume(device_t dev) 1573 { 1574 struct ale_softc *sc; 1575 struct ifnet *ifp; 1576 int pmc; 1577 uint16_t pmstat; 1578 1579 sc = device_get_softc(dev); 1580 1581 ALE_LOCK(sc); 1582 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1583 /* Disable PME and clear PME status. */ 1584 pmstat = pci_read_config(sc->ale_dev, 1585 pmc + PCIR_POWER_STATUS, 2); 1586 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1587 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1588 pci_write_config(sc->ale_dev, 1589 pmc + PCIR_POWER_STATUS, pmstat, 2); 1590 } 1591 } 1592 /* Reset PHY. */ 1593 ale_phy_reset(sc); 1594 ifp = sc->ale_ifp; 1595 if ((ifp->if_flags & IFF_UP) != 0) { 1596 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1597 ale_init_locked(sc); 1598 } 1599 ALE_UNLOCK(sc); 1600 1601 return (0); 1602 } 1603 1604 static int 1605 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1606 { 1607 struct ale_txdesc *txd, *txd_last; 1608 struct tx_desc *desc; 1609 struct mbuf *m; 1610 struct ip *ip; 1611 struct tcphdr *tcp; 1612 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1613 bus_dmamap_t map; 1614 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1615 int error, i, nsegs, prod, si; 1616 1617 ALE_LOCK_ASSERT(sc); 1618 1619 M_ASSERTPKTHDR((*m_head)); 1620 1621 m = *m_head; 1622 ip = NULL; 1623 tcp = NULL; 1624 cflags = vtag = 0; 1625 ip_off = poff = 0; 1626 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1627 /* 1628 * AR81xx requires offset of TCP/UDP payload in its Tx 1629 * descriptor to perform hardware Tx checksum offload. 1630 * Additionally, TSO requires IP/TCP header size and 1631 * modification of IP/TCP header in order to make TSO 1632 * engine work. This kind of operation takes many CPU 1633 * cycles on FreeBSD so fast host CPU is required to 1634 * get smooth TSO performance. 1635 */ 1636 struct ether_header *eh; 1637 1638 if (M_WRITABLE(m) == 0) { 1639 /* Get a writable copy. */ 1640 m = m_dup(*m_head, M_NOWAIT); 1641 /* Release original mbufs. */ 1642 m_freem(*m_head); 1643 if (m == NULL) { 1644 *m_head = NULL; 1645 return (ENOBUFS); 1646 } 1647 *m_head = m; 1648 } 1649 1650 /* 1651 * Buggy-controller requires 4 byte aligned Tx buffer 1652 * to make custom checksum offload work. 1653 */ 1654 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1655 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1656 (mtod(m, intptr_t) & 3) != 0) { 1657 m = m_defrag(*m_head, M_NOWAIT); 1658 if (m == NULL) { 1659 m_freem(*m_head); 1660 *m_head = NULL; 1661 return (ENOBUFS); 1662 } 1663 *m_head = m; 1664 } 1665 1666 ip_off = sizeof(struct ether_header); 1667 m = m_pullup(m, ip_off); 1668 if (m == NULL) { 1669 *m_head = NULL; 1670 return (ENOBUFS); 1671 } 1672 eh = mtod(m, struct ether_header *); 1673 /* 1674 * Check if hardware VLAN insertion is off. 1675 * Additional check for LLC/SNAP frame? 1676 */ 1677 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1678 ip_off = sizeof(struct ether_vlan_header); 1679 m = m_pullup(m, ip_off); 1680 if (m == NULL) { 1681 *m_head = NULL; 1682 return (ENOBUFS); 1683 } 1684 } 1685 m = m_pullup(m, ip_off + sizeof(struct ip)); 1686 if (m == NULL) { 1687 *m_head = NULL; 1688 return (ENOBUFS); 1689 } 1690 ip = (struct ip *)(mtod(m, char *) + ip_off); 1691 poff = ip_off + (ip->ip_hl << 2); 1692 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1693 /* 1694 * XXX 1695 * AR81xx requires the first descriptor should 1696 * not include any TCP playload for TSO case. 1697 * (i.e. ethernet header + IP + TCP header only) 1698 * m_pullup(9) above will ensure this too. 1699 * However it's not correct if the first mbuf 1700 * of the chain does not use cluster. 1701 */ 1702 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1703 if (m == NULL) { 1704 *m_head = NULL; 1705 return (ENOBUFS); 1706 } 1707 ip = (struct ip *)(mtod(m, char *) + ip_off); 1708 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1709 m = m_pullup(m, poff + (tcp->th_off << 2)); 1710 if (m == NULL) { 1711 *m_head = NULL; 1712 return (ENOBUFS); 1713 } 1714 /* 1715 * AR81xx requires IP/TCP header size and offset as 1716 * well as TCP pseudo checksum which complicates 1717 * TSO configuration. I guess this comes from the 1718 * adherence to Microsoft NDIS Large Send 1719 * specification which requires insertion of 1720 * pseudo checksum by upper stack. The pseudo 1721 * checksum that NDIS refers to doesn't include 1722 * TCP payload length so ale(4) should recompute 1723 * the pseudo checksum here. Hopefully this wouldn't 1724 * be much burden on modern CPUs. 1725 * Reset IP checksum and recompute TCP pseudo 1726 * checksum as NDIS specification said. 1727 */ 1728 ip->ip_sum = 0; 1729 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1730 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1731 } 1732 *m_head = m; 1733 } 1734 1735 si = prod = sc->ale_cdata.ale_tx_prod; 1736 txd = &sc->ale_cdata.ale_txdesc[prod]; 1737 txd_last = txd; 1738 map = txd->tx_dmamap; 1739 1740 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1741 *m_head, txsegs, &nsegs, 0); 1742 if (error == EFBIG) { 1743 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1744 if (m == NULL) { 1745 m_freem(*m_head); 1746 *m_head = NULL; 1747 return (ENOMEM); 1748 } 1749 *m_head = m; 1750 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1751 *m_head, txsegs, &nsegs, 0); 1752 if (error != 0) { 1753 m_freem(*m_head); 1754 *m_head = NULL; 1755 return (error); 1756 } 1757 } else if (error != 0) 1758 return (error); 1759 if (nsegs == 0) { 1760 m_freem(*m_head); 1761 *m_head = NULL; 1762 return (EIO); 1763 } 1764 1765 /* Check descriptor overrun. */ 1766 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1767 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1768 return (ENOBUFS); 1769 } 1770 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1771 1772 m = *m_head; 1773 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1774 /* Request TSO and set MSS. */ 1775 cflags |= ALE_TD_TSO; 1776 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1777 /* Set IP/TCP header size. */ 1778 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1779 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1780 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1781 /* 1782 * AR81xx supports Tx custom checksum offload feature 1783 * that offloads single 16bit checksum computation. 1784 * So you can choose one among IP, TCP and UDP. 1785 * Normally driver sets checksum start/insertion 1786 * position from the information of TCP/UDP frame as 1787 * TCP/UDP checksum takes more time than that of IP. 1788 * However it seems that custom checksum offload 1789 * requires 4 bytes aligned Tx buffers due to hardware 1790 * bug. 1791 * AR81xx also supports explicit Tx checksum computation 1792 * if it is told that the size of IP header and TCP 1793 * header(for UDP, the header size does not matter 1794 * because it's fixed length). However with this scheme 1795 * TSO does not work so you have to choose one either 1796 * TSO or explicit Tx checksum offload. I chosen TSO 1797 * plus custom checksum offload with work-around which 1798 * will cover most common usage for this consumer 1799 * ethernet controller. The work-around takes a lot of 1800 * CPU cycles if Tx buffer is not aligned on 4 bytes 1801 * boundary, though. 1802 */ 1803 cflags |= ALE_TD_CXSUM; 1804 /* Set checksum start offset. */ 1805 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1806 /* Set checksum insertion position of TCP/UDP. */ 1807 cflags |= ((poff + m->m_pkthdr.csum_data) << 1808 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1809 } 1810 1811 /* Configure VLAN hardware tag insertion. */ 1812 if ((m->m_flags & M_VLANTAG) != 0) { 1813 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1814 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1815 cflags |= ALE_TD_INSERT_VLAN_TAG; 1816 } 1817 1818 i = 0; 1819 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1820 /* 1821 * Make sure the first fragment contains 1822 * only ethernet and IP/TCP header with options. 1823 */ 1824 hdrlen = poff + (tcp->th_off << 2); 1825 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1826 desc->addr = htole64(txsegs[i].ds_addr); 1827 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1828 desc->flags = htole32(cflags); 1829 sc->ale_cdata.ale_tx_cnt++; 1830 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1831 if (m->m_len - hdrlen > 0) { 1832 /* Handle remaining payload of the first fragment. */ 1833 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1834 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1835 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1836 vtag); 1837 desc->flags = htole32(cflags); 1838 sc->ale_cdata.ale_tx_cnt++; 1839 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1840 } 1841 i = 1; 1842 } 1843 for (; i < nsegs; i++) { 1844 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1845 desc->addr = htole64(txsegs[i].ds_addr); 1846 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1847 desc->flags = htole32(cflags); 1848 sc->ale_cdata.ale_tx_cnt++; 1849 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1850 } 1851 /* Update producer index. */ 1852 sc->ale_cdata.ale_tx_prod = prod; 1853 /* Set TSO header on the first descriptor. */ 1854 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1855 desc = &sc->ale_cdata.ale_tx_ring[si]; 1856 desc->flags |= htole32(ALE_TD_TSO_HDR); 1857 } 1858 1859 /* Finally set EOP on the last descriptor. */ 1860 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1861 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1862 desc->flags |= htole32(ALE_TD_EOP); 1863 1864 /* Swap dmamap of the first and the last. */ 1865 txd = &sc->ale_cdata.ale_txdesc[prod]; 1866 map = txd_last->tx_dmamap; 1867 txd_last->tx_dmamap = txd->tx_dmamap; 1868 txd->tx_dmamap = map; 1869 txd->tx_m = m; 1870 1871 /* Sync descriptors. */ 1872 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1873 sc->ale_cdata.ale_tx_ring_map, 1874 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1875 1876 return (0); 1877 } 1878 1879 static void 1880 ale_start(struct ifnet *ifp) 1881 { 1882 struct ale_softc *sc; 1883 1884 sc = ifp->if_softc; 1885 ALE_LOCK(sc); 1886 ale_start_locked(ifp); 1887 ALE_UNLOCK(sc); 1888 } 1889 1890 static void 1891 ale_start_locked(struct ifnet *ifp) 1892 { 1893 struct ale_softc *sc; 1894 struct mbuf *m_head; 1895 int enq; 1896 1897 sc = ifp->if_softc; 1898 1899 ALE_LOCK_ASSERT(sc); 1900 1901 /* Reclaim transmitted frames. */ 1902 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1903 ale_txeof(sc); 1904 1905 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1906 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1907 return; 1908 1909 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1910 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1911 if (m_head == NULL) 1912 break; 1913 /* 1914 * Pack the data into the transmit ring. If we 1915 * don't have room, set the OACTIVE flag and wait 1916 * for the NIC to drain the ring. 1917 */ 1918 if (ale_encap(sc, &m_head)) { 1919 if (m_head == NULL) 1920 break; 1921 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1922 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1923 break; 1924 } 1925 1926 enq++; 1927 /* 1928 * If there's a BPF listener, bounce a copy of this frame 1929 * to him. 1930 */ 1931 ETHER_BPF_MTAP(ifp, m_head); 1932 } 1933 1934 if (enq > 0) { 1935 /* Kick. */ 1936 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1937 sc->ale_cdata.ale_tx_prod); 1938 /* Set a timeout in case the chip goes out to lunch. */ 1939 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1940 } 1941 } 1942 1943 static void 1944 ale_watchdog(struct ale_softc *sc) 1945 { 1946 struct ifnet *ifp; 1947 1948 ALE_LOCK_ASSERT(sc); 1949 1950 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1951 return; 1952 1953 ifp = sc->ale_ifp; 1954 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1955 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1956 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1957 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1958 ale_init_locked(sc); 1959 return; 1960 } 1961 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1962 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1963 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1964 ale_init_locked(sc); 1965 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1966 ale_start_locked(ifp); 1967 } 1968 1969 static int 1970 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1971 { 1972 struct ale_softc *sc; 1973 struct ifreq *ifr; 1974 struct mii_data *mii; 1975 int error, mask; 1976 1977 sc = ifp->if_softc; 1978 ifr = (struct ifreq *)data; 1979 error = 0; 1980 switch (cmd) { 1981 case SIOCSIFMTU: 1982 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1983 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1984 ifr->ifr_mtu > ETHERMTU)) 1985 error = EINVAL; 1986 else if (ifp->if_mtu != ifr->ifr_mtu) { 1987 ALE_LOCK(sc); 1988 ifp->if_mtu = ifr->ifr_mtu; 1989 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1990 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1991 ale_init_locked(sc); 1992 } 1993 ALE_UNLOCK(sc); 1994 } 1995 break; 1996 case SIOCSIFFLAGS: 1997 ALE_LOCK(sc); 1998 if ((ifp->if_flags & IFF_UP) != 0) { 1999 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2000 if (((ifp->if_flags ^ sc->ale_if_flags) 2001 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2002 ale_rxfilter(sc); 2003 } else { 2004 ale_init_locked(sc); 2005 } 2006 } else { 2007 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2008 ale_stop(sc); 2009 } 2010 sc->ale_if_flags = ifp->if_flags; 2011 ALE_UNLOCK(sc); 2012 break; 2013 case SIOCADDMULTI: 2014 case SIOCDELMULTI: 2015 ALE_LOCK(sc); 2016 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2017 ale_rxfilter(sc); 2018 ALE_UNLOCK(sc); 2019 break; 2020 case SIOCSIFMEDIA: 2021 case SIOCGIFMEDIA: 2022 mii = device_get_softc(sc->ale_miibus); 2023 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2024 break; 2025 case SIOCSIFCAP: 2026 ALE_LOCK(sc); 2027 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2028 if ((mask & IFCAP_TXCSUM) != 0 && 2029 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2030 ifp->if_capenable ^= IFCAP_TXCSUM; 2031 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2032 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2033 else 2034 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2035 } 2036 if ((mask & IFCAP_RXCSUM) != 0 && 2037 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2038 ifp->if_capenable ^= IFCAP_RXCSUM; 2039 if ((mask & IFCAP_TSO4) != 0 && 2040 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2041 ifp->if_capenable ^= IFCAP_TSO4; 2042 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2043 ifp->if_hwassist |= CSUM_TSO; 2044 else 2045 ifp->if_hwassist &= ~CSUM_TSO; 2046 } 2047 2048 if ((mask & IFCAP_WOL_MCAST) != 0 && 2049 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2050 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2051 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2052 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2053 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2054 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2055 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2056 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2057 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2058 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2059 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2060 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2061 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2062 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2063 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2064 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2065 ale_rxvlan(sc); 2066 } 2067 ALE_UNLOCK(sc); 2068 VLAN_CAPABILITIES(ifp); 2069 break; 2070 default: 2071 error = ether_ioctl(ifp, cmd, data); 2072 break; 2073 } 2074 2075 return (error); 2076 } 2077 2078 static void 2079 ale_mac_config(struct ale_softc *sc) 2080 { 2081 struct mii_data *mii; 2082 uint32_t reg; 2083 2084 ALE_LOCK_ASSERT(sc); 2085 2086 mii = device_get_softc(sc->ale_miibus); 2087 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2088 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2089 MAC_CFG_SPEED_MASK); 2090 /* Reprogram MAC with resolved speed/duplex. */ 2091 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2092 case IFM_10_T: 2093 case IFM_100_TX: 2094 reg |= MAC_CFG_SPEED_10_100; 2095 break; 2096 case IFM_1000_T: 2097 reg |= MAC_CFG_SPEED_1000; 2098 break; 2099 } 2100 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2101 reg |= MAC_CFG_FULL_DUPLEX; 2102 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2103 reg |= MAC_CFG_TX_FC; 2104 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2105 reg |= MAC_CFG_RX_FC; 2106 } 2107 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2108 } 2109 2110 static void 2111 ale_stats_clear(struct ale_softc *sc) 2112 { 2113 struct smb sb; 2114 uint32_t *reg; 2115 int i; 2116 2117 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2118 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2119 i += sizeof(uint32_t); 2120 } 2121 /* Read Tx statistics. */ 2122 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2123 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2124 i += sizeof(uint32_t); 2125 } 2126 } 2127 2128 static void 2129 ale_stats_update(struct ale_softc *sc) 2130 { 2131 struct ale_hw_stats *stat; 2132 struct smb sb, *smb; 2133 struct ifnet *ifp; 2134 uint32_t *reg; 2135 int i; 2136 2137 ALE_LOCK_ASSERT(sc); 2138 2139 ifp = sc->ale_ifp; 2140 stat = &sc->ale_stats; 2141 smb = &sb; 2142 2143 /* Read Rx statistics. */ 2144 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2145 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2146 i += sizeof(uint32_t); 2147 } 2148 /* Read Tx statistics. */ 2149 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2150 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2151 i += sizeof(uint32_t); 2152 } 2153 2154 /* Rx stats. */ 2155 stat->rx_frames += smb->rx_frames; 2156 stat->rx_bcast_frames += smb->rx_bcast_frames; 2157 stat->rx_mcast_frames += smb->rx_mcast_frames; 2158 stat->rx_pause_frames += smb->rx_pause_frames; 2159 stat->rx_control_frames += smb->rx_control_frames; 2160 stat->rx_crcerrs += smb->rx_crcerrs; 2161 stat->rx_lenerrs += smb->rx_lenerrs; 2162 stat->rx_bytes += smb->rx_bytes; 2163 stat->rx_runts += smb->rx_runts; 2164 stat->rx_fragments += smb->rx_fragments; 2165 stat->rx_pkts_64 += smb->rx_pkts_64; 2166 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2167 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2168 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2169 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2170 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2171 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2172 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2173 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2174 stat->rx_rrs_errs += smb->rx_rrs_errs; 2175 stat->rx_alignerrs += smb->rx_alignerrs; 2176 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2177 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2178 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2179 2180 /* Tx stats. */ 2181 stat->tx_frames += smb->tx_frames; 2182 stat->tx_bcast_frames += smb->tx_bcast_frames; 2183 stat->tx_mcast_frames += smb->tx_mcast_frames; 2184 stat->tx_pause_frames += smb->tx_pause_frames; 2185 stat->tx_excess_defer += smb->tx_excess_defer; 2186 stat->tx_control_frames += smb->tx_control_frames; 2187 stat->tx_deferred += smb->tx_deferred; 2188 stat->tx_bytes += smb->tx_bytes; 2189 stat->tx_pkts_64 += smb->tx_pkts_64; 2190 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2191 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2192 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2193 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2194 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2195 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2196 stat->tx_single_colls += smb->tx_single_colls; 2197 stat->tx_multi_colls += smb->tx_multi_colls; 2198 stat->tx_late_colls += smb->tx_late_colls; 2199 stat->tx_excess_colls += smb->tx_excess_colls; 2200 stat->tx_underrun += smb->tx_underrun; 2201 stat->tx_desc_underrun += smb->tx_desc_underrun; 2202 stat->tx_lenerrs += smb->tx_lenerrs; 2203 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2204 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2205 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2206 2207 /* Update counters in ifnet. */ 2208 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2209 2210 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2211 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2212 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2213 2214 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2215 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2216 2217 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2218 2219 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2220 smb->rx_crcerrs + smb->rx_lenerrs + 2221 smb->rx_runts + smb->rx_pkts_truncated + 2222 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2223 smb->rx_alignerrs); 2224 } 2225 2226 static int 2227 ale_intr(void *arg) 2228 { 2229 struct ale_softc *sc; 2230 uint32_t status; 2231 2232 sc = (struct ale_softc *)arg; 2233 2234 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2235 if ((status & ALE_INTRS) == 0) 2236 return (FILTER_STRAY); 2237 /* Disable interrupts. */ 2238 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2239 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2240 2241 return (FILTER_HANDLED); 2242 } 2243 2244 static void 2245 ale_int_task(void *arg, int pending) 2246 { 2247 struct ale_softc *sc; 2248 struct ifnet *ifp; 2249 uint32_t status; 2250 int more; 2251 2252 sc = (struct ale_softc *)arg; 2253 2254 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2255 ALE_LOCK(sc); 2256 if (sc->ale_morework != 0) 2257 status |= INTR_RX_PKT; 2258 if ((status & ALE_INTRS) == 0) 2259 goto done; 2260 2261 /* Acknowledge interrupts but still disable interrupts. */ 2262 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2263 2264 ifp = sc->ale_ifp; 2265 more = 0; 2266 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2267 more = ale_rxeof(sc, sc->ale_process_limit); 2268 if (more == EAGAIN) 2269 sc->ale_morework = 1; 2270 else if (more == EIO) { 2271 sc->ale_stats.reset_brk_seq++; 2272 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2273 ale_init_locked(sc); 2274 ALE_UNLOCK(sc); 2275 return; 2276 } 2277 2278 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2279 if ((status & INTR_DMA_RD_TO_RST) != 0) 2280 device_printf(sc->ale_dev, 2281 "DMA read error! -- resetting\n"); 2282 if ((status & INTR_DMA_WR_TO_RST) != 0) 2283 device_printf(sc->ale_dev, 2284 "DMA write error! -- resetting\n"); 2285 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2286 ale_init_locked(sc); 2287 ALE_UNLOCK(sc); 2288 return; 2289 } 2290 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2291 ale_start_locked(ifp); 2292 } 2293 2294 if (more == EAGAIN || 2295 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2296 ALE_UNLOCK(sc); 2297 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2298 return; 2299 } 2300 2301 done: 2302 ALE_UNLOCK(sc); 2303 2304 /* Re-enable interrupts. */ 2305 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2306 } 2307 2308 static void 2309 ale_txeof(struct ale_softc *sc) 2310 { 2311 struct ifnet *ifp; 2312 struct ale_txdesc *txd; 2313 uint32_t cons, prod; 2314 int prog; 2315 2316 ALE_LOCK_ASSERT(sc); 2317 2318 ifp = sc->ale_ifp; 2319 2320 if (sc->ale_cdata.ale_tx_cnt == 0) 2321 return; 2322 2323 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2324 sc->ale_cdata.ale_tx_ring_map, 2325 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2326 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2327 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2328 sc->ale_cdata.ale_tx_cmb_map, 2329 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2330 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2331 } else 2332 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2333 cons = sc->ale_cdata.ale_tx_cons; 2334 /* 2335 * Go through our Tx list and free mbufs for those 2336 * frames which have been transmitted. 2337 */ 2338 for (prog = 0; cons != prod; prog++, 2339 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2340 if (sc->ale_cdata.ale_tx_cnt <= 0) 2341 break; 2342 prog++; 2343 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2344 sc->ale_cdata.ale_tx_cnt--; 2345 txd = &sc->ale_cdata.ale_txdesc[cons]; 2346 if (txd->tx_m != NULL) { 2347 /* Reclaim transmitted mbufs. */ 2348 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2349 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2350 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2351 txd->tx_dmamap); 2352 m_freem(txd->tx_m); 2353 txd->tx_m = NULL; 2354 } 2355 } 2356 2357 if (prog > 0) { 2358 sc->ale_cdata.ale_tx_cons = cons; 2359 /* 2360 * Unarm watchdog timer only when there is no pending 2361 * Tx descriptors in queue. 2362 */ 2363 if (sc->ale_cdata.ale_tx_cnt == 0) 2364 sc->ale_watchdog_timer = 0; 2365 } 2366 } 2367 2368 static void 2369 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2370 uint32_t length, uint32_t *prod) 2371 { 2372 struct ale_rx_page *rx_page; 2373 2374 rx_page = *page; 2375 /* Update consumer position. */ 2376 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2377 ALE_RX_PAGE_ALIGN); 2378 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2379 /* 2380 * End of Rx page reached, let hardware reuse 2381 * this page. 2382 */ 2383 rx_page->cons = 0; 2384 *rx_page->cmb_addr = 0; 2385 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2386 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2387 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2388 RXF_VALID); 2389 /* Switch to alternate Rx page. */ 2390 sc->ale_cdata.ale_rx_curp ^= 1; 2391 rx_page = *page = 2392 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2393 /* Page flipped, sync CMB and Rx page. */ 2394 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2395 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2396 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2397 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2398 /* Sync completed, cache updated producer index. */ 2399 *prod = *rx_page->cmb_addr; 2400 } 2401 } 2402 2403 2404 /* 2405 * It seems that AR81xx controller can compute partial checksum. 2406 * The partial checksum value can be used to accelerate checksum 2407 * computation for fragmented TCP/UDP packets. Upper network stack 2408 * already takes advantage of the partial checksum value in IP 2409 * reassembly stage. But I'm not sure the correctness of the 2410 * partial hardware checksum assistance due to lack of data sheet. 2411 * In addition, the Rx feature of controller that requires copying 2412 * for every frames effectively nullifies one of most nice offload 2413 * capability of controller. 2414 */ 2415 static void 2416 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2417 { 2418 struct ifnet *ifp; 2419 struct ip *ip; 2420 char *p; 2421 2422 ifp = sc->ale_ifp; 2423 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2424 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2425 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2426 2427 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2428 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2429 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2430 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2431 m->m_pkthdr.csum_flags |= 2432 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2433 m->m_pkthdr.csum_data = 0xffff; 2434 } 2435 } else { 2436 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2437 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2438 p = mtod(m, char *); 2439 p += ETHER_HDR_LEN; 2440 if ((status & ALE_RD_802_3) != 0) 2441 p += LLC_SNAPFRAMELEN; 2442 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2443 (status & ALE_RD_VLAN) != 0) 2444 p += ETHER_VLAN_ENCAP_LEN; 2445 ip = (struct ip *)p; 2446 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2447 return; 2448 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2449 CSUM_PSEUDO_HDR; 2450 m->m_pkthdr.csum_data = 0xffff; 2451 } 2452 } 2453 /* 2454 * Don't mark bad checksum for TCP/UDP frames 2455 * as fragmented frames may always have set 2456 * bad checksummed bit of frame status. 2457 */ 2458 } 2459 2460 /* Process received frames. */ 2461 static int 2462 ale_rxeof(struct ale_softc *sc, int count) 2463 { 2464 struct ale_rx_page *rx_page; 2465 struct rx_rs *rs; 2466 struct ifnet *ifp; 2467 struct mbuf *m; 2468 uint32_t length, prod, seqno, status, vtags; 2469 int prog; 2470 2471 ifp = sc->ale_ifp; 2472 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2473 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2474 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2475 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2476 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2477 /* 2478 * Don't directly access producer index as hardware may 2479 * update it while Rx handler is in progress. It would 2480 * be even better if there is a way to let hardware 2481 * know how far driver processed its received frames. 2482 * Alternatively, hardware could provide a way to disable 2483 * CMB updates until driver acknowledges the end of CMB 2484 * access. 2485 */ 2486 prod = *rx_page->cmb_addr; 2487 for (prog = 0; prog < count; prog++) { 2488 if (rx_page->cons >= prod) 2489 break; 2490 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2491 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2492 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2493 /* 2494 * Normally I believe this should not happen unless 2495 * severe driver bug or corrupted memory. However 2496 * it seems to happen under certain conditions which 2497 * is triggered by abrupt Rx events such as initiation 2498 * of bulk transfer of remote host. It's not easy to 2499 * reproduce this and I doubt it could be related 2500 * with FIFO overflow of hardware or activity of Tx 2501 * CMB updates. I also remember similar behaviour 2502 * seen on RealTek 8139 which uses resembling Rx 2503 * scheme. 2504 */ 2505 if (bootverbose) 2506 device_printf(sc->ale_dev, 2507 "garbled seq: %u, expected: %u -- " 2508 "resetting!\n", seqno, 2509 sc->ale_cdata.ale_rx_seqno); 2510 return (EIO); 2511 } 2512 /* Frame received. */ 2513 sc->ale_cdata.ale_rx_seqno++; 2514 length = ALE_RX_BYTES(le32toh(rs->length)); 2515 status = le32toh(rs->flags); 2516 if ((status & ALE_RD_ERROR) != 0) { 2517 /* 2518 * We want to pass the following frames to upper 2519 * layer regardless of error status of Rx return 2520 * status. 2521 * 2522 * o IP/TCP/UDP checksum is bad. 2523 * o frame length and protocol specific length 2524 * does not match. 2525 */ 2526 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2527 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2528 ALE_RD_TRUNC)) != 0) { 2529 ale_rx_update_page(sc, &rx_page, length, &prod); 2530 continue; 2531 } 2532 } 2533 /* 2534 * m_devget(9) is major bottle-neck of ale(4)(It comes 2535 * from hardware limitation). For jumbo frames we could 2536 * get a slightly better performance if driver use 2537 * m_getjcl(9) with proper buffer size argument. However 2538 * that would make code more complicated and I don't 2539 * think users would expect good Rx performance numbers 2540 * on these low-end consumer ethernet controller. 2541 */ 2542 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2543 ETHER_ALIGN, ifp, NULL); 2544 if (m == NULL) { 2545 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2546 ale_rx_update_page(sc, &rx_page, length, &prod); 2547 continue; 2548 } 2549 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2550 (status & ALE_RD_IPV4) != 0) 2551 ale_rxcsum(sc, m, status); 2552 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2553 (status & ALE_RD_VLAN) != 0) { 2554 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2555 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2556 m->m_flags |= M_VLANTAG; 2557 } 2558 2559 /* Pass it to upper layer. */ 2560 ALE_UNLOCK(sc); 2561 (*ifp->if_input)(ifp, m); 2562 ALE_LOCK(sc); 2563 2564 ale_rx_update_page(sc, &rx_page, length, &prod); 2565 } 2566 2567 return (count > 0 ? 0 : EAGAIN); 2568 } 2569 2570 static void 2571 ale_tick(void *arg) 2572 { 2573 struct ale_softc *sc; 2574 struct mii_data *mii; 2575 2576 sc = (struct ale_softc *)arg; 2577 2578 ALE_LOCK_ASSERT(sc); 2579 2580 mii = device_get_softc(sc->ale_miibus); 2581 mii_tick(mii); 2582 ale_stats_update(sc); 2583 /* 2584 * Reclaim Tx buffers that have been transferred. It's not 2585 * needed here but it would release allocated mbuf chains 2586 * faster and limit the maximum delay to a hz. 2587 */ 2588 ale_txeof(sc); 2589 ale_watchdog(sc); 2590 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2591 } 2592 2593 static void 2594 ale_reset(struct ale_softc *sc) 2595 { 2596 uint32_t reg; 2597 int i; 2598 2599 /* Initialize PCIe module. From Linux. */ 2600 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2601 2602 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2603 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2604 DELAY(10); 2605 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2606 break; 2607 } 2608 if (i == 0) 2609 device_printf(sc->ale_dev, "master reset timeout!\n"); 2610 2611 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2612 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2613 break; 2614 DELAY(10); 2615 } 2616 2617 if (i == 0) 2618 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2619 } 2620 2621 static void 2622 ale_init(void *xsc) 2623 { 2624 struct ale_softc *sc; 2625 2626 sc = (struct ale_softc *)xsc; 2627 ALE_LOCK(sc); 2628 ale_init_locked(sc); 2629 ALE_UNLOCK(sc); 2630 } 2631 2632 static void 2633 ale_init_locked(struct ale_softc *sc) 2634 { 2635 struct ifnet *ifp; 2636 struct mii_data *mii; 2637 uint8_t eaddr[ETHER_ADDR_LEN]; 2638 bus_addr_t paddr; 2639 uint32_t reg, rxf_hi, rxf_lo; 2640 2641 ALE_LOCK_ASSERT(sc); 2642 2643 ifp = sc->ale_ifp; 2644 mii = device_get_softc(sc->ale_miibus); 2645 2646 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2647 return; 2648 /* 2649 * Cancel any pending I/O. 2650 */ 2651 ale_stop(sc); 2652 /* 2653 * Reset the chip to a known state. 2654 */ 2655 ale_reset(sc); 2656 /* Initialize Tx descriptors, DMA memory blocks. */ 2657 ale_init_rx_pages(sc); 2658 ale_init_tx_ring(sc); 2659 2660 /* Reprogram the station address. */ 2661 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2662 CSR_WRITE_4(sc, ALE_PAR0, 2663 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2664 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2665 /* 2666 * Clear WOL status and disable all WOL feature as WOL 2667 * would interfere Rx operation under normal environments. 2668 */ 2669 CSR_READ_4(sc, ALE_WOL_CFG); 2670 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2671 /* 2672 * Set Tx descriptor/RXF0/CMB base addresses. They share 2673 * the same high address part of DMAable region. 2674 */ 2675 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2676 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2677 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2678 CSR_WRITE_4(sc, ALE_TPD_CNT, 2679 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2680 /* Set Rx page base address, note we use single queue. */ 2681 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2682 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2683 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2684 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2685 /* Set Tx/Rx CMB addresses. */ 2686 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2687 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2688 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2689 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2690 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2691 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2692 /* Mark RXF0 is valid. */ 2693 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2694 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2695 /* 2696 * No need to initialize RFX1/RXF2/RXF3. We don't use 2697 * multi-queue yet. 2698 */ 2699 2700 /* Set Rx page size, excluding guard frame size. */ 2701 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2702 /* Tell hardware that we're ready to load DMA blocks. */ 2703 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2704 2705 /* Set Rx/Tx interrupt trigger threshold. */ 2706 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2707 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2708 /* 2709 * XXX 2710 * Set interrupt trigger timer, its purpose and relation 2711 * with interrupt moderation mechanism is not clear yet. 2712 */ 2713 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2714 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2715 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2716 2717 /* Configure interrupt moderation timer. */ 2718 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2719 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2720 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2721 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2722 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2723 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2724 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2725 reg |= MASTER_IM_RX_TIMER_ENB; 2726 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2727 reg |= MASTER_IM_TX_TIMER_ENB; 2728 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2729 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2730 2731 /* Set Maximum frame size of controller. */ 2732 if (ifp->if_mtu < ETHERMTU) 2733 sc->ale_max_frame_size = ETHERMTU; 2734 else 2735 sc->ale_max_frame_size = ifp->if_mtu; 2736 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2737 ETHER_CRC_LEN; 2738 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2739 /* Configure IPG/IFG parameters. */ 2740 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2741 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2742 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2743 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2744 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2745 /* Set parameters for half-duplex media. */ 2746 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2747 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2748 HDPX_CFG_LCOL_MASK) | 2749 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2750 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2751 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2752 HDPX_CFG_ABEBT_MASK) | 2753 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2754 HDPX_CFG_JAMIPG_MASK)); 2755 2756 /* Configure Tx jumbo frame parameters. */ 2757 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2758 if (ifp->if_mtu < ETHERMTU) 2759 reg = sc->ale_max_frame_size; 2760 else if (ifp->if_mtu < 6 * 1024) 2761 reg = (sc->ale_max_frame_size * 2) / 3; 2762 else 2763 reg = sc->ale_max_frame_size / 2; 2764 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2765 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2766 TX_JUMBO_THRESH_UNIT_SHIFT); 2767 } 2768 /* Configure TxQ. */ 2769 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2770 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2771 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2772 TXQ_CFG_TPD_BURST_MASK; 2773 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2774 2775 /* Configure Rx jumbo frame & flow control parameters. */ 2776 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2777 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2778 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2779 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2780 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2781 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2782 RX_JUMBO_LKAH_MASK)); 2783 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2784 rxf_hi = (reg * 7) / 10; 2785 rxf_lo = (reg * 3)/ 10; 2786 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2787 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2788 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2789 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2790 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2791 } 2792 2793 /* Disable RSS. */ 2794 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2795 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2796 2797 /* Configure RxQ. */ 2798 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2799 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2800 2801 /* Configure DMA parameters. */ 2802 reg = 0; 2803 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2804 reg |= DMA_CFG_TXCMB_ENB; 2805 CSR_WRITE_4(sc, ALE_DMA_CFG, 2806 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2807 sc->ale_dma_rd_burst | reg | 2808 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2809 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2810 DMA_CFG_RD_DELAY_CNT_MASK) | 2811 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2812 DMA_CFG_WR_DELAY_CNT_MASK)); 2813 2814 /* 2815 * Hardware can be configured to issue SMB interrupt based 2816 * on programmed interval. Since there is a callout that is 2817 * invoked for every hz in driver we use that instead of 2818 * relying on periodic SMB interrupt. 2819 */ 2820 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2821 /* Clear MAC statistics. */ 2822 ale_stats_clear(sc); 2823 2824 /* 2825 * Configure Tx/Rx MACs. 2826 * - Auto-padding for short frames. 2827 * - Enable CRC generation. 2828 * Actual reconfiguration of MAC for resolved speed/duplex 2829 * is followed after detection of link establishment. 2830 * AR81xx always does checksum computation regardless of 2831 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2832 * cause Rx handling issue for fragmented IP datagrams due 2833 * to silicon bug. 2834 */ 2835 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2836 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2837 MAC_CFG_PREAMBLE_MASK); 2838 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2839 reg |= MAC_CFG_SPEED_10_100; 2840 else 2841 reg |= MAC_CFG_SPEED_1000; 2842 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2843 2844 /* Set up the receive filter. */ 2845 ale_rxfilter(sc); 2846 ale_rxvlan(sc); 2847 2848 /* Acknowledge all pending interrupts and clear it. */ 2849 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2850 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2851 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2852 2853 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2854 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2855 2856 sc->ale_flags &= ~ALE_FLAG_LINK; 2857 /* Switch to the current media. */ 2858 mii_mediachg(mii); 2859 2860 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2861 } 2862 2863 static void 2864 ale_stop(struct ale_softc *sc) 2865 { 2866 struct ifnet *ifp; 2867 struct ale_txdesc *txd; 2868 uint32_t reg; 2869 int i; 2870 2871 ALE_LOCK_ASSERT(sc); 2872 /* 2873 * Mark the interface down and cancel the watchdog timer. 2874 */ 2875 ifp = sc->ale_ifp; 2876 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2877 sc->ale_flags &= ~ALE_FLAG_LINK; 2878 callout_stop(&sc->ale_tick_ch); 2879 sc->ale_watchdog_timer = 0; 2880 ale_stats_update(sc); 2881 /* Disable interrupts. */ 2882 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2883 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2884 /* Disable queue processing and DMA. */ 2885 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2886 reg &= ~TXQ_CFG_ENB; 2887 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2888 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2889 reg &= ~RXQ_CFG_ENB; 2890 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2891 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2892 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2893 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2894 DELAY(1000); 2895 /* Stop Rx/Tx MACs. */ 2896 ale_stop_mac(sc); 2897 /* Disable interrupts which might be touched in taskq handler. */ 2898 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2899 2900 /* 2901 * Free TX mbufs still in the queues. 2902 */ 2903 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2904 txd = &sc->ale_cdata.ale_txdesc[i]; 2905 if (txd->tx_m != NULL) { 2906 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2907 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2908 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2909 txd->tx_dmamap); 2910 m_freem(txd->tx_m); 2911 txd->tx_m = NULL; 2912 } 2913 } 2914 } 2915 2916 static void 2917 ale_stop_mac(struct ale_softc *sc) 2918 { 2919 uint32_t reg; 2920 int i; 2921 2922 ALE_LOCK_ASSERT(sc); 2923 2924 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2925 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2926 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2927 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2928 } 2929 2930 for (i = ALE_TIMEOUT; i > 0; i--) { 2931 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2932 if (reg == 0) 2933 break; 2934 DELAY(10); 2935 } 2936 if (i == 0) 2937 device_printf(sc->ale_dev, 2938 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2939 } 2940 2941 static void 2942 ale_init_tx_ring(struct ale_softc *sc) 2943 { 2944 struct ale_txdesc *txd; 2945 int i; 2946 2947 ALE_LOCK_ASSERT(sc); 2948 2949 sc->ale_cdata.ale_tx_prod = 0; 2950 sc->ale_cdata.ale_tx_cons = 0; 2951 sc->ale_cdata.ale_tx_cnt = 0; 2952 2953 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2954 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2955 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2956 txd = &sc->ale_cdata.ale_txdesc[i]; 2957 txd->tx_m = NULL; 2958 } 2959 *sc->ale_cdata.ale_tx_cmb = 0; 2960 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2961 sc->ale_cdata.ale_tx_cmb_map, 2962 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2963 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2964 sc->ale_cdata.ale_tx_ring_map, 2965 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2966 } 2967 2968 static void 2969 ale_init_rx_pages(struct ale_softc *sc) 2970 { 2971 struct ale_rx_page *rx_page; 2972 int i; 2973 2974 ALE_LOCK_ASSERT(sc); 2975 2976 sc->ale_morework = 0; 2977 sc->ale_cdata.ale_rx_seqno = 0; 2978 sc->ale_cdata.ale_rx_curp = 0; 2979 2980 for (i = 0; i < ALE_RX_PAGES; i++) { 2981 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2982 bzero(rx_page->page_addr, sc->ale_pagesize); 2983 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2984 rx_page->cons = 0; 2985 *rx_page->cmb_addr = 0; 2986 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2987 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2988 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2989 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2990 } 2991 } 2992 2993 static void 2994 ale_rxvlan(struct ale_softc *sc) 2995 { 2996 struct ifnet *ifp; 2997 uint32_t reg; 2998 2999 ALE_LOCK_ASSERT(sc); 3000 3001 ifp = sc->ale_ifp; 3002 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3003 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3004 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3005 reg |= MAC_CFG_VLAN_TAG_STRIP; 3006 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3007 } 3008 3009 static void 3010 ale_rxfilter(struct ale_softc *sc) 3011 { 3012 struct ifnet *ifp; 3013 struct ifmultiaddr *ifma; 3014 uint32_t crc; 3015 uint32_t mchash[2]; 3016 uint32_t rxcfg; 3017 3018 ALE_LOCK_ASSERT(sc); 3019 3020 ifp = sc->ale_ifp; 3021 3022 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3023 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3024 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3025 rxcfg |= MAC_CFG_BCAST; 3026 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3027 if ((ifp->if_flags & IFF_PROMISC) != 0) 3028 rxcfg |= MAC_CFG_PROMISC; 3029 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3030 rxcfg |= MAC_CFG_ALLMULTI; 3031 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3032 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3033 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3034 return; 3035 } 3036 3037 /* Program new filter. */ 3038 bzero(mchash, sizeof(mchash)); 3039 3040 if_maddr_rlock(ifp); 3041 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3042 if (ifma->ifma_addr->sa_family != AF_LINK) 3043 continue; 3044 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3045 ifma->ifma_addr), ETHER_ADDR_LEN); 3046 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3047 } 3048 if_maddr_runlock(ifp); 3049 3050 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3051 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3052 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3053 } 3054 3055 static int 3056 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3057 { 3058 int error, value; 3059 3060 if (arg1 == NULL) 3061 return (EINVAL); 3062 value = *(int *)arg1; 3063 error = sysctl_handle_int(oidp, &value, 0, req); 3064 if (error || req->newptr == NULL) 3065 return (error); 3066 if (value < low || value > high) 3067 return (EINVAL); 3068 *(int *)arg1 = value; 3069 3070 return (0); 3071 } 3072 3073 static int 3074 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3075 { 3076 return (sysctl_int_range(oidp, arg1, arg2, req, 3077 ALE_PROC_MIN, ALE_PROC_MAX)); 3078 } 3079 3080 static int 3081 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3082 { 3083 3084 return (sysctl_int_range(oidp, arg1, arg2, req, 3085 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3086 } 3087