1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2011-2012 Robert N. M. Watson 5 * All rights reserved. 6 * 7 * This software was developed by SRI International and the University of 8 * Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237) 9 * ("CTSRD"), as part of the DARPA CRASH research programme. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 30 * SUCH DAMAGE. 31 */ 32 33 #include <sys/param.h> 34 #include <sys/bus.h> 35 #include <sys/cons.h> 36 #include <sys/endian.h> 37 #include <sys/kdb.h> 38 #include <sys/kernel.h> 39 #include <sys/lock.h> 40 #include <sys/mutex.h> 41 #include <sys/reboot.h> 42 #include <sys/sysctl.h> 43 #include <sys/systm.h> 44 #include <sys/tty.h> 45 46 #include <ddb/ddb.h> 47 48 #include <dev/altera/jtag_uart/altera_jtag_uart.h> 49 50 static SYSCTL_NODE(_hw, OID_AUTO, altera_jtag_uart, 51 CTLFLAG_RW | CTLFLAG_MPSAFE, 0, 52 "Altera JTAG UART configuration knobs"); 53 54 /* 55 * One-byte buffer as we can't check whether the UART is readable without 56 * actually reading from it, synchronised by a spinlock; this lock also 57 * synchronises access to the I/O ports for non-atomic sequences. These 58 * symbols are public so that the TTY layer can use them when working on an 59 * instance of the UART that is also a low-level console. 60 */ 61 char aju_cons_buffer_data; 62 int aju_cons_buffer_valid; 63 int aju_cons_jtag_present; 64 u_int aju_cons_jtag_missed; 65 struct mtx aju_cons_lock; 66 67 /* 68 * Low-level console driver functions. 69 */ 70 static cn_probe_t aju_cnprobe; 71 static cn_init_t aju_cninit; 72 static cn_term_t aju_cnterm; 73 static cn_getc_t aju_cngetc; 74 static cn_putc_t aju_cnputc; 75 static cn_grab_t aju_cngrab; 76 static cn_ungrab_t aju_cnungrab; 77 78 /* 79 * JTAG sets the ALTERA_JTAG_UART_CONTROL_AC bit whenever it accesses the 80 * FIFO. This allows us to (sort of) tell when JTAG is present, so that we 81 * can adopt lossy, rather than blocking, behaviour when JTAG isn't there. 82 * When it is present, we do full flow control. This delay is how long we 83 * wait to see if JTAG has really disappeared when finding a full buffer and 84 * no AC bit set. 85 */ 86 #define ALTERA_JTAG_UART_AC_POLL_DELAY 10000 87 static u_int altera_jtag_uart_ac_poll_delay = 88 ALTERA_JTAG_UART_AC_POLL_DELAY; 89 SYSCTL_UINT(_hw_altera_jtag_uart, OID_AUTO, ac_poll_delay, 90 CTLFLAG_RW, &altera_jtag_uart_ac_poll_delay, 0, 91 "Maximum delay waiting for JTAG present flag when buffer is full"); 92 93 /* 94 * I/O routines lifted from Deimos. This is not only MIPS-specific, but also 95 * BERI-specific, as we're hard coding the address at which we expect to 96 * find the Altera JTAG UART and using it unconditionally. We use these 97 * low-level routines so that we can perform console I/O long before newbus 98 * has initialised and devices have attached. The TTY layer of the driver 99 * knows about this, and uses the console-layer spinlock instead of the 100 * TTY-layer lock to avoid confusion between layers for the console UART. 101 * 102 * XXXRW: The only place this inter-layer behaviour breaks down is if the 103 * low-level console is used for polled read while the TTY driver is also 104 * looking for input. Probably we should also share buffers between layers. 105 */ 106 #define MIPS_XKPHYS_UNCACHED_BASE 0x9000000000000000 107 108 typedef uint64_t paddr_t; 109 typedef uint64_t vaddr_t; 110 111 static inline vaddr_t 112 mips_phys_to_uncached(paddr_t phys) 113 { 114 115 return (phys | MIPS_XKPHYS_UNCACHED_BASE); 116 } 117 118 static inline uint32_t 119 mips_ioread_uint32(vaddr_t vaddr) 120 { 121 uint32_t v; 122 123 __asm__ __volatile__ ("lw %0, 0(%1)" : "=r" (v) : "r" (vaddr)); 124 return (v); 125 } 126 127 static inline void 128 mips_iowrite_uint32(vaddr_t vaddr, uint32_t v) 129 { 130 131 __asm__ __volatile__ ("sw %0, 0(%1)" : : "r" (v), "r" (vaddr)); 132 } 133 134 /* 135 * Little-endian versions of 32-bit I/O routines. 136 */ 137 static inline uint32_t 138 mips_ioread_uint32le(vaddr_t vaddr) 139 { 140 141 return (le32toh(mips_ioread_uint32(vaddr))); 142 } 143 144 static inline void 145 mips_iowrite_uint32le(vaddr_t vaddr, uint32_t v) 146 { 147 148 mips_iowrite_uint32(vaddr, htole32(v)); 149 } 150 151 /* 152 * Low-level read and write register routines; the Altera UART is little 153 * endian, so we byte swap 32-bit reads and writes. 154 */ 155 static inline uint32_t 156 aju_cons_data_read(void) 157 { 158 159 return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 160 ALTERA_JTAG_UART_DATA_OFF))); 161 } 162 163 static inline void 164 aju_cons_data_write(uint32_t v) 165 { 166 167 mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 168 ALTERA_JTAG_UART_DATA_OFF), v); 169 } 170 171 static inline uint32_t 172 aju_cons_control_read(void) 173 { 174 175 return (mips_ioread_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 176 ALTERA_JTAG_UART_CONTROL_OFF))); 177 } 178 179 static inline void 180 aju_cons_control_write(uint32_t v) 181 { 182 183 mips_iowrite_uint32le(mips_phys_to_uncached(BERI_UART_BASE + 184 ALTERA_JTAG_UART_CONTROL_OFF), v); 185 } 186 187 /* 188 * Slightly higher-level routines aware of buffering and flow control. 189 */ 190 static int 191 aju_cons_readable(void) 192 { 193 uint32_t v; 194 195 AJU_CONSOLE_LOCK_ASSERT(); 196 197 if (aju_cons_buffer_valid) 198 return (1); 199 v = aju_cons_data_read(); 200 if ((v & ALTERA_JTAG_UART_DATA_RVALID) != 0) { 201 aju_cons_buffer_valid = 1; 202 aju_cons_buffer_data = (v & ALTERA_JTAG_UART_DATA_DATA); 203 return (1); 204 } 205 return (0); 206 } 207 208 static void 209 aju_cons_write(char ch) 210 { 211 uint32_t v; 212 213 AJU_CONSOLE_LOCK_ASSERT(); 214 215 /* 216 * The flow control logic here is somewhat subtle: we want to wait for 217 * write buffer space only while JTAG is present. However, we can't 218 * directly ask if JTAG is present -- just whether it's been seen 219 * since we last cleared the ALTERA_JTAG_UART_CONTROL_AC bit. As 220 * such, implement a polling loop in which we both wait for space and 221 * try to decide whether JTAG has disappeared on us. We will have to 222 * wait one complete polling delay to detect that JTAG has gone away, 223 * but otherwise shouldn't wait any further once it has gone. And we 224 * had to wait for buffer space anyway, if it was there. 225 * 226 * If JTAG is spotted, reset the TTY-layer miss counter so console- 227 * layer clearing of the bit doesn't trigger a TTY-layer 228 * disconnection. 229 * 230 * XXXRW: Notice the inherent race with hardware: in clearing the 231 * bit, we may race with hardware setting the same bit. This can 232 * cause real-world reliability problems due to lost output on the 233 * console. 234 */ 235 v = aju_cons_control_read(); 236 if (v & ALTERA_JTAG_UART_CONTROL_AC) { 237 aju_cons_jtag_present = 1; 238 aju_cons_jtag_missed = 0; 239 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 240 aju_cons_control_write(v); 241 } 242 while ((v & ALTERA_JTAG_UART_CONTROL_WSPACE) == 0) { 243 if (!aju_cons_jtag_present) 244 return; 245 DELAY(altera_jtag_uart_ac_poll_delay); 246 v = aju_cons_control_read(); 247 if (v & ALTERA_JTAG_UART_CONTROL_AC) { 248 aju_cons_jtag_present = 1; 249 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 250 aju_cons_control_write(v); 251 } else 252 aju_cons_jtag_present = 0; 253 } 254 aju_cons_data_write(ch); 255 } 256 257 static char 258 aju_cons_read(void) 259 { 260 261 AJU_CONSOLE_LOCK_ASSERT(); 262 263 while (!aju_cons_readable()); 264 aju_cons_buffer_valid = 0; 265 return (aju_cons_buffer_data); 266 } 267 268 /* 269 * Implementation of a FreeBSD low-level, polled console driver. 270 */ 271 static void 272 aju_cnprobe(struct consdev *cp) 273 { 274 275 sprintf(cp->cn_name, "%s%d", AJU_TTYNAME, 0); 276 cp->cn_pri = (boothowto & RB_SERIAL) ? CN_REMOTE : CN_NORMAL; 277 } 278 279 static void 280 aju_cninit(struct consdev *cp) 281 { 282 uint32_t v; 283 284 AJU_CONSOLE_LOCK_INIT(); 285 286 AJU_CONSOLE_LOCK(); 287 v = aju_cons_control_read(); 288 v &= ~ALTERA_JTAG_UART_CONTROL_AC; 289 aju_cons_control_write(v); 290 AJU_CONSOLE_UNLOCK(); 291 } 292 293 static void 294 aju_cnterm(struct consdev *cp) 295 { 296 297 } 298 299 static int 300 aju_cngetc(struct consdev *cp) 301 { 302 int ret; 303 304 AJU_CONSOLE_LOCK(); 305 ret = aju_cons_read(); 306 AJU_CONSOLE_UNLOCK(); 307 return (ret); 308 } 309 310 static void 311 aju_cnputc(struct consdev *cp, int c) 312 { 313 314 AJU_CONSOLE_LOCK(); 315 aju_cons_write(c); 316 AJU_CONSOLE_UNLOCK(); 317 } 318 319 static void 320 aju_cngrab(struct consdev *cp) 321 { 322 323 } 324 325 static void 326 aju_cnungrab(struct consdev *cp) 327 { 328 329 } 330 331 CONSOLE_DRIVER(aju); 332