1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 13 ** 14 ** Redistribution and use in source and binary forms, with or without 15 ** modification, are permitted provided that the following conditions 16 ** are met: 17 ** 1. Redistributions of source code must retain the above copyright 18 ** notice, this list of conditions and the following disclaimer. 19 ** 2. Redistributions in binary form must reproduce the above copyright 20 ** notice, this list of conditions and the following disclaimer in the 21 ** documentation and/or other materials provided with the distribution. 22 ** 3. The name of the author may not be used to endorse or promote products 23 ** derived from this software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ******************************************************************************** 36 ** History 37 ** 38 ** REV# DATE NAME DESCRIPTION 39 ** 1.00.00.00 03/31/2004 Erich Chen First release 40 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 41 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 42 ** clean unused function 43 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 44 ** firmware version check 45 ** and firmware update notify for hardware bug fix 46 ** handling if none zero high part physical address 47 ** of srb resource 48 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 49 ** add iop message xfer 50 ** with scsi pass-through command 51 ** add new device id of sas raid adapters 52 ** code fit for SPARC64 & PPC 53 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 54 ** and cause g_vfs_done() read write error 55 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 56 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 57 ** bus_dmamem_alloc() with BUS_DMA_ZERO 58 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 59 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 60 ** prevent cam_periph_error removing all LUN devices of one Target id 61 ** for any one LUN device failed 62 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 63 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 64 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 65 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 66 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 67 ** 02/14/2011 Ching Huang Modified pktRequestCount 68 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 69 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 70 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 71 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 72 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 73 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 74 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 75 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 76 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 77 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 78 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 79 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 80 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 81 ****************************************************************************************** 82 */ 83 84 #include <sys/cdefs.h> 85 __FBSDID("$FreeBSD$"); 86 87 #if 0 88 #define ARCMSR_DEBUG1 1 89 #endif 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/malloc.h> 93 #include <sys/kernel.h> 94 #include <sys/bus.h> 95 #include <sys/queue.h> 96 #include <sys/stat.h> 97 #include <sys/devicestat.h> 98 #include <sys/kthread.h> 99 #include <sys/module.h> 100 #include <sys/proc.h> 101 #include <sys/lock.h> 102 #include <sys/sysctl.h> 103 #include <sys/poll.h> 104 #include <sys/ioccom.h> 105 #include <vm/vm.h> 106 #include <vm/vm_param.h> 107 #include <vm/pmap.h> 108 109 #include <isa/rtc.h> 110 111 #include <machine/bus.h> 112 #include <machine/resource.h> 113 #include <machine/atomic.h> 114 #include <sys/conf.h> 115 #include <sys/rman.h> 116 117 #include <cam/cam.h> 118 #include <cam/cam_ccb.h> 119 #include <cam/cam_sim.h> 120 #include <cam/cam_periph.h> 121 #include <cam/cam_xpt_periph.h> 122 #include <cam/cam_xpt_sim.h> 123 #include <cam/cam_debug.h> 124 #include <cam/scsi/scsi_all.h> 125 #include <cam/scsi/scsi_message.h> 126 /* 127 ************************************************************************** 128 ************************************************************************** 129 */ 130 #if __FreeBSD_version >= 500005 131 #include <sys/selinfo.h> 132 #include <sys/mutex.h> 133 #include <sys/endian.h> 134 #include <dev/pci/pcivar.h> 135 #include <dev/pci/pcireg.h> 136 #else 137 #include <sys/select.h> 138 #include <pci/pcivar.h> 139 #include <pci/pcireg.h> 140 #endif 141 142 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 143 #define CAM_NEW_TRAN_CODE 1 144 #endif 145 146 #if __FreeBSD_version > 500000 147 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 148 #else 149 #define arcmsr_callout_init(a) callout_init(a); 150 #endif 151 152 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.40.00.00 2017-07-11" 153 #include <dev/arcmsr/arcmsr.h> 154 /* 155 ************************************************************************** 156 ************************************************************************** 157 */ 158 static void arcmsr_free_srb(struct CommandControlBlock *srb); 159 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 160 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 161 static int arcmsr_probe(device_t dev); 162 static int arcmsr_attach(device_t dev); 163 static int arcmsr_detach(device_t dev); 164 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 165 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 166 static int arcmsr_shutdown(device_t dev); 167 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 168 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 169 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 170 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 171 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 172 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 173 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 174 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 175 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 176 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 177 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 178 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 179 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 180 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 181 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 182 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 183 static int arcmsr_resume(device_t dev); 184 static int arcmsr_suspend(device_t dev); 185 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 186 static void arcmsr_polling_devmap(void *arg); 187 static void arcmsr_srb_timeout(void *arg); 188 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 189 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 190 void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 191 #ifdef ARCMSR_DEBUG1 192 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 193 #endif 194 /* 195 ************************************************************************** 196 ************************************************************************** 197 */ 198 static void UDELAY(u_int32_t us) { DELAY(us); } 199 /* 200 ************************************************************************** 201 ************************************************************************** 202 */ 203 static bus_dmamap_callback_t arcmsr_map_free_srb; 204 static bus_dmamap_callback_t arcmsr_execute_srb; 205 /* 206 ************************************************************************** 207 ************************************************************************** 208 */ 209 static d_open_t arcmsr_open; 210 static d_close_t arcmsr_close; 211 static d_ioctl_t arcmsr_ioctl; 212 213 static device_method_t arcmsr_methods[]={ 214 DEVMETHOD(device_probe, arcmsr_probe), 215 DEVMETHOD(device_attach, arcmsr_attach), 216 DEVMETHOD(device_detach, arcmsr_detach), 217 DEVMETHOD(device_shutdown, arcmsr_shutdown), 218 DEVMETHOD(device_suspend, arcmsr_suspend), 219 DEVMETHOD(device_resume, arcmsr_resume), 220 221 #if __FreeBSD_version >= 803000 222 DEVMETHOD_END 223 #else 224 { 0, 0 } 225 #endif 226 }; 227 228 static driver_t arcmsr_driver={ 229 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 230 }; 231 232 static devclass_t arcmsr_devclass; 233 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 234 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 235 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 236 #ifndef BUS_DMA_COHERENT 237 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 238 #endif 239 #if __FreeBSD_version >= 501000 240 static struct cdevsw arcmsr_cdevsw={ 241 #if __FreeBSD_version >= 503000 242 .d_version = D_VERSION, 243 #endif 244 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 245 .d_flags = D_NEEDGIANT, 246 #endif 247 .d_open = arcmsr_open, /* open */ 248 .d_close = arcmsr_close, /* close */ 249 .d_ioctl = arcmsr_ioctl, /* ioctl */ 250 .d_name = "arcmsr", /* name */ 251 }; 252 #else 253 #define ARCMSR_CDEV_MAJOR 180 254 255 static struct cdevsw arcmsr_cdevsw = { 256 arcmsr_open, /* open */ 257 arcmsr_close, /* close */ 258 noread, /* read */ 259 nowrite, /* write */ 260 arcmsr_ioctl, /* ioctl */ 261 nopoll, /* poll */ 262 nommap, /* mmap */ 263 nostrategy, /* strategy */ 264 "arcmsr", /* name */ 265 ARCMSR_CDEV_MAJOR, /* major */ 266 nodump, /* dump */ 267 nopsize, /* psize */ 268 0 /* flags */ 269 }; 270 #endif 271 /* 272 ************************************************************************** 273 ************************************************************************** 274 */ 275 #if __FreeBSD_version < 500005 276 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 277 #else 278 #if __FreeBSD_version < 503000 279 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 280 #else 281 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 282 #endif 283 #endif 284 { 285 #if __FreeBSD_version < 503000 286 struct AdapterControlBlock *acb = dev->si_drv1; 287 #else 288 int unit = dev2unit(dev); 289 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 290 #endif 291 if(acb == NULL) { 292 return ENXIO; 293 } 294 return (0); 295 } 296 /* 297 ************************************************************************** 298 ************************************************************************** 299 */ 300 #if __FreeBSD_version < 500005 301 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 302 #else 303 #if __FreeBSD_version < 503000 304 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 305 #else 306 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 307 #endif 308 #endif 309 { 310 #if __FreeBSD_version < 503000 311 struct AdapterControlBlock *acb = dev->si_drv1; 312 #else 313 int unit = dev2unit(dev); 314 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 315 #endif 316 if(acb == NULL) { 317 return ENXIO; 318 } 319 return 0; 320 } 321 /* 322 ************************************************************************** 323 ************************************************************************** 324 */ 325 #if __FreeBSD_version < 500005 326 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 327 #else 328 #if __FreeBSD_version < 503000 329 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 330 #else 331 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 332 #endif 333 #endif 334 { 335 #if __FreeBSD_version < 503000 336 struct AdapterControlBlock *acb = dev->si_drv1; 337 #else 338 int unit = dev2unit(dev); 339 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 340 #endif 341 342 if(acb == NULL) { 343 return ENXIO; 344 } 345 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 346 } 347 /* 348 ********************************************************************** 349 ********************************************************************** 350 */ 351 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 352 { 353 u_int32_t intmask_org = 0; 354 355 switch (acb->adapter_type) { 356 case ACB_ADAPTER_TYPE_A: { 357 /* disable all outbound interrupt */ 358 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 359 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 360 } 361 break; 362 case ACB_ADAPTER_TYPE_B: { 363 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 364 /* disable all outbound interrupt */ 365 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 366 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 367 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 368 } 369 break; 370 case ACB_ADAPTER_TYPE_C: { 371 /* disable all outbound interrupt */ 372 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 373 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 374 } 375 break; 376 case ACB_ADAPTER_TYPE_D: { 377 /* disable all outbound interrupt */ 378 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 379 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 380 } 381 break; 382 case ACB_ADAPTER_TYPE_E: { 383 /* disable all outbound interrupt */ 384 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 385 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 386 } 387 break; 388 } 389 return (intmask_org); 390 } 391 /* 392 ********************************************************************** 393 ********************************************************************** 394 */ 395 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 396 { 397 u_int32_t mask; 398 399 switch (acb->adapter_type) { 400 case ACB_ADAPTER_TYPE_A: { 401 /* enable outbound Post Queue, outbound doorbell Interrupt */ 402 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 403 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 404 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 405 } 406 break; 407 case ACB_ADAPTER_TYPE_B: { 408 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 409 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 410 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 411 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 412 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 413 } 414 break; 415 case ACB_ADAPTER_TYPE_C: { 416 /* enable outbound Post Queue, outbound doorbell Interrupt */ 417 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 418 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 419 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 420 } 421 break; 422 case ACB_ADAPTER_TYPE_D: { 423 /* enable outbound Post Queue, outbound doorbell Interrupt */ 424 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 425 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 426 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 427 acb->outbound_int_enable = mask; 428 } 429 break; 430 case ACB_ADAPTER_TYPE_E: { 431 /* enable outbound Post Queue, outbound doorbell Interrupt */ 432 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 433 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 434 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 435 } 436 break; 437 } 438 } 439 /* 440 ********************************************************************** 441 ********************************************************************** 442 */ 443 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 444 { 445 u_int32_t Index; 446 u_int8_t Retries = 0x00; 447 448 do { 449 for(Index=0; Index < 100; Index++) { 450 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 451 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 452 return TRUE; 453 } 454 UDELAY(10000); 455 }/*max 1 seconds*/ 456 }while(Retries++ < 20);/*max 20 sec*/ 457 return (FALSE); 458 } 459 /* 460 ********************************************************************** 461 ********************************************************************** 462 */ 463 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 464 { 465 u_int32_t Index; 466 u_int8_t Retries = 0x00; 467 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 468 469 do { 470 for(Index=0; Index < 100; Index++) { 471 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 472 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 473 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 474 return TRUE; 475 } 476 UDELAY(10000); 477 }/*max 1 seconds*/ 478 }while(Retries++ < 20);/*max 20 sec*/ 479 return (FALSE); 480 } 481 /* 482 ********************************************************************** 483 ********************************************************************** 484 */ 485 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 486 { 487 u_int32_t Index; 488 u_int8_t Retries = 0x00; 489 490 do { 491 for(Index=0; Index < 100; Index++) { 492 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 493 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 494 return TRUE; 495 } 496 UDELAY(10000); 497 }/*max 1 seconds*/ 498 }while(Retries++ < 20);/*max 20 sec*/ 499 return (FALSE); 500 } 501 /* 502 ********************************************************************** 503 ********************************************************************** 504 */ 505 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 506 { 507 u_int32_t Index; 508 u_int8_t Retries = 0x00; 509 510 do { 511 for(Index=0; Index < 100; Index++) { 512 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 513 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 514 return TRUE; 515 } 516 UDELAY(10000); 517 }/*max 1 seconds*/ 518 }while(Retries++ < 20);/*max 20 sec*/ 519 return (FALSE); 520 } 521 /* 522 ********************************************************************** 523 ********************************************************************** 524 */ 525 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 526 { 527 u_int32_t Index, read_doorbell; 528 u_int8_t Retries = 0x00; 529 530 do { 531 for(Index=0; Index < 100; Index++) { 532 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 533 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 534 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 535 acb->in_doorbell = read_doorbell; 536 return TRUE; 537 } 538 UDELAY(10000); 539 }/*max 1 seconds*/ 540 }while(Retries++ < 20);/*max 20 sec*/ 541 return (FALSE); 542 } 543 /* 544 ************************************************************************ 545 ************************************************************************ 546 */ 547 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 548 { 549 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 550 551 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 552 do { 553 if(arcmsr_hba_wait_msgint_ready(acb)) { 554 break; 555 } else { 556 retry_count--; 557 } 558 }while(retry_count != 0); 559 } 560 /* 561 ************************************************************************ 562 ************************************************************************ 563 */ 564 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 565 { 566 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 567 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 568 569 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 570 do { 571 if(arcmsr_hbb_wait_msgint_ready(acb)) { 572 break; 573 } else { 574 retry_count--; 575 } 576 }while(retry_count != 0); 577 } 578 /* 579 ************************************************************************ 580 ************************************************************************ 581 */ 582 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 583 { 584 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 585 586 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 587 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 588 do { 589 if(arcmsr_hbc_wait_msgint_ready(acb)) { 590 break; 591 } else { 592 retry_count--; 593 } 594 }while(retry_count != 0); 595 } 596 /* 597 ************************************************************************ 598 ************************************************************************ 599 */ 600 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 601 { 602 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 603 604 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 605 do { 606 if(arcmsr_hbd_wait_msgint_ready(acb)) { 607 break; 608 } else { 609 retry_count--; 610 } 611 }while(retry_count != 0); 612 } 613 /* 614 ************************************************************************ 615 ************************************************************************ 616 */ 617 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 618 { 619 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 620 621 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 622 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 623 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 624 do { 625 if(arcmsr_hbe_wait_msgint_ready(acb)) { 626 break; 627 } else { 628 retry_count--; 629 } 630 }while(retry_count != 0); 631 } 632 /* 633 ************************************************************************ 634 ************************************************************************ 635 */ 636 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 637 { 638 switch (acb->adapter_type) { 639 case ACB_ADAPTER_TYPE_A: { 640 arcmsr_flush_hba_cache(acb); 641 } 642 break; 643 case ACB_ADAPTER_TYPE_B: { 644 arcmsr_flush_hbb_cache(acb); 645 } 646 break; 647 case ACB_ADAPTER_TYPE_C: { 648 arcmsr_flush_hbc_cache(acb); 649 } 650 break; 651 case ACB_ADAPTER_TYPE_D: { 652 arcmsr_flush_hbd_cache(acb); 653 } 654 break; 655 case ACB_ADAPTER_TYPE_E: { 656 arcmsr_flush_hbe_cache(acb); 657 } 658 break; 659 } 660 } 661 /* 662 ******************************************************************************* 663 ******************************************************************************* 664 */ 665 static int arcmsr_suspend(device_t dev) 666 { 667 struct AdapterControlBlock *acb = device_get_softc(dev); 668 669 /* flush controller */ 670 arcmsr_iop_parking(acb); 671 /* disable all outbound interrupt */ 672 arcmsr_disable_allintr(acb); 673 return(0); 674 } 675 /* 676 ******************************************************************************* 677 ******************************************************************************* 678 */ 679 static int arcmsr_resume(device_t dev) 680 { 681 struct AdapterControlBlock *acb = device_get_softc(dev); 682 683 arcmsr_iop_init(acb); 684 return(0); 685 } 686 /* 687 ********************************************************************************* 688 ********************************************************************************* 689 */ 690 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 691 { 692 struct AdapterControlBlock *acb; 693 u_int8_t target_id, target_lun; 694 struct cam_sim *sim; 695 696 sim = (struct cam_sim *) cb_arg; 697 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 698 switch (code) { 699 case AC_LOST_DEVICE: 700 target_id = xpt_path_target_id(path); 701 target_lun = xpt_path_lun_id(path); 702 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 703 break; 704 } 705 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 706 break; 707 default: 708 break; 709 } 710 } 711 /* 712 ********************************************************************** 713 ********************************************************************** 714 */ 715 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 716 { 717 union ccb *pccb = srb->pccb; 718 719 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 720 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 721 if(pccb->csio.sense_len) { 722 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 723 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 724 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 725 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 726 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 727 } 728 } 729 /* 730 ********************************************************************* 731 ********************************************************************* 732 */ 733 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 734 { 735 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 736 if(!arcmsr_hba_wait_msgint_ready(acb)) { 737 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 738 } 739 } 740 /* 741 ********************************************************************* 742 ********************************************************************* 743 */ 744 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 745 { 746 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 747 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 748 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 749 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 750 } 751 } 752 /* 753 ********************************************************************* 754 ********************************************************************* 755 */ 756 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 757 { 758 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 759 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 760 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 761 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 762 } 763 } 764 /* 765 ********************************************************************* 766 ********************************************************************* 767 */ 768 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 769 { 770 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 771 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 772 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 773 } 774 } 775 /* 776 ********************************************************************* 777 ********************************************************************* 778 */ 779 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 780 { 781 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 782 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 783 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 784 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 785 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 786 } 787 } 788 /* 789 ********************************************************************* 790 ********************************************************************* 791 */ 792 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 793 { 794 switch (acb->adapter_type) { 795 case ACB_ADAPTER_TYPE_A: { 796 arcmsr_abort_hba_allcmd(acb); 797 } 798 break; 799 case ACB_ADAPTER_TYPE_B: { 800 arcmsr_abort_hbb_allcmd(acb); 801 } 802 break; 803 case ACB_ADAPTER_TYPE_C: { 804 arcmsr_abort_hbc_allcmd(acb); 805 } 806 break; 807 case ACB_ADAPTER_TYPE_D: { 808 arcmsr_abort_hbd_allcmd(acb); 809 } 810 break; 811 case ACB_ADAPTER_TYPE_E: { 812 arcmsr_abort_hbe_allcmd(acb); 813 } 814 break; 815 } 816 } 817 /* 818 ********************************************************************** 819 ********************************************************************** 820 */ 821 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 822 { 823 struct AdapterControlBlock *acb = srb->acb; 824 union ccb *pccb = srb->pccb; 825 826 if(srb->srb_flags & SRB_FLAG_TIMER_START) 827 callout_stop(&srb->ccb_callout); 828 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 829 bus_dmasync_op_t op; 830 831 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 832 op = BUS_DMASYNC_POSTREAD; 833 } else { 834 op = BUS_DMASYNC_POSTWRITE; 835 } 836 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 837 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 838 } 839 if(stand_flag == 1) { 840 atomic_subtract_int(&acb->srboutstandingcount, 1); 841 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 842 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 843 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 844 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 845 } 846 } 847 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 848 arcmsr_free_srb(srb); 849 acb->pktReturnCount++; 850 xpt_done(pccb); 851 } 852 /* 853 ************************************************************************** 854 ************************************************************************** 855 */ 856 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 857 { 858 int target, lun; 859 860 target = srb->pccb->ccb_h.target_id; 861 lun = srb->pccb->ccb_h.target_lun; 862 if(error == FALSE) { 863 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 864 acb->devstate[target][lun] = ARECA_RAID_GOOD; 865 } 866 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 867 arcmsr_srb_complete(srb, 1); 868 } else { 869 switch(srb->arcmsr_cdb.DeviceStatus) { 870 case ARCMSR_DEV_SELECT_TIMEOUT: { 871 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 872 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 873 } 874 acb->devstate[target][lun] = ARECA_RAID_GONE; 875 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 876 arcmsr_srb_complete(srb, 1); 877 } 878 break; 879 case ARCMSR_DEV_ABORTED: 880 case ARCMSR_DEV_INIT_FAIL: { 881 acb->devstate[target][lun] = ARECA_RAID_GONE; 882 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 883 arcmsr_srb_complete(srb, 1); 884 } 885 break; 886 case SCSISTAT_CHECK_CONDITION: { 887 acb->devstate[target][lun] = ARECA_RAID_GOOD; 888 arcmsr_report_sense_info(srb); 889 arcmsr_srb_complete(srb, 1); 890 } 891 break; 892 default: 893 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 894 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 895 acb->devstate[target][lun] = ARECA_RAID_GONE; 896 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 897 /*unknown error or crc error just for retry*/ 898 arcmsr_srb_complete(srb, 1); 899 break; 900 } 901 } 902 } 903 /* 904 ************************************************************************** 905 ************************************************************************** 906 */ 907 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 908 { 909 struct CommandControlBlock *srb; 910 911 /* check if command done with no error*/ 912 switch (acb->adapter_type) { 913 case ACB_ADAPTER_TYPE_C: 914 case ACB_ADAPTER_TYPE_D: 915 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 916 break; 917 case ACB_ADAPTER_TYPE_E: 918 srb = acb->psrb_pool[flag_srb]; 919 break; 920 case ACB_ADAPTER_TYPE_A: 921 case ACB_ADAPTER_TYPE_B: 922 default: 923 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 924 break; 925 } 926 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 927 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 928 arcmsr_free_srb(srb); 929 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 930 return; 931 } 932 printf("arcmsr%d: return srb has been completed\n" 933 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 934 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 935 return; 936 } 937 arcmsr_report_srb_state(acb, srb, error); 938 } 939 /* 940 ************************************************************************** 941 ************************************************************************** 942 */ 943 static void arcmsr_srb_timeout(void *arg) 944 { 945 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 946 struct AdapterControlBlock *acb; 947 int target, lun; 948 u_int8_t cmd; 949 950 target = srb->pccb->ccb_h.target_id; 951 lun = srb->pccb->ccb_h.target_lun; 952 acb = srb->acb; 953 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 954 if(srb->srb_state == ARCMSR_SRB_START) 955 { 956 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 957 srb->srb_state = ARCMSR_SRB_TIMEOUT; 958 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 959 arcmsr_srb_complete(srb, 1); 960 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 961 acb->pci_unit, target, lun, cmd, srb); 962 } 963 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 964 #ifdef ARCMSR_DEBUG1 965 arcmsr_dump_data(acb); 966 #endif 967 } 968 969 /* 970 ********************************************************************** 971 ********************************************************************** 972 */ 973 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 974 { 975 int i=0; 976 u_int32_t flag_srb; 977 u_int16_t error; 978 979 switch (acb->adapter_type) { 980 case ACB_ADAPTER_TYPE_A: { 981 u_int32_t outbound_intstatus; 982 983 /*clear and abort all outbound posted Q*/ 984 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 985 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 986 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 987 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 988 arcmsr_drain_donequeue(acb, flag_srb, error); 989 } 990 } 991 break; 992 case ACB_ADAPTER_TYPE_B: { 993 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 994 995 /*clear all outbound posted Q*/ 996 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 997 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 998 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 999 phbbmu->done_qbuffer[i] = 0; 1000 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1001 arcmsr_drain_donequeue(acb, flag_srb, error); 1002 } 1003 phbbmu->post_qbuffer[i] = 0; 1004 }/*drain reply FIFO*/ 1005 phbbmu->doneq_index = 0; 1006 phbbmu->postq_index = 0; 1007 } 1008 break; 1009 case ACB_ADAPTER_TYPE_C: { 1010 1011 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 1012 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1013 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 1014 arcmsr_drain_donequeue(acb, flag_srb, error); 1015 } 1016 } 1017 break; 1018 case ACB_ADAPTER_TYPE_D: { 1019 arcmsr_hbd_postqueue_isr(acb); 1020 } 1021 break; 1022 case ACB_ADAPTER_TYPE_E: { 1023 arcmsr_hbe_postqueue_isr(acb); 1024 } 1025 break; 1026 } 1027 } 1028 /* 1029 **************************************************************************** 1030 **************************************************************************** 1031 */ 1032 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 1033 { 1034 struct CommandControlBlock *srb; 1035 u_int32_t intmask_org; 1036 u_int32_t i=0; 1037 1038 if(acb->srboutstandingcount>0) { 1039 /* disable all outbound interrupt */ 1040 intmask_org = arcmsr_disable_allintr(acb); 1041 /*clear and abort all outbound posted Q*/ 1042 arcmsr_done4abort_postqueue(acb); 1043 /* talk to iop 331 outstanding command aborted*/ 1044 arcmsr_abort_allcmd(acb); 1045 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 1046 srb = acb->psrb_pool[i]; 1047 if(srb->srb_state == ARCMSR_SRB_START) { 1048 srb->srb_state = ARCMSR_SRB_ABORTED; 1049 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1050 arcmsr_srb_complete(srb, 1); 1051 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 1052 , acb->pci_unit, srb->pccb->ccb_h.target_id 1053 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 1054 } 1055 } 1056 /* enable all outbound interrupt */ 1057 arcmsr_enable_allintr(acb, intmask_org); 1058 } 1059 acb->srboutstandingcount = 0; 1060 acb->workingsrb_doneindex = 0; 1061 acb->workingsrb_startindex = 0; 1062 acb->pktRequestCount = 0; 1063 acb->pktReturnCount = 0; 1064 } 1065 /* 1066 ********************************************************************** 1067 ********************************************************************** 1068 */ 1069 static void arcmsr_build_srb(struct CommandControlBlock *srb, 1070 bus_dma_segment_t *dm_segs, u_int32_t nseg) 1071 { 1072 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 1073 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 1074 u_int32_t address_lo, address_hi; 1075 union ccb *pccb = srb->pccb; 1076 struct ccb_scsiio *pcsio = &pccb->csio; 1077 u_int32_t arccdbsize = 0x30; 1078 1079 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1080 arcmsr_cdb->Bus = 0; 1081 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1082 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1083 arcmsr_cdb->Function = 1; 1084 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1085 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1086 if(nseg != 0) { 1087 struct AdapterControlBlock *acb = srb->acb; 1088 bus_dmasync_op_t op; 1089 u_int32_t length, i, cdb_sgcount = 0; 1090 1091 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1092 op = BUS_DMASYNC_PREREAD; 1093 } else { 1094 op = BUS_DMASYNC_PREWRITE; 1095 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1096 srb->srb_flags |= SRB_FLAG_WRITE; 1097 } 1098 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1099 for(i=0; i < nseg; i++) { 1100 /* Get the physical address of the current data pointer */ 1101 length = arcmsr_htole32(dm_segs[i].ds_len); 1102 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1103 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1104 if(address_hi == 0) { 1105 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1106 pdma_sg->address = address_lo; 1107 pdma_sg->length = length; 1108 psge += sizeof(struct SG32ENTRY); 1109 arccdbsize += sizeof(struct SG32ENTRY); 1110 } else { 1111 u_int32_t sg64s_size = 0, tmplength = length; 1112 1113 while(1) { 1114 u_int64_t span4G, length0; 1115 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1116 1117 span4G = (u_int64_t)address_lo + tmplength; 1118 pdma_sg->addresshigh = address_hi; 1119 pdma_sg->address = address_lo; 1120 if(span4G > 0x100000000) { 1121 /*see if cross 4G boundary*/ 1122 length0 = 0x100000000-address_lo; 1123 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1124 address_hi = address_hi+1; 1125 address_lo = 0; 1126 tmplength = tmplength - (u_int32_t)length0; 1127 sg64s_size += sizeof(struct SG64ENTRY); 1128 psge += sizeof(struct SG64ENTRY); 1129 cdb_sgcount++; 1130 } else { 1131 pdma_sg->length = tmplength | IS_SG64_ADDR; 1132 sg64s_size += sizeof(struct SG64ENTRY); 1133 psge += sizeof(struct SG64ENTRY); 1134 break; 1135 } 1136 } 1137 arccdbsize += sg64s_size; 1138 } 1139 cdb_sgcount++; 1140 } 1141 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1142 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1143 if( arccdbsize > 256) { 1144 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1145 } 1146 } else { 1147 arcmsr_cdb->DataLength = 0; 1148 } 1149 srb->arc_cdb_size = arccdbsize; 1150 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1151 } 1152 /* 1153 ************************************************************************** 1154 ************************************************************************** 1155 */ 1156 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1157 { 1158 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1159 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1160 1161 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1162 atomic_add_int(&acb->srboutstandingcount, 1); 1163 srb->srb_state = ARCMSR_SRB_START; 1164 1165 switch (acb->adapter_type) { 1166 case ACB_ADAPTER_TYPE_A: { 1167 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1168 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1169 } else { 1170 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1171 } 1172 } 1173 break; 1174 case ACB_ADAPTER_TYPE_B: { 1175 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1176 int ending_index, index; 1177 1178 index = phbbmu->postq_index; 1179 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1180 phbbmu->post_qbuffer[ending_index] = 0; 1181 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1182 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1183 } else { 1184 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1185 } 1186 index++; 1187 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1188 phbbmu->postq_index = index; 1189 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1190 } 1191 break; 1192 case ACB_ADAPTER_TYPE_C: { 1193 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1194 1195 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1196 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1197 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1198 if(cdb_phyaddr_hi32) 1199 { 1200 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1201 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1202 } 1203 else 1204 { 1205 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1206 } 1207 } 1208 break; 1209 case ACB_ADAPTER_TYPE_D: { 1210 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1211 u_int16_t index_stripped; 1212 u_int16_t postq_index; 1213 struct InBound_SRB *pinbound_srb; 1214 1215 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1216 postq_index = phbdmu->postq_index; 1217 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1218 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1219 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1220 pinbound_srb->length = srb->arc_cdb_size >> 2; 1221 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1222 if (postq_index & 0x4000) { 1223 index_stripped = postq_index & 0xFF; 1224 index_stripped += 1; 1225 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1226 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1227 } else { 1228 index_stripped = postq_index; 1229 index_stripped += 1; 1230 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1231 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1232 } 1233 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1234 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1235 } 1236 break; 1237 case ACB_ADAPTER_TYPE_E: { 1238 u_int32_t ccb_post_stamp, arc_cdb_size; 1239 1240 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1241 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1242 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1243 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1244 } 1245 break; 1246 } 1247 } 1248 /* 1249 ************************************************************************ 1250 ************************************************************************ 1251 */ 1252 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1253 { 1254 struct QBUFFER *qbuffer=NULL; 1255 1256 switch (acb->adapter_type) { 1257 case ACB_ADAPTER_TYPE_A: { 1258 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1259 1260 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1261 } 1262 break; 1263 case ACB_ADAPTER_TYPE_B: { 1264 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1265 1266 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1267 } 1268 break; 1269 case ACB_ADAPTER_TYPE_C: { 1270 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1271 1272 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1273 } 1274 break; 1275 case ACB_ADAPTER_TYPE_D: { 1276 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1277 1278 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1279 } 1280 break; 1281 case ACB_ADAPTER_TYPE_E: { 1282 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1283 1284 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1285 } 1286 break; 1287 } 1288 return(qbuffer); 1289 } 1290 /* 1291 ************************************************************************ 1292 ************************************************************************ 1293 */ 1294 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1295 { 1296 struct QBUFFER *qbuffer = NULL; 1297 1298 switch (acb->adapter_type) { 1299 case ACB_ADAPTER_TYPE_A: { 1300 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1301 1302 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1303 } 1304 break; 1305 case ACB_ADAPTER_TYPE_B: { 1306 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1307 1308 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1309 } 1310 break; 1311 case ACB_ADAPTER_TYPE_C: { 1312 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1313 1314 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1315 } 1316 break; 1317 case ACB_ADAPTER_TYPE_D: { 1318 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1319 1320 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1321 } 1322 break; 1323 case ACB_ADAPTER_TYPE_E: { 1324 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1325 1326 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1327 } 1328 break; 1329 } 1330 return(qbuffer); 1331 } 1332 /* 1333 ************************************************************************** 1334 ************************************************************************** 1335 */ 1336 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1337 { 1338 switch (acb->adapter_type) { 1339 case ACB_ADAPTER_TYPE_A: { 1340 /* let IOP know data has been read */ 1341 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1342 } 1343 break; 1344 case ACB_ADAPTER_TYPE_B: { 1345 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1346 /* let IOP know data has been read */ 1347 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1348 } 1349 break; 1350 case ACB_ADAPTER_TYPE_C: { 1351 /* let IOP know data has been read */ 1352 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1353 } 1354 break; 1355 case ACB_ADAPTER_TYPE_D: { 1356 /* let IOP know data has been read */ 1357 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1358 } 1359 break; 1360 case ACB_ADAPTER_TYPE_E: { 1361 /* let IOP know data has been read */ 1362 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1363 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1364 } 1365 break; 1366 } 1367 } 1368 /* 1369 ************************************************************************** 1370 ************************************************************************** 1371 */ 1372 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1373 { 1374 switch (acb->adapter_type) { 1375 case ACB_ADAPTER_TYPE_A: { 1376 /* 1377 ** push inbound doorbell tell iop, driver data write ok 1378 ** and wait reply on next hwinterrupt for next Qbuffer post 1379 */ 1380 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1381 } 1382 break; 1383 case ACB_ADAPTER_TYPE_B: { 1384 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1385 /* 1386 ** push inbound doorbell tell iop, driver data write ok 1387 ** and wait reply on next hwinterrupt for next Qbuffer post 1388 */ 1389 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1390 } 1391 break; 1392 case ACB_ADAPTER_TYPE_C: { 1393 /* 1394 ** push inbound doorbell tell iop, driver data write ok 1395 ** and wait reply on next hwinterrupt for next Qbuffer post 1396 */ 1397 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1398 } 1399 break; 1400 case ACB_ADAPTER_TYPE_D: { 1401 /* 1402 ** push inbound doorbell tell iop, driver data write ok 1403 ** and wait reply on next hwinterrupt for next Qbuffer post 1404 */ 1405 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1406 } 1407 break; 1408 case ACB_ADAPTER_TYPE_E: { 1409 /* 1410 ** push inbound doorbell tell iop, driver data write ok 1411 ** and wait reply on next hwinterrupt for next Qbuffer post 1412 */ 1413 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1414 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1415 } 1416 break; 1417 } 1418 } 1419 /* 1420 ************************************************************************ 1421 ************************************************************************ 1422 */ 1423 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1424 { 1425 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1426 CHIP_REG_WRITE32(HBA_MessageUnit, 1427 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1428 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1429 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1430 , acb->pci_unit); 1431 } 1432 } 1433 /* 1434 ************************************************************************ 1435 ************************************************************************ 1436 */ 1437 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1438 { 1439 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1440 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1441 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1442 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1443 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1444 , acb->pci_unit); 1445 } 1446 } 1447 /* 1448 ************************************************************************ 1449 ************************************************************************ 1450 */ 1451 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1452 { 1453 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1454 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1455 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1456 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1457 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1458 } 1459 } 1460 /* 1461 ************************************************************************ 1462 ************************************************************************ 1463 */ 1464 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1465 { 1466 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1467 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1468 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1469 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1470 } 1471 } 1472 /* 1473 ************************************************************************ 1474 ************************************************************************ 1475 */ 1476 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1477 { 1478 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1479 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1480 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1481 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1482 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1483 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1484 } 1485 } 1486 /* 1487 ************************************************************************ 1488 ************************************************************************ 1489 */ 1490 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1491 { 1492 switch (acb->adapter_type) { 1493 case ACB_ADAPTER_TYPE_A: { 1494 arcmsr_stop_hba_bgrb(acb); 1495 } 1496 break; 1497 case ACB_ADAPTER_TYPE_B: { 1498 arcmsr_stop_hbb_bgrb(acb); 1499 } 1500 break; 1501 case ACB_ADAPTER_TYPE_C: { 1502 arcmsr_stop_hbc_bgrb(acb); 1503 } 1504 break; 1505 case ACB_ADAPTER_TYPE_D: { 1506 arcmsr_stop_hbd_bgrb(acb); 1507 } 1508 break; 1509 case ACB_ADAPTER_TYPE_E: { 1510 arcmsr_stop_hbe_bgrb(acb); 1511 } 1512 break; 1513 } 1514 } 1515 /* 1516 ************************************************************************ 1517 ************************************************************************ 1518 */ 1519 static void arcmsr_poll(struct cam_sim *psim) 1520 { 1521 struct AdapterControlBlock *acb; 1522 int mutex; 1523 1524 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1525 mutex = mtx_owned(&acb->isr_lock); 1526 if( mutex == 0 ) 1527 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1528 arcmsr_interrupt(acb); 1529 if( mutex == 0 ) 1530 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1531 } 1532 /* 1533 ************************************************************************** 1534 ************************************************************************** 1535 */ 1536 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1537 struct QBUFFER *prbuffer) { 1538 1539 u_int8_t *pQbuffer; 1540 u_int8_t *buf1 = NULL; 1541 u_int32_t *iop_data, *buf2 = NULL; 1542 u_int32_t iop_len, data_len; 1543 1544 iop_data = (u_int32_t *)prbuffer->data; 1545 iop_len = (u_int32_t)prbuffer->data_len; 1546 if ( iop_len > 0 ) 1547 { 1548 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1549 buf2 = (u_int32_t *)buf1; 1550 if( buf1 == NULL) 1551 return (0); 1552 data_len = iop_len; 1553 while(data_len >= 4) 1554 { 1555 *buf2++ = *iop_data++; 1556 data_len -= 4; 1557 } 1558 if(data_len) 1559 *buf2 = *iop_data; 1560 buf2 = (u_int32_t *)buf1; 1561 } 1562 while (iop_len > 0) { 1563 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1564 *pQbuffer = *buf1; 1565 acb->rqbuf_lastindex++; 1566 /* if last, index number set it to 0 */ 1567 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1568 buf1++; 1569 iop_len--; 1570 } 1571 if(buf2) 1572 free( (u_int8_t *)buf2, M_DEVBUF); 1573 /* let IOP know data has been read */ 1574 arcmsr_iop_message_read(acb); 1575 return (1); 1576 } 1577 /* 1578 ************************************************************************** 1579 ************************************************************************** 1580 */ 1581 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1582 struct QBUFFER *prbuffer) { 1583 1584 u_int8_t *pQbuffer; 1585 u_int8_t *iop_data; 1586 u_int32_t iop_len; 1587 1588 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) || 1589 (acb->adapter_type == ACB_ADAPTER_TYPE_E)) { 1590 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1591 } 1592 iop_data = (u_int8_t *)prbuffer->data; 1593 iop_len = (u_int32_t)prbuffer->data_len; 1594 while (iop_len > 0) { 1595 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1596 *pQbuffer = *iop_data; 1597 acb->rqbuf_lastindex++; 1598 /* if last, index number set it to 0 */ 1599 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1600 iop_data++; 1601 iop_len--; 1602 } 1603 /* let IOP know data has been read */ 1604 arcmsr_iop_message_read(acb); 1605 return (1); 1606 } 1607 /* 1608 ************************************************************************** 1609 ************************************************************************** 1610 */ 1611 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1612 { 1613 struct QBUFFER *prbuffer; 1614 int my_empty_len; 1615 1616 /*check this iop data if overflow my rqbuffer*/ 1617 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1618 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1619 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1620 (ARCMSR_MAX_QBUFFER-1); 1621 if(my_empty_len >= prbuffer->data_len) { 1622 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1623 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1624 } else { 1625 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1626 } 1627 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1628 } 1629 /* 1630 ********************************************************************** 1631 ********************************************************************** 1632 */ 1633 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1634 { 1635 u_int8_t *pQbuffer; 1636 struct QBUFFER *pwbuffer; 1637 u_int8_t *buf1 = NULL; 1638 u_int32_t *iop_data, *buf2 = NULL; 1639 u_int32_t allxfer_len = 0, data_len; 1640 1641 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1642 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1643 buf2 = (u_int32_t *)buf1; 1644 if( buf1 == NULL) 1645 return; 1646 1647 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1648 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1649 iop_data = (u_int32_t *)pwbuffer->data; 1650 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1651 && (allxfer_len < 124)) { 1652 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1653 *buf1 = *pQbuffer; 1654 acb->wqbuf_firstindex++; 1655 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1656 buf1++; 1657 allxfer_len++; 1658 } 1659 pwbuffer->data_len = allxfer_len; 1660 data_len = allxfer_len; 1661 buf1 = (u_int8_t *)buf2; 1662 while(data_len >= 4) 1663 { 1664 *iop_data++ = *buf2++; 1665 data_len -= 4; 1666 } 1667 if(data_len) 1668 *iop_data = *buf2; 1669 free( buf1, M_DEVBUF); 1670 arcmsr_iop_message_wrote(acb); 1671 } 1672 } 1673 /* 1674 ********************************************************************** 1675 ********************************************************************** 1676 */ 1677 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1678 { 1679 u_int8_t *pQbuffer; 1680 struct QBUFFER *pwbuffer; 1681 u_int8_t *iop_data; 1682 int32_t allxfer_len=0; 1683 1684 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) || 1685 (acb->adapter_type == ACB_ADAPTER_TYPE_E)) { 1686 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1687 return; 1688 } 1689 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1690 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1691 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1692 iop_data = (u_int8_t *)pwbuffer->data; 1693 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1694 && (allxfer_len < 124)) { 1695 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1696 *iop_data = *pQbuffer; 1697 acb->wqbuf_firstindex++; 1698 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1699 iop_data++; 1700 allxfer_len++; 1701 } 1702 pwbuffer->data_len = allxfer_len; 1703 arcmsr_iop_message_wrote(acb); 1704 } 1705 } 1706 /* 1707 ************************************************************************** 1708 ************************************************************************** 1709 */ 1710 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1711 { 1712 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1713 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1714 /* 1715 ***************************************************************** 1716 ** check if there are any mail packages from user space program 1717 ** in my post bag, now is the time to send them into Areca's firmware 1718 ***************************************************************** 1719 */ 1720 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1721 arcmsr_Write_data_2iop_wqbuffer(acb); 1722 } 1723 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1724 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1725 } 1726 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1727 } 1728 /* 1729 ************************************************************************** 1730 ************************************************************************** 1731 */ 1732 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1733 { 1734 /* 1735 if (ccb->ccb_h.status != CAM_REQ_CMP) 1736 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1737 "failure status=%x\n", ccb->ccb_h.target_id, 1738 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1739 else 1740 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1741 */ 1742 xpt_free_path(ccb->ccb_h.path); 1743 xpt_free_ccb(ccb); 1744 } 1745 1746 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1747 { 1748 struct cam_path *path; 1749 union ccb *ccb; 1750 1751 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1752 return; 1753 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1754 { 1755 xpt_free_ccb(ccb); 1756 return; 1757 } 1758 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1759 bzero(ccb, sizeof(union ccb)); 1760 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1761 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1762 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1763 ccb->crcn.flags = CAM_FLAG_NONE; 1764 xpt_action(ccb); 1765 } 1766 1767 1768 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1769 { 1770 struct CommandControlBlock *srb; 1771 u_int32_t intmask_org; 1772 int i; 1773 1774 /* disable all outbound interrupts */ 1775 intmask_org = arcmsr_disable_allintr(acb); 1776 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1777 { 1778 srb = acb->psrb_pool[i]; 1779 if (srb->srb_state == ARCMSR_SRB_START) 1780 { 1781 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1782 { 1783 srb->srb_state = ARCMSR_SRB_ABORTED; 1784 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1785 arcmsr_srb_complete(srb, 1); 1786 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1787 } 1788 } 1789 } 1790 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1791 arcmsr_enable_allintr(acb, intmask_org); 1792 } 1793 /* 1794 ************************************************************************** 1795 ************************************************************************** 1796 */ 1797 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1798 u_int32_t devicemap; 1799 u_int32_t target, lun; 1800 u_int32_t deviceMapCurrent[4]={0}; 1801 u_int8_t *pDevMap; 1802 1803 switch (acb->adapter_type) { 1804 case ACB_ADAPTER_TYPE_A: 1805 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1806 for (target = 0; target < 4; target++) 1807 { 1808 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1809 devicemap += 4; 1810 } 1811 break; 1812 1813 case ACB_ADAPTER_TYPE_B: 1814 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1815 for (target = 0; target < 4; target++) 1816 { 1817 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1818 devicemap += 4; 1819 } 1820 break; 1821 1822 case ACB_ADAPTER_TYPE_C: 1823 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1824 for (target = 0; target < 4; target++) 1825 { 1826 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1827 devicemap += 4; 1828 } 1829 break; 1830 case ACB_ADAPTER_TYPE_D: 1831 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1832 for (target = 0; target < 4; target++) 1833 { 1834 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1835 devicemap += 4; 1836 } 1837 break; 1838 case ACB_ADAPTER_TYPE_E: 1839 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1840 for (target = 0; target < 4; target++) 1841 { 1842 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1843 devicemap += 4; 1844 } 1845 break; 1846 } 1847 1848 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1849 { 1850 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1851 } 1852 /* 1853 ** adapter posted CONFIG message 1854 ** copy the new map, note if there are differences with the current map 1855 */ 1856 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1857 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1858 { 1859 if (*pDevMap != acb->device_map[target]) 1860 { 1861 u_int8_t difference, bit_check; 1862 1863 difference = *pDevMap ^ acb->device_map[target]; 1864 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1865 { 1866 bit_check = (1 << lun); /*check bit from 0....31*/ 1867 if(difference & bit_check) 1868 { 1869 if(acb->device_map[target] & bit_check) 1870 {/* unit departed */ 1871 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1872 arcmsr_abort_dr_ccbs(acb, target, lun); 1873 arcmsr_rescan_lun(acb, target, lun); 1874 acb->devstate[target][lun] = ARECA_RAID_GONE; 1875 } 1876 else 1877 {/* unit arrived */ 1878 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1879 arcmsr_rescan_lun(acb, target, lun); 1880 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1881 } 1882 } 1883 } 1884 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1885 acb->device_map[target] = *pDevMap; 1886 } 1887 pDevMap++; 1888 } 1889 } 1890 /* 1891 ************************************************************************** 1892 ************************************************************************** 1893 */ 1894 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1895 u_int32_t outbound_message; 1896 1897 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1898 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1899 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1900 arcmsr_dr_handle( acb ); 1901 } 1902 /* 1903 ************************************************************************** 1904 ************************************************************************** 1905 */ 1906 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1907 u_int32_t outbound_message; 1908 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1909 1910 /* clear interrupts */ 1911 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1912 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1913 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1914 arcmsr_dr_handle( acb ); 1915 } 1916 /* 1917 ************************************************************************** 1918 ************************************************************************** 1919 */ 1920 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1921 u_int32_t outbound_message; 1922 1923 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1924 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1925 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1926 arcmsr_dr_handle( acb ); 1927 } 1928 /* 1929 ************************************************************************** 1930 ************************************************************************** 1931 */ 1932 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1933 u_int32_t outbound_message; 1934 1935 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1936 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1937 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1938 arcmsr_dr_handle( acb ); 1939 } 1940 /* 1941 ************************************************************************** 1942 ************************************************************************** 1943 */ 1944 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1945 u_int32_t outbound_message; 1946 1947 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1948 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1949 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1950 arcmsr_dr_handle( acb ); 1951 } 1952 /* 1953 ************************************************************************** 1954 ************************************************************************** 1955 */ 1956 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1957 { 1958 u_int32_t doorbell_status; 1959 1960 /* 1961 ******************************************************************* 1962 ** Maybe here we need to check wrqbuffer_lock is lock or not 1963 ** DOORBELL: din! don! 1964 ** check if there are any mail need to pack from firmware 1965 ******************************************************************* 1966 */ 1967 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1968 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1969 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1970 arcmsr_iop2drv_data_wrote_handle(acb); 1971 } 1972 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1973 arcmsr_iop2drv_data_read_handle(acb); 1974 } 1975 } 1976 /* 1977 ************************************************************************** 1978 ************************************************************************** 1979 */ 1980 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1981 { 1982 u_int32_t doorbell_status; 1983 1984 /* 1985 ******************************************************************* 1986 ** Maybe here we need to check wrqbuffer_lock is lock or not 1987 ** DOORBELL: din! don! 1988 ** check if there are any mail need to pack from firmware 1989 ******************************************************************* 1990 */ 1991 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1992 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1993 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1994 arcmsr_iop2drv_data_wrote_handle(acb); 1995 } 1996 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1997 arcmsr_iop2drv_data_read_handle(acb); 1998 } 1999 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 2000 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 2001 } 2002 } 2003 /* 2004 ************************************************************************** 2005 ************************************************************************** 2006 */ 2007 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 2008 { 2009 u_int32_t doorbell_status; 2010 2011 /* 2012 ******************************************************************* 2013 ** Maybe here we need to check wrqbuffer_lock is lock or not 2014 ** DOORBELL: din! don! 2015 ** check if there are any mail need to pack from firmware 2016 ******************************************************************* 2017 */ 2018 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 2019 if(doorbell_status) 2020 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 2021 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 2022 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 2023 arcmsr_iop2drv_data_wrote_handle(acb); 2024 } 2025 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 2026 arcmsr_iop2drv_data_read_handle(acb); 2027 } 2028 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 2029 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 2030 } 2031 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 2032 if(doorbell_status) 2033 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 2034 } 2035 } 2036 /* 2037 ************************************************************************** 2038 ************************************************************************** 2039 */ 2040 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 2041 { 2042 u_int32_t doorbell_status, in_doorbell; 2043 2044 /* 2045 ******************************************************************* 2046 ** Maybe here we need to check wrqbuffer_lock is lock or not 2047 ** DOORBELL: din! don! 2048 ** check if there are any mail need to pack from firmware 2049 ******************************************************************* 2050 */ 2051 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2052 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2053 doorbell_status = in_doorbell ^ acb->in_doorbell; 2054 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2055 arcmsr_iop2drv_data_wrote_handle(acb); 2056 } 2057 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2058 arcmsr_iop2drv_data_read_handle(acb); 2059 } 2060 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2061 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2062 } 2063 acb->in_doorbell = in_doorbell; 2064 } 2065 /* 2066 ************************************************************************** 2067 ************************************************************************** 2068 */ 2069 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2070 { 2071 u_int32_t flag_srb; 2072 u_int16_t error; 2073 2074 /* 2075 ***************************************************************************** 2076 ** areca cdb command done 2077 ***************************************************************************** 2078 */ 2079 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2080 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2081 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2082 0, outbound_queueport)) != 0xFFFFFFFF) { 2083 /* check if command done with no error*/ 2084 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2085 arcmsr_drain_donequeue(acb, flag_srb, error); 2086 } /*drain reply FIFO*/ 2087 } 2088 /* 2089 ************************************************************************** 2090 ************************************************************************** 2091 */ 2092 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2093 { 2094 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2095 u_int32_t flag_srb; 2096 int index; 2097 u_int16_t error; 2098 2099 /* 2100 ***************************************************************************** 2101 ** areca cdb command done 2102 ***************************************************************************** 2103 */ 2104 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2105 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2106 index = phbbmu->doneq_index; 2107 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2108 phbbmu->done_qbuffer[index] = 0; 2109 index++; 2110 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2111 phbbmu->doneq_index = index; 2112 /* check if command done with no error*/ 2113 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2114 arcmsr_drain_donequeue(acb, flag_srb, error); 2115 } /*drain reply FIFO*/ 2116 } 2117 /* 2118 ************************************************************************** 2119 ************************************************************************** 2120 */ 2121 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2122 { 2123 u_int32_t flag_srb,throttling = 0; 2124 u_int16_t error; 2125 2126 /* 2127 ***************************************************************************** 2128 ** areca cdb command done 2129 ***************************************************************************** 2130 */ 2131 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2132 do { 2133 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2134 if (flag_srb == 0xFFFFFFFF) 2135 break; 2136 /* check if command done with no error*/ 2137 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2138 arcmsr_drain_donequeue(acb, flag_srb, error); 2139 throttling++; 2140 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2141 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2142 throttling = 0; 2143 } 2144 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2145 } 2146 /* 2147 ********************************************************************** 2148 ** 2149 ********************************************************************** 2150 */ 2151 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2152 { 2153 uint16_t doneq_index, index_stripped; 2154 2155 doneq_index = phbdmu->doneq_index; 2156 if (doneq_index & 0x4000) { 2157 index_stripped = doneq_index & 0xFF; 2158 index_stripped += 1; 2159 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2160 phbdmu->doneq_index = index_stripped ? 2161 (index_stripped | 0x4000) : index_stripped; 2162 } else { 2163 index_stripped = doneq_index; 2164 index_stripped += 1; 2165 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2166 phbdmu->doneq_index = index_stripped ? 2167 index_stripped : (index_stripped | 0x4000); 2168 } 2169 return (phbdmu->doneq_index); 2170 } 2171 /* 2172 ************************************************************************** 2173 ************************************************************************** 2174 */ 2175 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2176 { 2177 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2178 u_int32_t outbound_write_pointer; 2179 u_int32_t addressLow; 2180 uint16_t doneq_index; 2181 u_int16_t error; 2182 /* 2183 ***************************************************************************** 2184 ** areca cdb command done 2185 ***************************************************************************** 2186 */ 2187 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2188 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2189 return; 2190 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2191 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2192 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2193 doneq_index = phbdmu->doneq_index; 2194 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2195 doneq_index = arcmsr_get_doneq_index(phbdmu); 2196 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2197 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2198 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2199 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2200 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2201 } 2202 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2203 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2204 } 2205 /* 2206 ************************************************************************** 2207 ************************************************************************** 2208 */ 2209 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2210 { 2211 u_int16_t error; 2212 uint32_t doneq_index; 2213 uint16_t cmdSMID; 2214 2215 /* 2216 ***************************************************************************** 2217 ** areca cdb command done 2218 ***************************************************************************** 2219 */ 2220 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2221 doneq_index = acb->doneq_index; 2222 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2223 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2224 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2225 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2226 doneq_index++; 2227 if (doneq_index >= acb->completionQ_entry) 2228 doneq_index = 0; 2229 } 2230 acb->doneq_index = doneq_index; 2231 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2232 } 2233 /* 2234 ********************************************************************** 2235 ********************************************************************** 2236 */ 2237 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2238 { 2239 u_int32_t outbound_intStatus; 2240 /* 2241 ********************************************* 2242 ** check outbound intstatus 2243 ********************************************* 2244 */ 2245 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2246 if(!outbound_intStatus) { 2247 /*it must be share irq*/ 2248 return; 2249 } 2250 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2251 /* MU doorbell interrupts*/ 2252 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2253 arcmsr_hba_doorbell_isr(acb); 2254 } 2255 /* MU post queue interrupts*/ 2256 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2257 arcmsr_hba_postqueue_isr(acb); 2258 } 2259 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2260 arcmsr_hba_message_isr(acb); 2261 } 2262 } 2263 /* 2264 ********************************************************************** 2265 ********************************************************************** 2266 */ 2267 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2268 { 2269 u_int32_t outbound_doorbell; 2270 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2271 /* 2272 ********************************************* 2273 ** check outbound intstatus 2274 ********************************************* 2275 */ 2276 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2277 if(!outbound_doorbell) { 2278 /*it must be share irq*/ 2279 return; 2280 } 2281 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2282 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2283 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2284 /* MU ioctl transfer doorbell interrupts*/ 2285 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2286 arcmsr_iop2drv_data_wrote_handle(acb); 2287 } 2288 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2289 arcmsr_iop2drv_data_read_handle(acb); 2290 } 2291 /* MU post queue interrupts*/ 2292 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2293 arcmsr_hbb_postqueue_isr(acb); 2294 } 2295 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2296 arcmsr_hbb_message_isr(acb); 2297 } 2298 } 2299 /* 2300 ********************************************************************** 2301 ********************************************************************** 2302 */ 2303 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2304 { 2305 u_int32_t host_interrupt_status; 2306 /* 2307 ********************************************* 2308 ** check outbound intstatus 2309 ********************************************* 2310 */ 2311 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2312 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2313 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2314 if(!host_interrupt_status) { 2315 /*it must be share irq*/ 2316 return; 2317 } 2318 do { 2319 /* MU doorbell interrupts*/ 2320 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2321 arcmsr_hbc_doorbell_isr(acb); 2322 } 2323 /* MU post queue interrupts*/ 2324 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2325 arcmsr_hbc_postqueue_isr(acb); 2326 } 2327 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2328 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2329 } 2330 /* 2331 ********************************************************************** 2332 ********************************************************************** 2333 */ 2334 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2335 { 2336 u_int32_t host_interrupt_status; 2337 u_int32_t intmask_org; 2338 /* 2339 ********************************************* 2340 ** check outbound intstatus 2341 ********************************************* 2342 */ 2343 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2344 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2345 /*it must be share irq*/ 2346 return; 2347 } 2348 /* disable outbound interrupt */ 2349 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2350 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2351 /* MU doorbell interrupts*/ 2352 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2353 arcmsr_hbd_doorbell_isr(acb); 2354 } 2355 /* MU post queue interrupts*/ 2356 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2357 arcmsr_hbd_postqueue_isr(acb); 2358 } 2359 /* enable all outbound interrupt */ 2360 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2361 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2362 } 2363 /* 2364 ********************************************************************** 2365 ********************************************************************** 2366 */ 2367 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2368 { 2369 u_int32_t host_interrupt_status; 2370 /* 2371 ********************************************* 2372 ** check outbound intstatus 2373 ********************************************* 2374 */ 2375 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2376 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2377 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2378 if(!host_interrupt_status) { 2379 /*it must be share irq*/ 2380 return; 2381 } 2382 do { 2383 /* MU doorbell interrupts*/ 2384 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2385 arcmsr_hbe_doorbell_isr(acb); 2386 } 2387 /* MU post queue interrupts*/ 2388 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2389 arcmsr_hbe_postqueue_isr(acb); 2390 } 2391 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2392 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2393 } 2394 /* 2395 ****************************************************************************** 2396 ****************************************************************************** 2397 */ 2398 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2399 { 2400 switch (acb->adapter_type) { 2401 case ACB_ADAPTER_TYPE_A: 2402 arcmsr_handle_hba_isr(acb); 2403 break; 2404 case ACB_ADAPTER_TYPE_B: 2405 arcmsr_handle_hbb_isr(acb); 2406 break; 2407 case ACB_ADAPTER_TYPE_C: 2408 arcmsr_handle_hbc_isr(acb); 2409 break; 2410 case ACB_ADAPTER_TYPE_D: 2411 arcmsr_handle_hbd_isr(acb); 2412 break; 2413 case ACB_ADAPTER_TYPE_E: 2414 arcmsr_handle_hbe_isr(acb); 2415 break; 2416 default: 2417 printf("arcmsr%d: interrupt service," 2418 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2419 break; 2420 } 2421 } 2422 /* 2423 ********************************************************************** 2424 ********************************************************************** 2425 */ 2426 static void arcmsr_intr_handler(void *arg) 2427 { 2428 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2429 2430 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2431 arcmsr_interrupt(acb); 2432 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2433 } 2434 /* 2435 ****************************************************************************** 2436 ****************************************************************************** 2437 */ 2438 static void arcmsr_polling_devmap(void *arg) 2439 { 2440 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2441 switch (acb->adapter_type) { 2442 case ACB_ADAPTER_TYPE_A: 2443 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2444 break; 2445 2446 case ACB_ADAPTER_TYPE_B: { 2447 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2448 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2449 } 2450 break; 2451 2452 case ACB_ADAPTER_TYPE_C: 2453 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2454 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2455 break; 2456 2457 case ACB_ADAPTER_TYPE_D: 2458 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2459 break; 2460 2461 case ACB_ADAPTER_TYPE_E: 2462 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2463 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2464 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2465 break; 2466 } 2467 2468 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2469 { 2470 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2471 } 2472 } 2473 2474 /* 2475 ******************************************************************************* 2476 ** 2477 ******************************************************************************* 2478 */ 2479 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2480 { 2481 u_int32_t intmask_org; 2482 2483 if(acb != NULL) { 2484 /* stop adapter background rebuild */ 2485 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2486 intmask_org = arcmsr_disable_allintr(acb); 2487 arcmsr_stop_adapter_bgrb(acb); 2488 arcmsr_flush_adapter_cache(acb); 2489 arcmsr_enable_allintr(acb, intmask_org); 2490 } 2491 } 2492 } 2493 /* 2494 *********************************************************************** 2495 ** 2496 ************************************************************************ 2497 */ 2498 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2499 { 2500 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2501 u_int32_t retvalue = EINVAL; 2502 2503 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2504 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2505 return retvalue; 2506 } 2507 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2508 switch(ioctl_cmd) { 2509 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2510 u_int8_t *pQbuffer; 2511 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2512 u_int32_t allxfer_len=0; 2513 2514 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2515 && (allxfer_len < 1031)) { 2516 /*copy READ QBUFFER to srb*/ 2517 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2518 *ptmpQbuffer = *pQbuffer; 2519 acb->rqbuf_firstindex++; 2520 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2521 /*if last index number set it to 0 */ 2522 ptmpQbuffer++; 2523 allxfer_len++; 2524 } 2525 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2526 struct QBUFFER *prbuffer; 2527 2528 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2529 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2530 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2531 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2532 } 2533 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2534 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2535 retvalue = ARCMSR_MESSAGE_SUCCESS; 2536 } 2537 break; 2538 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2539 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2540 u_int8_t *pQbuffer; 2541 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2542 2543 user_len = pcmdmessagefld->cmdmessage.Length; 2544 /*check if data xfer length of this request will overflow my array qbuffer */ 2545 wqbuf_lastindex = acb->wqbuf_lastindex; 2546 wqbuf_firstindex = acb->wqbuf_firstindex; 2547 if(wqbuf_lastindex != wqbuf_firstindex) { 2548 arcmsr_Write_data_2iop_wqbuffer(acb); 2549 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2550 } else { 2551 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2552 (ARCMSR_MAX_QBUFFER - 1); 2553 if(my_empty_len >= user_len) { 2554 while(user_len > 0) { 2555 /*copy srb data to wqbuffer*/ 2556 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2557 *pQbuffer = *ptmpuserbuffer; 2558 acb->wqbuf_lastindex++; 2559 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2560 /*if last index number set it to 0 */ 2561 ptmpuserbuffer++; 2562 user_len--; 2563 } 2564 /*post fist Qbuffer*/ 2565 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2566 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2567 arcmsr_Write_data_2iop_wqbuffer(acb); 2568 } 2569 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2570 } else { 2571 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2572 } 2573 } 2574 retvalue = ARCMSR_MESSAGE_SUCCESS; 2575 } 2576 break; 2577 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2578 u_int8_t *pQbuffer = acb->rqbuffer; 2579 2580 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2581 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2582 arcmsr_iop_message_read(acb); 2583 /*signature, let IOP know data has been readed */ 2584 } 2585 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2586 acb->rqbuf_firstindex = 0; 2587 acb->rqbuf_lastindex = 0; 2588 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2589 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2590 retvalue = ARCMSR_MESSAGE_SUCCESS; 2591 } 2592 break; 2593 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2594 { 2595 u_int8_t *pQbuffer = acb->wqbuffer; 2596 2597 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2598 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2599 arcmsr_iop_message_read(acb); 2600 /*signature, let IOP know data has been readed */ 2601 } 2602 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2603 acb->wqbuf_firstindex = 0; 2604 acb->wqbuf_lastindex = 0; 2605 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2606 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2607 retvalue = ARCMSR_MESSAGE_SUCCESS; 2608 } 2609 break; 2610 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2611 u_int8_t *pQbuffer; 2612 2613 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2614 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2615 arcmsr_iop_message_read(acb); 2616 /*signature, let IOP know data has been readed */ 2617 } 2618 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2619 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2620 |ACB_F_MESSAGE_WQBUFFER_READ); 2621 acb->rqbuf_firstindex = 0; 2622 acb->rqbuf_lastindex = 0; 2623 acb->wqbuf_firstindex = 0; 2624 acb->wqbuf_lastindex = 0; 2625 pQbuffer = acb->rqbuffer; 2626 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2627 pQbuffer = acb->wqbuffer; 2628 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2629 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2630 retvalue = ARCMSR_MESSAGE_SUCCESS; 2631 } 2632 break; 2633 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2634 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2635 retvalue = ARCMSR_MESSAGE_SUCCESS; 2636 } 2637 break; 2638 case ARCMSR_MESSAGE_SAY_HELLO: { 2639 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2640 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2641 2642 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2643 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2644 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2645 return ENOIOCTL; 2646 } 2647 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2648 retvalue = ARCMSR_MESSAGE_SUCCESS; 2649 } 2650 break; 2651 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2652 arcmsr_iop_parking(acb); 2653 retvalue = ARCMSR_MESSAGE_SUCCESS; 2654 } 2655 break; 2656 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2657 arcmsr_flush_adapter_cache(acb); 2658 retvalue = ARCMSR_MESSAGE_SUCCESS; 2659 } 2660 break; 2661 } 2662 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2663 return (retvalue); 2664 } 2665 /* 2666 ************************************************************************** 2667 ************************************************************************** 2668 */ 2669 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2670 { 2671 struct AdapterControlBlock *acb; 2672 2673 acb = srb->acb; 2674 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2675 srb->srb_state = ARCMSR_SRB_DONE; 2676 srb->srb_flags = 0; 2677 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2678 acb->workingsrb_doneindex++; 2679 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2680 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2681 } 2682 /* 2683 ************************************************************************** 2684 ************************************************************************** 2685 */ 2686 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2687 { 2688 struct CommandControlBlock *srb = NULL; 2689 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2690 2691 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2692 workingsrb_doneindex = acb->workingsrb_doneindex; 2693 workingsrb_startindex = acb->workingsrb_startindex; 2694 srb = acb->srbworkingQ[workingsrb_startindex]; 2695 workingsrb_startindex++; 2696 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2697 if(workingsrb_doneindex != workingsrb_startindex) { 2698 acb->workingsrb_startindex = workingsrb_startindex; 2699 } else { 2700 srb = NULL; 2701 } 2702 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2703 return(srb); 2704 } 2705 /* 2706 ************************************************************************** 2707 ************************************************************************** 2708 */ 2709 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2710 { 2711 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2712 int retvalue = 0, transfer_len = 0; 2713 char *buffer; 2714 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2715 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2716 (u_int32_t ) ptr[6] << 16 | 2717 (u_int32_t ) ptr[7] << 8 | 2718 (u_int32_t ) ptr[8]; 2719 /* 4 bytes: Areca io control code */ 2720 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2721 buffer = pccb->csio.data_ptr; 2722 transfer_len = pccb->csio.dxfer_len; 2723 } else { 2724 retvalue = ARCMSR_MESSAGE_FAIL; 2725 goto message_out; 2726 } 2727 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2728 retvalue = ARCMSR_MESSAGE_FAIL; 2729 goto message_out; 2730 } 2731 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2732 switch(controlcode) { 2733 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2734 u_int8_t *pQbuffer; 2735 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2736 int32_t allxfer_len = 0; 2737 2738 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2739 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2740 && (allxfer_len < 1031)) { 2741 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2742 *ptmpQbuffer = *pQbuffer; 2743 acb->rqbuf_firstindex++; 2744 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2745 ptmpQbuffer++; 2746 allxfer_len++; 2747 } 2748 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2749 struct QBUFFER *prbuffer; 2750 2751 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2752 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2753 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2754 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2755 } 2756 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2757 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2758 retvalue = ARCMSR_MESSAGE_SUCCESS; 2759 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2760 } 2761 break; 2762 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2763 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2764 u_int8_t *pQbuffer; 2765 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2766 2767 user_len = pcmdmessagefld->cmdmessage.Length; 2768 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2769 wqbuf_lastindex = acb->wqbuf_lastindex; 2770 wqbuf_firstindex = acb->wqbuf_firstindex; 2771 if (wqbuf_lastindex != wqbuf_firstindex) { 2772 arcmsr_Write_data_2iop_wqbuffer(acb); 2773 /* has error report sensedata */ 2774 if(pccb->csio.sense_len) { 2775 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2776 /* Valid,ErrorCode */ 2777 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2778 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2779 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2780 /* AdditionalSenseLength */ 2781 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2782 /* AdditionalSenseCode */ 2783 } 2784 retvalue = ARCMSR_MESSAGE_FAIL; 2785 } else { 2786 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2787 &(ARCMSR_MAX_QBUFFER - 1); 2788 if (my_empty_len >= user_len) { 2789 while (user_len > 0) { 2790 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2791 *pQbuffer = *ptmpuserbuffer; 2792 acb->wqbuf_lastindex++; 2793 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2794 ptmpuserbuffer++; 2795 user_len--; 2796 } 2797 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2798 acb->acb_flags &= 2799 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2800 arcmsr_Write_data_2iop_wqbuffer(acb); 2801 } 2802 } else { 2803 /* has error report sensedata */ 2804 if(pccb->csio.sense_len) { 2805 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2806 /* Valid,ErrorCode */ 2807 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2808 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2809 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2810 /* AdditionalSenseLength */ 2811 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2812 /* AdditionalSenseCode */ 2813 } 2814 retvalue = ARCMSR_MESSAGE_FAIL; 2815 } 2816 } 2817 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2818 } 2819 break; 2820 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2821 u_int8_t *pQbuffer = acb->rqbuffer; 2822 2823 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2824 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2825 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2826 arcmsr_iop_message_read(acb); 2827 } 2828 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2829 acb->rqbuf_firstindex = 0; 2830 acb->rqbuf_lastindex = 0; 2831 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2832 pcmdmessagefld->cmdmessage.ReturnCode = 2833 ARCMSR_MESSAGE_RETURNCODE_OK; 2834 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2835 } 2836 break; 2837 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2838 u_int8_t *pQbuffer = acb->wqbuffer; 2839 2840 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2841 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2842 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2843 arcmsr_iop_message_read(acb); 2844 } 2845 acb->acb_flags |= 2846 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2847 ACB_F_MESSAGE_WQBUFFER_READ); 2848 acb->wqbuf_firstindex = 0; 2849 acb->wqbuf_lastindex = 0; 2850 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2851 pcmdmessagefld->cmdmessage.ReturnCode = 2852 ARCMSR_MESSAGE_RETURNCODE_OK; 2853 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2854 } 2855 break; 2856 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2857 u_int8_t *pQbuffer; 2858 2859 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2860 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2861 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2862 arcmsr_iop_message_read(acb); 2863 } 2864 acb->acb_flags |= 2865 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2866 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2867 | ACB_F_MESSAGE_WQBUFFER_READ); 2868 acb->rqbuf_firstindex = 0; 2869 acb->rqbuf_lastindex = 0; 2870 acb->wqbuf_firstindex = 0; 2871 acb->wqbuf_lastindex = 0; 2872 pQbuffer = acb->rqbuffer; 2873 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2874 pQbuffer = acb->wqbuffer; 2875 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2876 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2877 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2878 } 2879 break; 2880 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2881 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2882 } 2883 break; 2884 case ARCMSR_MESSAGE_SAY_HELLO: { 2885 int8_t *hello_string = "Hello! I am ARCMSR"; 2886 2887 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2888 , (int16_t)strlen(hello_string)); 2889 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2890 } 2891 break; 2892 case ARCMSR_MESSAGE_SAY_GOODBYE: 2893 arcmsr_iop_parking(acb); 2894 break; 2895 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2896 arcmsr_flush_adapter_cache(acb); 2897 break; 2898 default: 2899 retvalue = ARCMSR_MESSAGE_FAIL; 2900 } 2901 message_out: 2902 return (retvalue); 2903 } 2904 /* 2905 ********************************************************************* 2906 ********************************************************************* 2907 */ 2908 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2909 { 2910 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2911 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2912 union ccb *pccb; 2913 int target, lun; 2914 2915 pccb = srb->pccb; 2916 target = pccb->ccb_h.target_id; 2917 lun = pccb->ccb_h.target_lun; 2918 acb->pktRequestCount++; 2919 if(error != 0) { 2920 if(error != EFBIG) { 2921 printf("arcmsr%d: unexpected error %x" 2922 " returned from 'bus_dmamap_load' \n" 2923 , acb->pci_unit, error); 2924 } 2925 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2926 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2927 } 2928 arcmsr_srb_complete(srb, 0); 2929 return; 2930 } 2931 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2932 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2933 arcmsr_srb_complete(srb, 0); 2934 return; 2935 } 2936 if(acb->acb_flags & ACB_F_BUS_RESET) { 2937 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2938 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2939 arcmsr_srb_complete(srb, 0); 2940 return; 2941 } 2942 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2943 u_int8_t block_cmd, cmd; 2944 2945 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2946 block_cmd = cmd & 0x0f; 2947 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2948 printf("arcmsr%d:block 'read/write' command " 2949 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2950 , acb->pci_unit, cmd, target, lun); 2951 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2952 arcmsr_srb_complete(srb, 0); 2953 return; 2954 } 2955 } 2956 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2957 if(nseg != 0) { 2958 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2959 } 2960 arcmsr_srb_complete(srb, 0); 2961 return; 2962 } 2963 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2964 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2965 { 2966 xpt_freeze_simq(acb->psim, 1); 2967 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2968 } 2969 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2970 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2971 arcmsr_srb_complete(srb, 0); 2972 return; 2973 } 2974 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2975 arcmsr_build_srb(srb, dm_segs, nseg); 2976 arcmsr_post_srb(acb, srb); 2977 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2978 { 2979 arcmsr_callout_init(&srb->ccb_callout); 2980 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 2981 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 2982 arcmsr_srb_timeout, srb, 0); 2983 srb->srb_flags |= SRB_FLAG_TIMER_START; 2984 } 2985 } 2986 /* 2987 ***************************************************************************************** 2988 ***************************************************************************************** 2989 */ 2990 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2991 { 2992 struct CommandControlBlock *srb; 2993 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2994 u_int32_t intmask_org; 2995 int i = 0; 2996 2997 acb->num_aborts++; 2998 /* 2999 *************************************************************************** 3000 ** It is the upper layer do abort command this lock just prior to calling us. 3001 ** First determine if we currently own this command. 3002 ** Start by searching the device queue. If not found 3003 ** at all, and the system wanted us to just abort the 3004 ** command return success. 3005 *************************************************************************** 3006 */ 3007 if(acb->srboutstandingcount != 0) { 3008 /* disable all outbound interrupt */ 3009 intmask_org = arcmsr_disable_allintr(acb); 3010 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3011 srb = acb->psrb_pool[i]; 3012 if(srb->srb_state == ARCMSR_SRB_START) { 3013 if(srb->pccb == abortccb) { 3014 srb->srb_state = ARCMSR_SRB_ABORTED; 3015 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3016 "outstanding command \n" 3017 , acb->pci_unit, abortccb->ccb_h.target_id 3018 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3019 arcmsr_polling_srbdone(acb, srb); 3020 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3021 arcmsr_enable_allintr(acb, intmask_org); 3022 return (TRUE); 3023 } 3024 } 3025 } 3026 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3027 arcmsr_enable_allintr(acb, intmask_org); 3028 } 3029 return(FALSE); 3030 } 3031 /* 3032 **************************************************************************** 3033 **************************************************************************** 3034 */ 3035 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3036 { 3037 int retry = 0; 3038 3039 acb->num_resets++; 3040 acb->acb_flags |= ACB_F_BUS_RESET; 3041 while(acb->srboutstandingcount != 0 && retry < 400) { 3042 arcmsr_interrupt(acb); 3043 UDELAY(25000); 3044 retry++; 3045 } 3046 arcmsr_iop_reset(acb); 3047 acb->acb_flags &= ~ACB_F_BUS_RESET; 3048 } 3049 /* 3050 ************************************************************************** 3051 ************************************************************************** 3052 */ 3053 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3054 union ccb *pccb) 3055 { 3056 if (pccb->ccb_h.target_lun) { 3057 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3058 xpt_done(pccb); 3059 return; 3060 } 3061 pccb->ccb_h.status |= CAM_REQ_CMP; 3062 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3063 case INQUIRY: { 3064 unsigned char inqdata[36]; 3065 char *buffer = pccb->csio.data_ptr; 3066 3067 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3068 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3069 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3070 inqdata[3] = 0; 3071 inqdata[4] = 31; /* length of additional data */ 3072 inqdata[5] = 0; 3073 inqdata[6] = 0; 3074 inqdata[7] = 0; 3075 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3076 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3077 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3078 memcpy(buffer, inqdata, sizeof(inqdata)); 3079 xpt_done(pccb); 3080 } 3081 break; 3082 case WRITE_BUFFER: 3083 case READ_BUFFER: { 3084 if (arcmsr_iop_message_xfer(acb, pccb)) { 3085 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3086 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3087 } 3088 xpt_done(pccb); 3089 } 3090 break; 3091 default: 3092 xpt_done(pccb); 3093 } 3094 } 3095 /* 3096 ********************************************************************* 3097 ********************************************************************* 3098 */ 3099 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3100 { 3101 struct AdapterControlBlock *acb; 3102 3103 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3104 if(acb == NULL) { 3105 pccb->ccb_h.status |= CAM_REQ_INVALID; 3106 xpt_done(pccb); 3107 return; 3108 } 3109 switch (pccb->ccb_h.func_code) { 3110 case XPT_SCSI_IO: { 3111 struct CommandControlBlock *srb; 3112 int target = pccb->ccb_h.target_id; 3113 int error; 3114 3115 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3116 pccb->ccb_h.status = CAM_REQ_INVALID; 3117 xpt_done(pccb); 3118 return; 3119 } 3120 3121 if(target == 16) { 3122 /* virtual device for iop message transfer */ 3123 arcmsr_handle_virtual_command(acb, pccb); 3124 return; 3125 } 3126 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3127 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3128 xpt_done(pccb); 3129 return; 3130 } 3131 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3132 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3133 srb->pccb = pccb; 3134 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3135 , srb->dm_segs_dmamap 3136 , pccb 3137 , arcmsr_execute_srb, srb, /*flags*/0); 3138 if(error == EINPROGRESS) { 3139 xpt_freeze_simq(acb->psim, 1); 3140 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3141 } 3142 break; 3143 } 3144 case XPT_PATH_INQ: { 3145 struct ccb_pathinq *cpi = &pccb->cpi; 3146 3147 cpi->version_num = 1; 3148 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3149 cpi->target_sprt = 0; 3150 cpi->hba_misc = 0; 3151 cpi->hba_eng_cnt = 0; 3152 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3153 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3154 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3155 cpi->bus_id = cam_sim_bus(psim); 3156 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3157 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3158 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3159 cpi->unit_number = cam_sim_unit(psim); 3160 #ifdef CAM_NEW_TRAN_CODE 3161 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3162 cpi->base_transfer_speed = 1200000; 3163 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3164 cpi->base_transfer_speed = 600000; 3165 else 3166 cpi->base_transfer_speed = 300000; 3167 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3168 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3169 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3170 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3171 { 3172 cpi->transport = XPORT_SAS; 3173 cpi->transport_version = 0; 3174 cpi->protocol_version = SCSI_REV_SPC2; 3175 } 3176 else 3177 { 3178 cpi->transport = XPORT_SPI; 3179 cpi->transport_version = 2; 3180 cpi->protocol_version = SCSI_REV_2; 3181 } 3182 cpi->protocol = PROTO_SCSI; 3183 #endif 3184 cpi->ccb_h.status |= CAM_REQ_CMP; 3185 xpt_done(pccb); 3186 break; 3187 } 3188 case XPT_ABORT: { 3189 union ccb *pabort_ccb; 3190 3191 pabort_ccb = pccb->cab.abort_ccb; 3192 switch (pabort_ccb->ccb_h.func_code) { 3193 case XPT_ACCEPT_TARGET_IO: 3194 case XPT_CONT_TARGET_IO: 3195 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3196 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3197 xpt_done(pabort_ccb); 3198 pccb->ccb_h.status |= CAM_REQ_CMP; 3199 } else { 3200 xpt_print_path(pabort_ccb->ccb_h.path); 3201 printf("Not found\n"); 3202 pccb->ccb_h.status |= CAM_PATH_INVALID; 3203 } 3204 break; 3205 case XPT_SCSI_IO: 3206 pccb->ccb_h.status |= CAM_UA_ABORT; 3207 break; 3208 default: 3209 pccb->ccb_h.status |= CAM_REQ_INVALID; 3210 break; 3211 } 3212 xpt_done(pccb); 3213 break; 3214 } 3215 case XPT_RESET_BUS: 3216 case XPT_RESET_DEV: { 3217 u_int32_t i; 3218 3219 arcmsr_bus_reset(acb); 3220 for (i=0; i < 500; i++) { 3221 DELAY(1000); 3222 } 3223 pccb->ccb_h.status |= CAM_REQ_CMP; 3224 xpt_done(pccb); 3225 break; 3226 } 3227 case XPT_TERM_IO: { 3228 pccb->ccb_h.status |= CAM_REQ_INVALID; 3229 xpt_done(pccb); 3230 break; 3231 } 3232 case XPT_GET_TRAN_SETTINGS: { 3233 struct ccb_trans_settings *cts; 3234 3235 if(pccb->ccb_h.target_id == 16) { 3236 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3237 xpt_done(pccb); 3238 break; 3239 } 3240 cts = &pccb->cts; 3241 #ifdef CAM_NEW_TRAN_CODE 3242 { 3243 struct ccb_trans_settings_scsi *scsi; 3244 struct ccb_trans_settings_spi *spi; 3245 struct ccb_trans_settings_sas *sas; 3246 3247 scsi = &cts->proto_specific.scsi; 3248 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3249 scsi->valid = CTS_SCSI_VALID_TQ; 3250 cts->protocol = PROTO_SCSI; 3251 3252 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3253 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3254 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3255 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3256 { 3257 cts->protocol_version = SCSI_REV_SPC2; 3258 cts->transport_version = 0; 3259 cts->transport = XPORT_SAS; 3260 sas = &cts->xport_specific.sas; 3261 sas->valid = CTS_SAS_VALID_SPEED; 3262 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3263 sas->bitrate = 1200000; 3264 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3265 sas->bitrate = 600000; 3266 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3267 sas->bitrate = 300000; 3268 } 3269 else 3270 { 3271 cts->protocol_version = SCSI_REV_2; 3272 cts->transport_version = 2; 3273 cts->transport = XPORT_SPI; 3274 spi = &cts->xport_specific.spi; 3275 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3276 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3277 spi->sync_period = 1; 3278 else 3279 spi->sync_period = 2; 3280 spi->sync_offset = 32; 3281 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3282 spi->valid = CTS_SPI_VALID_DISC 3283 | CTS_SPI_VALID_SYNC_RATE 3284 | CTS_SPI_VALID_SYNC_OFFSET 3285 | CTS_SPI_VALID_BUS_WIDTH; 3286 } 3287 } 3288 #else 3289 { 3290 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 3291 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3292 cts->sync_period = 1; 3293 else 3294 cts->sync_period = 2; 3295 cts->sync_offset = 32; 3296 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3297 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 3298 CCB_TRANS_SYNC_OFFSET_VALID | 3299 CCB_TRANS_BUS_WIDTH_VALID | 3300 CCB_TRANS_DISC_VALID | 3301 CCB_TRANS_TQ_VALID; 3302 } 3303 #endif 3304 pccb->ccb_h.status |= CAM_REQ_CMP; 3305 xpt_done(pccb); 3306 break; 3307 } 3308 case XPT_SET_TRAN_SETTINGS: { 3309 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3310 xpt_done(pccb); 3311 break; 3312 } 3313 case XPT_CALC_GEOMETRY: 3314 if(pccb->ccb_h.target_id == 16) { 3315 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3316 xpt_done(pccb); 3317 break; 3318 } 3319 #if __FreeBSD_version >= 500000 3320 cam_calc_geometry(&pccb->ccg, 1); 3321 #else 3322 { 3323 struct ccb_calc_geometry *ccg; 3324 u_int32_t size_mb; 3325 u_int32_t secs_per_cylinder; 3326 3327 ccg = &pccb->ccg; 3328 if (ccg->block_size == 0) { 3329 pccb->ccb_h.status = CAM_REQ_INVALID; 3330 xpt_done(pccb); 3331 break; 3332 } 3333 if(((1024L * 1024L)/ccg->block_size) < 0) { 3334 pccb->ccb_h.status = CAM_REQ_INVALID; 3335 xpt_done(pccb); 3336 break; 3337 } 3338 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 3339 if(size_mb > 1024 ) { 3340 ccg->heads = 255; 3341 ccg->secs_per_track = 63; 3342 } else { 3343 ccg->heads = 64; 3344 ccg->secs_per_track = 32; 3345 } 3346 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3347 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3348 pccb->ccb_h.status |= CAM_REQ_CMP; 3349 } 3350 #endif 3351 xpt_done(pccb); 3352 break; 3353 default: 3354 pccb->ccb_h.status |= CAM_REQ_INVALID; 3355 xpt_done(pccb); 3356 break; 3357 } 3358 } 3359 /* 3360 ********************************************************************** 3361 ********************************************************************** 3362 */ 3363 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3364 { 3365 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3366 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3367 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3368 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3369 } 3370 } 3371 /* 3372 ********************************************************************** 3373 ********************************************************************** 3374 */ 3375 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3376 { 3377 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3378 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3379 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3380 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3381 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3382 } 3383 } 3384 /* 3385 ********************************************************************** 3386 ********************************************************************** 3387 */ 3388 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3389 { 3390 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3391 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3392 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3393 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3394 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3395 } 3396 } 3397 /* 3398 ********************************************************************** 3399 ********************************************************************** 3400 */ 3401 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3402 { 3403 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3404 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3405 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3406 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3407 } 3408 } 3409 /* 3410 ********************************************************************** 3411 ********************************************************************** 3412 */ 3413 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3414 { 3415 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3416 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3417 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3418 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3419 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3420 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3421 } 3422 } 3423 /* 3424 ********************************************************************** 3425 ********************************************************************** 3426 */ 3427 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3428 { 3429 switch (acb->adapter_type) { 3430 case ACB_ADAPTER_TYPE_A: 3431 arcmsr_start_hba_bgrb(acb); 3432 break; 3433 case ACB_ADAPTER_TYPE_B: 3434 arcmsr_start_hbb_bgrb(acb); 3435 break; 3436 case ACB_ADAPTER_TYPE_C: 3437 arcmsr_start_hbc_bgrb(acb); 3438 break; 3439 case ACB_ADAPTER_TYPE_D: 3440 arcmsr_start_hbd_bgrb(acb); 3441 break; 3442 case ACB_ADAPTER_TYPE_E: 3443 arcmsr_start_hbe_bgrb(acb); 3444 break; 3445 } 3446 } 3447 /* 3448 ********************************************************************** 3449 ** 3450 ********************************************************************** 3451 */ 3452 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3453 { 3454 struct CommandControlBlock *srb; 3455 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3456 u_int16_t error; 3457 3458 polling_ccb_retry: 3459 poll_count++; 3460 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3461 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3462 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3463 while(1) { 3464 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3465 0, outbound_queueport)) == 0xFFFFFFFF) { 3466 if(poll_srb_done) { 3467 break;/*chip FIFO no ccb for completion already*/ 3468 } else { 3469 UDELAY(25000); 3470 if ((poll_count > 100) && (poll_srb != NULL)) { 3471 break; 3472 } 3473 goto polling_ccb_retry; 3474 } 3475 } 3476 /* check if command done with no error*/ 3477 srb = (struct CommandControlBlock *) 3478 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3479 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3480 poll_srb_done = (srb == poll_srb) ? 1:0; 3481 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3482 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3483 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3484 "poll command abort successfully \n" 3485 , acb->pci_unit 3486 , srb->pccb->ccb_h.target_id 3487 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3488 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3489 arcmsr_srb_complete(srb, 1); 3490 continue; 3491 } 3492 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3493 "srboutstandingcount=%d \n" 3494 , acb->pci_unit 3495 , srb, acb->srboutstandingcount); 3496 continue; 3497 } 3498 arcmsr_report_srb_state(acb, srb, error); 3499 } /*drain reply FIFO*/ 3500 } 3501 /* 3502 ********************************************************************** 3503 ** 3504 ********************************************************************** 3505 */ 3506 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3507 { 3508 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3509 struct CommandControlBlock *srb; 3510 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3511 int index; 3512 u_int16_t error; 3513 3514 polling_ccb_retry: 3515 poll_count++; 3516 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3517 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3518 while(1) { 3519 index = phbbmu->doneq_index; 3520 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3521 if(poll_srb_done) { 3522 break;/*chip FIFO no ccb for completion already*/ 3523 } else { 3524 UDELAY(25000); 3525 if ((poll_count > 100) && (poll_srb != NULL)) { 3526 break; 3527 } 3528 goto polling_ccb_retry; 3529 } 3530 } 3531 phbbmu->done_qbuffer[index] = 0; 3532 index++; 3533 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3534 phbbmu->doneq_index = index; 3535 /* check if command done with no error*/ 3536 srb = (struct CommandControlBlock *) 3537 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3538 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3539 poll_srb_done = (srb == poll_srb) ? 1:0; 3540 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3541 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3542 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3543 "poll command abort successfully \n" 3544 , acb->pci_unit 3545 , srb->pccb->ccb_h.target_id 3546 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3547 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3548 arcmsr_srb_complete(srb, 1); 3549 continue; 3550 } 3551 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3552 "srboutstandingcount=%d \n" 3553 , acb->pci_unit 3554 , srb, acb->srboutstandingcount); 3555 continue; 3556 } 3557 arcmsr_report_srb_state(acb, srb, error); 3558 } /*drain reply FIFO*/ 3559 } 3560 /* 3561 ********************************************************************** 3562 ** 3563 ********************************************************************** 3564 */ 3565 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3566 { 3567 struct CommandControlBlock *srb; 3568 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3569 u_int16_t error; 3570 3571 polling_ccb_retry: 3572 poll_count++; 3573 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3574 while(1) { 3575 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3576 if(poll_srb_done) { 3577 break;/*chip FIFO no ccb for completion already*/ 3578 } else { 3579 UDELAY(25000); 3580 if ((poll_count > 100) && (poll_srb != NULL)) { 3581 break; 3582 } 3583 if (acb->srboutstandingcount == 0) { 3584 break; 3585 } 3586 goto polling_ccb_retry; 3587 } 3588 } 3589 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3590 /* check if command done with no error*/ 3591 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3592 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3593 if (poll_srb != NULL) 3594 poll_srb_done = (srb == poll_srb) ? 1:0; 3595 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3596 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3597 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3598 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3599 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3600 arcmsr_srb_complete(srb, 1); 3601 continue; 3602 } 3603 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3604 , acb->pci_unit, srb, acb->srboutstandingcount); 3605 continue; 3606 } 3607 arcmsr_report_srb_state(acb, srb, error); 3608 } /*drain reply FIFO*/ 3609 } 3610 /* 3611 ********************************************************************** 3612 ** 3613 ********************************************************************** 3614 */ 3615 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3616 { 3617 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3618 struct CommandControlBlock *srb; 3619 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3620 u_int32_t outbound_write_pointer; 3621 u_int16_t error, doneq_index; 3622 3623 polling_ccb_retry: 3624 poll_count++; 3625 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3626 while(1) { 3627 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3628 doneq_index = phbdmu->doneq_index; 3629 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3630 if(poll_srb_done) { 3631 break;/*chip FIFO no ccb for completion already*/ 3632 } else { 3633 UDELAY(25000); 3634 if ((poll_count > 100) && (poll_srb != NULL)) { 3635 break; 3636 } 3637 if (acb->srboutstandingcount == 0) { 3638 break; 3639 } 3640 goto polling_ccb_retry; 3641 } 3642 } 3643 doneq_index = arcmsr_get_doneq_index(phbdmu); 3644 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3645 /* check if command done with no error*/ 3646 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3647 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3648 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3649 if (poll_srb != NULL) 3650 poll_srb_done = (srb == poll_srb) ? 1:0; 3651 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3652 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3653 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3654 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3655 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3656 arcmsr_srb_complete(srb, 1); 3657 continue; 3658 } 3659 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3660 , acb->pci_unit, srb, acb->srboutstandingcount); 3661 continue; 3662 } 3663 arcmsr_report_srb_state(acb, srb, error); 3664 } /*drain reply FIFO*/ 3665 } 3666 /* 3667 ********************************************************************** 3668 ** 3669 ********************************************************************** 3670 */ 3671 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3672 { 3673 struct CommandControlBlock *srb; 3674 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3675 u_int16_t error, cmdSMID; 3676 3677 polling_ccb_retry: 3678 poll_count++; 3679 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3680 while(1) { 3681 doneq_index = acb->doneq_index; 3682 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3683 if(poll_srb_done) { 3684 break;/*chip FIFO no ccb for completion already*/ 3685 } else { 3686 UDELAY(25000); 3687 if ((poll_count > 100) && (poll_srb != NULL)) { 3688 break; 3689 } 3690 if (acb->srboutstandingcount == 0) { 3691 break; 3692 } 3693 goto polling_ccb_retry; 3694 } 3695 } 3696 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3697 doneq_index++; 3698 if (doneq_index >= acb->completionQ_entry) 3699 doneq_index = 0; 3700 acb->doneq_index = doneq_index; 3701 srb = acb->psrb_pool[cmdSMID]; 3702 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3703 if (poll_srb != NULL) 3704 poll_srb_done = (srb == poll_srb) ? 1:0; 3705 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3706 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3707 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3708 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3709 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3710 arcmsr_srb_complete(srb, 1); 3711 continue; 3712 } 3713 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3714 , acb->pci_unit, srb, acb->srboutstandingcount); 3715 continue; 3716 } 3717 arcmsr_report_srb_state(acb, srb, error); 3718 } /*drain reply FIFO*/ 3719 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3720 } 3721 /* 3722 ********************************************************************** 3723 ********************************************************************** 3724 */ 3725 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3726 { 3727 switch (acb->adapter_type) { 3728 case ACB_ADAPTER_TYPE_A: { 3729 arcmsr_polling_hba_srbdone(acb, poll_srb); 3730 } 3731 break; 3732 case ACB_ADAPTER_TYPE_B: { 3733 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3734 } 3735 break; 3736 case ACB_ADAPTER_TYPE_C: { 3737 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3738 } 3739 break; 3740 case ACB_ADAPTER_TYPE_D: { 3741 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3742 } 3743 break; 3744 case ACB_ADAPTER_TYPE_E: { 3745 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3746 } 3747 break; 3748 } 3749 } 3750 /* 3751 ********************************************************************** 3752 ********************************************************************** 3753 */ 3754 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3755 { 3756 char *acb_firm_model = acb->firm_model; 3757 char *acb_firm_version = acb->firm_version; 3758 char *acb_device_map = acb->device_map; 3759 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3760 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3761 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3762 int i; 3763 3764 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3765 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3766 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3767 } 3768 i = 0; 3769 while(i < 8) { 3770 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3771 /* 8 bytes firm_model, 15, 60-67*/ 3772 acb_firm_model++; 3773 i++; 3774 } 3775 i=0; 3776 while(i < 16) { 3777 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3778 /* 16 bytes firm_version, 17, 68-83*/ 3779 acb_firm_version++; 3780 i++; 3781 } 3782 i=0; 3783 while(i < 16) { 3784 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3785 acb_device_map++; 3786 i++; 3787 } 3788 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3789 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3790 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3791 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3792 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3793 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3794 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3795 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3796 else 3797 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3798 } 3799 /* 3800 ********************************************************************** 3801 ********************************************************************** 3802 */ 3803 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3804 { 3805 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3806 char *acb_firm_model = acb->firm_model; 3807 char *acb_firm_version = acb->firm_version; 3808 char *acb_device_map = acb->device_map; 3809 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3810 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3811 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3812 int i; 3813 3814 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3815 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3816 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3817 } 3818 i = 0; 3819 while(i < 8) { 3820 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3821 /* 8 bytes firm_model, 15, 60-67*/ 3822 acb_firm_model++; 3823 i++; 3824 } 3825 i = 0; 3826 while(i < 16) { 3827 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3828 /* 16 bytes firm_version, 17, 68-83*/ 3829 acb_firm_version++; 3830 i++; 3831 } 3832 i = 0; 3833 while(i < 16) { 3834 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3835 acb_device_map++; 3836 i++; 3837 } 3838 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3839 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3840 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3841 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3842 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3843 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3844 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3845 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3846 else 3847 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3848 } 3849 /* 3850 ********************************************************************** 3851 ********************************************************************** 3852 */ 3853 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3854 { 3855 char *acb_firm_model = acb->firm_model; 3856 char *acb_firm_version = acb->firm_version; 3857 char *acb_device_map = acb->device_map; 3858 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3859 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3860 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3861 int i; 3862 3863 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3864 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3865 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3866 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3867 } 3868 i = 0; 3869 while(i < 8) { 3870 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3871 /* 8 bytes firm_model, 15, 60-67*/ 3872 acb_firm_model++; 3873 i++; 3874 } 3875 i = 0; 3876 while(i < 16) { 3877 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3878 /* 16 bytes firm_version, 17, 68-83*/ 3879 acb_firm_version++; 3880 i++; 3881 } 3882 i = 0; 3883 while(i < 16) { 3884 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3885 acb_device_map++; 3886 i++; 3887 } 3888 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3889 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3890 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3891 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3892 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3893 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3894 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3895 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3896 else 3897 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3898 } 3899 /* 3900 ********************************************************************** 3901 ********************************************************************** 3902 */ 3903 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3904 { 3905 char *acb_firm_model = acb->firm_model; 3906 char *acb_firm_version = acb->firm_version; 3907 char *acb_device_map = acb->device_map; 3908 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3909 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3910 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3911 int i; 3912 3913 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3914 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3915 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3916 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3917 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3918 } 3919 i = 0; 3920 while(i < 8) { 3921 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3922 /* 8 bytes firm_model, 15, 60-67*/ 3923 acb_firm_model++; 3924 i++; 3925 } 3926 i = 0; 3927 while(i < 16) { 3928 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3929 /* 16 bytes firm_version, 17, 68-83*/ 3930 acb_firm_version++; 3931 i++; 3932 } 3933 i = 0; 3934 while(i < 16) { 3935 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3936 acb_device_map++; 3937 i++; 3938 } 3939 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3940 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3941 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3942 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3943 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3944 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3945 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3946 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3947 else 3948 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3949 } 3950 /* 3951 ********************************************************************** 3952 ********************************************************************** 3953 */ 3954 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3955 { 3956 char *acb_firm_model = acb->firm_model; 3957 char *acb_firm_version = acb->firm_version; 3958 char *acb_device_map = acb->device_map; 3959 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3960 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3961 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3962 int i; 3963 3964 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3965 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3966 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3967 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3968 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3969 } 3970 3971 i = 0; 3972 while(i < 8) { 3973 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3974 /* 8 bytes firm_model, 15, 60-67*/ 3975 acb_firm_model++; 3976 i++; 3977 } 3978 i = 0; 3979 while(i < 16) { 3980 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3981 /* 16 bytes firm_version, 17, 68-83*/ 3982 acb_firm_version++; 3983 i++; 3984 } 3985 i = 0; 3986 while(i < 16) { 3987 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3988 acb_device_map++; 3989 i++; 3990 } 3991 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3992 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3993 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3994 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3995 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3996 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3997 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3998 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3999 else 4000 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4001 } 4002 /* 4003 ********************************************************************** 4004 ********************************************************************** 4005 */ 4006 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4007 { 4008 switch (acb->adapter_type) { 4009 case ACB_ADAPTER_TYPE_A: { 4010 arcmsr_get_hba_config(acb); 4011 } 4012 break; 4013 case ACB_ADAPTER_TYPE_B: { 4014 arcmsr_get_hbb_config(acb); 4015 } 4016 break; 4017 case ACB_ADAPTER_TYPE_C: { 4018 arcmsr_get_hbc_config(acb); 4019 } 4020 break; 4021 case ACB_ADAPTER_TYPE_D: { 4022 arcmsr_get_hbd_config(acb); 4023 } 4024 break; 4025 case ACB_ADAPTER_TYPE_E: { 4026 arcmsr_get_hbe_config(acb); 4027 } 4028 break; 4029 } 4030 } 4031 /* 4032 ********************************************************************** 4033 ********************************************************************** 4034 */ 4035 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4036 { 4037 int timeout=0; 4038 4039 switch (acb->adapter_type) { 4040 case ACB_ADAPTER_TYPE_A: { 4041 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4042 { 4043 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4044 { 4045 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4046 return; 4047 } 4048 UDELAY(15000); /* wait 15 milli-seconds */ 4049 } 4050 } 4051 break; 4052 case ACB_ADAPTER_TYPE_B: { 4053 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4054 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4055 { 4056 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4057 { 4058 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4059 return; 4060 } 4061 UDELAY(15000); /* wait 15 milli-seconds */ 4062 } 4063 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4064 } 4065 break; 4066 case ACB_ADAPTER_TYPE_C: { 4067 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4068 { 4069 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4070 { 4071 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4072 return; 4073 } 4074 UDELAY(15000); /* wait 15 milli-seconds */ 4075 } 4076 } 4077 break; 4078 case ACB_ADAPTER_TYPE_D: { 4079 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4080 { 4081 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4082 { 4083 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4084 return; 4085 } 4086 UDELAY(15000); /* wait 15 milli-seconds */ 4087 } 4088 } 4089 break; 4090 case ACB_ADAPTER_TYPE_E: { 4091 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4092 { 4093 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4094 { 4095 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4096 return; 4097 } 4098 UDELAY(15000); /* wait 15 milli-seconds */ 4099 } 4100 } 4101 break; 4102 } 4103 } 4104 /* 4105 ********************************************************************** 4106 ********************************************************************** 4107 */ 4108 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4109 { 4110 u_int32_t outbound_doorbell; 4111 4112 switch (acb->adapter_type) { 4113 case ACB_ADAPTER_TYPE_A: { 4114 /* empty doorbell Qbuffer if door bell ringed */ 4115 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4116 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4117 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4118 4119 } 4120 break; 4121 case ACB_ADAPTER_TYPE_B: { 4122 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4123 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4124 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4125 /* let IOP know data has been read */ 4126 } 4127 break; 4128 case ACB_ADAPTER_TYPE_C: { 4129 /* empty doorbell Qbuffer if door bell ringed */ 4130 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4131 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4132 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4133 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4134 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4135 } 4136 break; 4137 case ACB_ADAPTER_TYPE_D: { 4138 /* empty doorbell Qbuffer if door bell ringed */ 4139 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4140 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4141 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4142 4143 } 4144 break; 4145 case ACB_ADAPTER_TYPE_E: { 4146 /* empty doorbell Qbuffer if door bell ringed */ 4147 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4148 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4149 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4150 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4151 } 4152 break; 4153 } 4154 } 4155 /* 4156 ************************************************************************ 4157 ************************************************************************ 4158 */ 4159 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4160 { 4161 unsigned long srb_phyaddr; 4162 u_int32_t srb_phyaddr_hi32; 4163 u_int32_t srb_phyaddr_lo32; 4164 4165 /* 4166 ******************************************************************** 4167 ** here we need to tell iop 331 our freesrb.HighPart 4168 ** if freesrb.HighPart is not zero 4169 ******************************************************************** 4170 */ 4171 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4172 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4173 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4174 switch (acb->adapter_type) { 4175 case ACB_ADAPTER_TYPE_A: { 4176 if(srb_phyaddr_hi32 != 0) { 4177 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4178 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4179 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4180 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4181 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4182 return FALSE; 4183 } 4184 } 4185 } 4186 break; 4187 /* 4188 *********************************************************************** 4189 ** if adapter type B, set window of "post command Q" 4190 *********************************************************************** 4191 */ 4192 case ACB_ADAPTER_TYPE_B: { 4193 u_int32_t post_queue_phyaddr; 4194 struct HBB_MessageUnit *phbbmu; 4195 4196 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4197 phbbmu->postq_index = 0; 4198 phbbmu->doneq_index = 0; 4199 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4200 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4201 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4202 return FALSE; 4203 } 4204 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4205 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4206 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4207 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4208 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4209 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4210 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4211 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4212 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4213 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4214 return FALSE; 4215 } 4216 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4217 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4218 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4219 return FALSE; 4220 } 4221 } 4222 break; 4223 case ACB_ADAPTER_TYPE_C: { 4224 if(srb_phyaddr_hi32 != 0) { 4225 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4226 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4227 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4228 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4229 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4230 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4231 return FALSE; 4232 } 4233 } 4234 } 4235 break; 4236 case ACB_ADAPTER_TYPE_D: { 4237 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4238 struct HBD_MessageUnit0 *phbdmu; 4239 4240 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4241 phbdmu->postq_index = 0; 4242 phbdmu->doneq_index = 0x40FF; 4243 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4244 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4245 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4246 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4247 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4248 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4249 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4250 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4251 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4252 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4253 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4254 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4255 return FALSE; 4256 } 4257 } 4258 break; 4259 case ACB_ADAPTER_TYPE_E: { 4260 u_int32_t cdb_phyaddr_lo32; 4261 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4262 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4263 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4264 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4265 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4266 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4267 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4268 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4269 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4270 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4271 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4272 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4273 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4274 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4275 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4276 return FALSE; 4277 } 4278 } 4279 break; 4280 } 4281 return (TRUE); 4282 } 4283 /* 4284 ************************************************************************ 4285 ************************************************************************ 4286 */ 4287 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4288 { 4289 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4290 { 4291 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4292 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4293 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4294 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4295 return; 4296 } 4297 } 4298 } 4299 /* 4300 ********************************************************************** 4301 ********************************************************************** 4302 */ 4303 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4304 { 4305 u_int32_t intmask_org; 4306 4307 /* disable all outbound interrupt */ 4308 intmask_org = arcmsr_disable_allintr(acb); 4309 arcmsr_wait_firmware_ready(acb); 4310 arcmsr_iop_confirm(acb); 4311 arcmsr_get_firmware_spec(acb); 4312 /*start background rebuild*/ 4313 arcmsr_start_adapter_bgrb(acb); 4314 /* empty doorbell Qbuffer if door bell ringed */ 4315 arcmsr_clear_doorbell_queue_buffer(acb); 4316 arcmsr_enable_eoi_mode(acb); 4317 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4318 arcmsr_enable_allintr(acb, intmask_org); 4319 acb->acb_flags |= ACB_F_IOP_INITED; 4320 } 4321 /* 4322 ********************************************************************** 4323 ********************************************************************** 4324 */ 4325 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4326 { 4327 struct AdapterControlBlock *acb = arg; 4328 struct CommandControlBlock *srb_tmp; 4329 u_int32_t i; 4330 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4331 4332 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4333 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4334 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4335 if(bus_dmamap_create(acb->dm_segs_dmat, 4336 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4337 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4338 printf("arcmsr%d:" 4339 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4340 return; 4341 } 4342 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4343 || (acb->adapter_type == ACB_ADAPTER_TYPE_E)) 4344 { 4345 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4346 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4347 } 4348 else 4349 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4350 srb_tmp->acb = acb; 4351 srb_tmp->smid = i << 16; 4352 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4353 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4354 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4355 } 4356 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4357 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4358 } 4359 /* 4360 ************************************************************************ 4361 ************************************************************************ 4362 */ 4363 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4364 { 4365 /* remove the control device */ 4366 if(acb->ioctl_dev != NULL) { 4367 destroy_dev(acb->ioctl_dev); 4368 } 4369 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4370 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4371 bus_dma_tag_destroy(acb->srb_dmat); 4372 bus_dma_tag_destroy(acb->dm_segs_dmat); 4373 bus_dma_tag_destroy(acb->parent_dmat); 4374 } 4375 /* 4376 ************************************************************************ 4377 ************************************************************************ 4378 */ 4379 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4380 { 4381 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4382 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4383 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4384 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4385 } 4386 /* 4387 ************************************************************************ 4388 ************************************************************************ 4389 */ 4390 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4391 { 4392 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4393 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4394 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4395 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4396 } 4397 /* 4398 ************************************************************************ 4399 ************************************************************************ 4400 */ 4401 static u_int32_t arcmsr_initialize(device_t dev) 4402 { 4403 struct AdapterControlBlock *acb = device_get_softc(dev); 4404 u_int16_t pci_command; 4405 int i, j,max_coherent_size; 4406 u_int32_t vendor_dev_id; 4407 4408 vendor_dev_id = pci_get_devid(dev); 4409 acb->vendor_device_id = vendor_dev_id; 4410 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4411 switch (vendor_dev_id) { 4412 case PCIDevVenIDARC1880: 4413 case PCIDevVenIDARC1882: 4414 case PCIDevVenIDARC1213: 4415 case PCIDevVenIDARC1223: { 4416 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4417 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883) 4418 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4419 else 4420 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4421 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4422 } 4423 break; 4424 case PCIDevVenIDARC1884: 4425 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4426 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4427 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4428 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4429 break; 4430 case PCIDevVenIDARC1214: { 4431 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4432 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4433 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4434 } 4435 break; 4436 case PCIDevVenIDARC1200: 4437 case PCIDevVenIDARC1201: { 4438 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4439 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4440 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4441 } 4442 break; 4443 case PCIDevVenIDARC1203: { 4444 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4445 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4446 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4447 } 4448 break; 4449 case PCIDevVenIDARC1110: 4450 case PCIDevVenIDARC1120: 4451 case PCIDevVenIDARC1130: 4452 case PCIDevVenIDARC1160: 4453 case PCIDevVenIDARC1170: 4454 case PCIDevVenIDARC1210: 4455 case PCIDevVenIDARC1220: 4456 case PCIDevVenIDARC1230: 4457 case PCIDevVenIDARC1231: 4458 case PCIDevVenIDARC1260: 4459 case PCIDevVenIDARC1261: 4460 case PCIDevVenIDARC1270: 4461 case PCIDevVenIDARC1280: 4462 case PCIDevVenIDARC1212: 4463 case PCIDevVenIDARC1222: 4464 case PCIDevVenIDARC1380: 4465 case PCIDevVenIDARC1381: 4466 case PCIDevVenIDARC1680: 4467 case PCIDevVenIDARC1681: { 4468 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4469 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4470 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4471 } 4472 break; 4473 default: { 4474 printf("arcmsr%d:" 4475 " unknown RAID adapter type \n", device_get_unit(dev)); 4476 return ENOMEM; 4477 } 4478 } 4479 #if __FreeBSD_version >= 700000 4480 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4481 #else 4482 if(bus_dma_tag_create( /*PCI parent*/ NULL, 4483 #endif 4484 /*alignemnt*/ 1, 4485 /*boundary*/ 0, 4486 /*lowaddr*/ BUS_SPACE_MAXADDR, 4487 /*highaddr*/ BUS_SPACE_MAXADDR, 4488 /*filter*/ NULL, 4489 /*filterarg*/ NULL, 4490 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4491 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4492 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4493 /*flags*/ 0, 4494 #if __FreeBSD_version >= 501102 4495 /*lockfunc*/ NULL, 4496 /*lockarg*/ NULL, 4497 #endif 4498 &acb->parent_dmat) != 0) 4499 { 4500 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4501 return ENOMEM; 4502 } 4503 4504 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4505 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4506 /*alignment*/ 1, 4507 /*boundary*/ 0, 4508 #ifdef PAE 4509 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4510 #else 4511 /*lowaddr*/ BUS_SPACE_MAXADDR, 4512 #endif 4513 /*highaddr*/ BUS_SPACE_MAXADDR, 4514 /*filter*/ NULL, 4515 /*filterarg*/ NULL, 4516 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4517 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4518 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4519 /*flags*/ 0, 4520 #if __FreeBSD_version >= 501102 4521 /*lockfunc*/ busdma_lock_mutex, 4522 /*lockarg*/ &acb->isr_lock, 4523 #endif 4524 &acb->dm_segs_dmat) != 0) 4525 { 4526 bus_dma_tag_destroy(acb->parent_dmat); 4527 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4528 return ENOMEM; 4529 } 4530 4531 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4532 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4533 /*alignment*/ 0x20, 4534 /*boundary*/ 0, 4535 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4536 /*highaddr*/ BUS_SPACE_MAXADDR, 4537 /*filter*/ NULL, 4538 /*filterarg*/ NULL, 4539 /*maxsize*/ max_coherent_size, 4540 /*nsegments*/ 1, 4541 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4542 /*flags*/ 0, 4543 #if __FreeBSD_version >= 501102 4544 /*lockfunc*/ NULL, 4545 /*lockarg*/ NULL, 4546 #endif 4547 &acb->srb_dmat) != 0) 4548 { 4549 bus_dma_tag_destroy(acb->dm_segs_dmat); 4550 bus_dma_tag_destroy(acb->parent_dmat); 4551 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4552 return ENXIO; 4553 } 4554 /* Allocation for our srbs */ 4555 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4556 bus_dma_tag_destroy(acb->srb_dmat); 4557 bus_dma_tag_destroy(acb->dm_segs_dmat); 4558 bus_dma_tag_destroy(acb->parent_dmat); 4559 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4560 return ENXIO; 4561 } 4562 /* And permanently map them */ 4563 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4564 bus_dma_tag_destroy(acb->srb_dmat); 4565 bus_dma_tag_destroy(acb->dm_segs_dmat); 4566 bus_dma_tag_destroy(acb->parent_dmat); 4567 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4568 return ENXIO; 4569 } 4570 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4571 pci_command |= PCIM_CMD_BUSMASTEREN; 4572 pci_command |= PCIM_CMD_PERRESPEN; 4573 pci_command |= PCIM_CMD_MWRICEN; 4574 /* Enable Busmaster */ 4575 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4576 switch(acb->adapter_type) { 4577 case ACB_ADAPTER_TYPE_A: { 4578 u_int32_t rid0 = PCIR_BAR(0); 4579 vm_offset_t mem_base0; 4580 4581 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4582 if(acb->sys_res_arcmsr[0] == NULL) { 4583 arcmsr_free_resource(acb); 4584 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4585 return ENOMEM; 4586 } 4587 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4588 arcmsr_free_resource(acb); 4589 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4590 return ENXIO; 4591 } 4592 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4593 if(mem_base0 == 0) { 4594 arcmsr_free_resource(acb); 4595 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4596 return ENXIO; 4597 } 4598 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4599 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4600 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4601 acb->rid = 0; 4602 } 4603 break; 4604 case ACB_ADAPTER_TYPE_B: { 4605 struct HBB_MessageUnit *phbbmu; 4606 struct CommandControlBlock *freesrb; 4607 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4608 vm_offset_t mem_base[]={0,0}; 4609 u_long size; 4610 if (vendor_dev_id == PCIDevVenIDARC1203) 4611 size = sizeof(struct HBB_DOORBELL_1203); 4612 else 4613 size = sizeof(struct HBB_DOORBELL); 4614 for(i=0; i < 2; i++) { 4615 if(i == 0) { 4616 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid[i], 4617 RF_ACTIVE); 4618 } else { 4619 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], 4620 RF_ACTIVE); 4621 } 4622 if(acb->sys_res_arcmsr[i] == NULL) { 4623 arcmsr_free_resource(acb); 4624 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4625 return ENOMEM; 4626 } 4627 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4628 arcmsr_free_resource(acb); 4629 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4630 return ENXIO; 4631 } 4632 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4633 if(mem_base[i] == 0) { 4634 arcmsr_free_resource(acb); 4635 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4636 return ENXIO; 4637 } 4638 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4639 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4640 } 4641 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4642 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4643 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4644 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4645 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4646 if (vendor_dev_id == PCIDevVenIDARC1203) { 4647 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4648 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4649 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4650 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4651 } else { 4652 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4653 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4654 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4655 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4656 } 4657 acb->rid = 0; 4658 } 4659 break; 4660 case ACB_ADAPTER_TYPE_C: { 4661 u_int32_t rid0 = PCIR_BAR(1); 4662 vm_offset_t mem_base0; 4663 4664 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4665 if(acb->sys_res_arcmsr[0] == NULL) { 4666 arcmsr_free_resource(acb); 4667 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4668 return ENOMEM; 4669 } 4670 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4671 arcmsr_free_resource(acb); 4672 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4673 return ENXIO; 4674 } 4675 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4676 if(mem_base0 == 0) { 4677 arcmsr_free_resource(acb); 4678 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4679 return ENXIO; 4680 } 4681 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4682 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4683 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4684 acb->rid = 1; 4685 } 4686 break; 4687 case ACB_ADAPTER_TYPE_D: { 4688 struct HBD_MessageUnit0 *phbdmu; 4689 u_int32_t rid0 = PCIR_BAR(0); 4690 vm_offset_t mem_base0; 4691 4692 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4693 if(acb->sys_res_arcmsr[0] == NULL) { 4694 arcmsr_free_resource(acb); 4695 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4696 return ENOMEM; 4697 } 4698 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4699 arcmsr_free_resource(acb); 4700 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4701 return ENXIO; 4702 } 4703 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4704 if(mem_base0 == 0) { 4705 arcmsr_free_resource(acb); 4706 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4707 return ENXIO; 4708 } 4709 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4710 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4711 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4712 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4713 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4714 acb->rid = 0; 4715 } 4716 break; 4717 case ACB_ADAPTER_TYPE_E: { 4718 u_int32_t rid0 = PCIR_BAR(1); 4719 vm_offset_t mem_base0; 4720 4721 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBE_MessageUnit), RF_ACTIVE); 4722 if(acb->sys_res_arcmsr[0] == NULL) { 4723 arcmsr_free_resource(acb); 4724 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4725 return ENOMEM; 4726 } 4727 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4728 arcmsr_free_resource(acb); 4729 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4730 return ENXIO; 4731 } 4732 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4733 if(mem_base0 == 0) { 4734 arcmsr_free_resource(acb); 4735 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4736 return ENXIO; 4737 } 4738 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4739 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4740 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4741 acb->doneq_index = 0; 4742 acb->in_doorbell = 0; 4743 acb->out_doorbell = 0; 4744 acb->rid = 1; 4745 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4746 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4747 } 4748 break; 4749 } 4750 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4751 arcmsr_free_resource(acb); 4752 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4753 return ENXIO; 4754 } 4755 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4756 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4757 /* 4758 ******************************************************************** 4759 ** init raid volume state 4760 ******************************************************************** 4761 */ 4762 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4763 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4764 acb->devstate[i][j] = ARECA_RAID_GONE; 4765 } 4766 } 4767 arcmsr_iop_init(acb); 4768 return(0); 4769 } 4770 4771 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4772 { 4773 int i; 4774 4775 for (i = 0; i < acb->msix_vectors; i++) { 4776 acb->irq_id[i] = acb->rid + i; 4777 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4778 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4779 if (acb->irqres[i] == NULL) { 4780 printf("arcmsr: Can't allocate MSI-X resource\n"); 4781 goto irq_alloc_failed; 4782 } 4783 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4784 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4785 acb, &acb->ih[i])) { 4786 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4787 goto irq_alloc_failed; 4788 } 4789 } 4790 printf("arcmsr: MSI-X INT enabled\n"); 4791 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4792 return TRUE; 4793 4794 irq_alloc_failed: 4795 arcmsr_teardown_intr(acb->pci_dev, acb); 4796 return FALSE; 4797 } 4798 4799 /* 4800 ************************************************************************ 4801 ************************************************************************ 4802 */ 4803 static int arcmsr_attach(device_t dev) 4804 { 4805 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4806 u_int32_t unit=device_get_unit(dev); 4807 struct ccb_setasync csa; 4808 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4809 struct resource *irqres; 4810 4811 if(acb == NULL) { 4812 printf("arcmsr%d: cannot allocate softc\n", unit); 4813 return (ENOMEM); 4814 } 4815 arcmsr_mutex_init(acb); 4816 acb->pci_dev = dev; 4817 acb->pci_unit = unit; 4818 if(arcmsr_initialize(dev)) { 4819 printf("arcmsr%d: initialize failure!\n", unit); 4820 goto initialize_failed; 4821 } 4822 /* After setting up the adapter, map our interrupt */ 4823 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4824 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4825 if (arcmsr_setup_msix(acb) == TRUE) 4826 goto irqx; 4827 } 4828 acb->irq_id[0] = acb->rid; 4829 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4830 if(irqres == NULL || 4831 #if __FreeBSD_version >= 700025 4832 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4833 #else 4834 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih[0])) { 4835 #endif 4836 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4837 goto setup_intr_failed; 4838 } 4839 acb->irqres[0] = irqres; 4840 irqx: 4841 /* 4842 * Now let the CAM generic SCSI layer find the SCSI devices on 4843 * the bus * start queue to reset to the idle loop. * 4844 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4845 * max_sim_transactions 4846 */ 4847 devq = cam_simq_alloc(acb->maxOutstanding); 4848 if(devq == NULL) { 4849 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4850 goto simq_alloc_failed; 4851 } 4852 #if __FreeBSD_version >= 700025 4853 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4854 #else 4855 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4856 #endif 4857 if(acb->psim == NULL) { 4858 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4859 goto sim_alloc_failed; 4860 } 4861 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4862 #if __FreeBSD_version >= 700044 4863 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4864 #else 4865 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4866 #endif 4867 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4868 goto xpt_bus_failed; 4869 } 4870 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4871 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4872 goto xpt_path_failed; 4873 } 4874 /* 4875 **************************************************** 4876 */ 4877 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4878 csa.ccb_h.func_code = XPT_SASYNC_CB; 4879 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4880 csa.callback = arcmsr_async; 4881 csa.callback_arg = acb->psim; 4882 xpt_action((union ccb *)&csa); 4883 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4884 /* Create the control device. */ 4885 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4886 4887 #if __FreeBSD_version < 503000 4888 acb->ioctl_dev->si_drv1 = acb; 4889 #endif 4890 #if __FreeBSD_version > 500005 4891 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4892 #endif 4893 arcmsr_callout_init(&acb->devmap_callout); 4894 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4895 return (0); 4896 xpt_path_failed: 4897 xpt_bus_deregister(cam_sim_path(acb->psim)); 4898 xpt_bus_failed: 4899 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4900 sim_alloc_failed: 4901 cam_simq_free(devq); 4902 simq_alloc_failed: 4903 arcmsr_teardown_intr(dev, acb); 4904 setup_intr_failed: 4905 arcmsr_free_resource(acb); 4906 initialize_failed: 4907 arcmsr_mutex_destroy(acb); 4908 return ENXIO; 4909 } 4910 4911 /* 4912 ************************************************************************ 4913 ************************************************************************ 4914 */ 4915 static int arcmsr_probe(device_t dev) 4916 { 4917 u_int32_t id; 4918 u_int16_t sub_device_id; 4919 static char buf[256]; 4920 char x_type[]={"unknown"}; 4921 char *type; 4922 int raid6 = 1; 4923 4924 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4925 return (ENXIO); 4926 } 4927 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4928 switch(id = pci_get_devid(dev)) { 4929 case PCIDevVenIDARC1110: 4930 case PCIDevVenIDARC1200: 4931 case PCIDevVenIDARC1201: 4932 case PCIDevVenIDARC1210: 4933 raid6 = 0; 4934 /*FALLTHRU*/ 4935 case PCIDevVenIDARC1120: 4936 case PCIDevVenIDARC1130: 4937 case PCIDevVenIDARC1160: 4938 case PCIDevVenIDARC1170: 4939 case PCIDevVenIDARC1220: 4940 case PCIDevVenIDARC1230: 4941 case PCIDevVenIDARC1231: 4942 case PCIDevVenIDARC1260: 4943 case PCIDevVenIDARC1261: 4944 case PCIDevVenIDARC1270: 4945 case PCIDevVenIDARC1280: 4946 type = "SATA 3G"; 4947 break; 4948 case PCIDevVenIDARC1212: 4949 case PCIDevVenIDARC1222: 4950 case PCIDevVenIDARC1380: 4951 case PCIDevVenIDARC1381: 4952 case PCIDevVenIDARC1680: 4953 case PCIDevVenIDARC1681: 4954 type = "SAS 3G"; 4955 break; 4956 case PCIDevVenIDARC1880: 4957 case PCIDevVenIDARC1882: 4958 case PCIDevVenIDARC1213: 4959 case PCIDevVenIDARC1223: 4960 if (sub_device_id == ARECA_SUB_DEV_ID_1883) 4961 type = "SAS 12G"; 4962 else 4963 type = "SAS 6G"; 4964 break; 4965 case PCIDevVenIDARC1884: 4966 type = "SAS 12G"; 4967 break; 4968 case PCIDevVenIDARC1214: 4969 case PCIDevVenIDARC1203: 4970 type = "SATA 6G"; 4971 break; 4972 default: 4973 type = x_type; 4974 raid6 = 0; 4975 break; 4976 } 4977 if(type == x_type) 4978 return(ENXIO); 4979 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 4980 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4981 device_set_desc_copy(dev, buf); 4982 return (BUS_PROBE_DEFAULT); 4983 } 4984 /* 4985 ************************************************************************ 4986 ************************************************************************ 4987 */ 4988 static int arcmsr_shutdown(device_t dev) 4989 { 4990 u_int32_t i; 4991 u_int32_t intmask_org; 4992 struct CommandControlBlock *srb; 4993 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4994 4995 /* stop adapter background rebuild */ 4996 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4997 /* disable all outbound interrupt */ 4998 intmask_org = arcmsr_disable_allintr(acb); 4999 arcmsr_stop_adapter_bgrb(acb); 5000 arcmsr_flush_adapter_cache(acb); 5001 /* abort all outstanding command */ 5002 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5003 acb->acb_flags &= ~ACB_F_IOP_INITED; 5004 if(acb->srboutstandingcount != 0) { 5005 /*clear and abort all outbound posted Q*/ 5006 arcmsr_done4abort_postqueue(acb); 5007 /* talk to iop 331 outstanding command aborted*/ 5008 arcmsr_abort_allcmd(acb); 5009 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5010 srb = acb->psrb_pool[i]; 5011 if(srb->srb_state == ARCMSR_SRB_START) { 5012 srb->srb_state = ARCMSR_SRB_ABORTED; 5013 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5014 arcmsr_srb_complete(srb, 1); 5015 } 5016 } 5017 } 5018 acb->srboutstandingcount = 0; 5019 acb->workingsrb_doneindex = 0; 5020 acb->workingsrb_startindex = 0; 5021 acb->pktRequestCount = 0; 5022 acb->pktReturnCount = 0; 5023 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5024 return (0); 5025 } 5026 /* 5027 ************************************************************************ 5028 ************************************************************************ 5029 */ 5030 void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5031 { 5032 int i; 5033 5034 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5035 for (i = 0; i < acb->msix_vectors; i++) { 5036 if (acb->ih[i]) 5037 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5038 if (acb->irqres[i] != NULL) 5039 bus_release_resource(dev, SYS_RES_IRQ, 5040 acb->irq_id[i], acb->irqres[i]); 5041 5042 acb->ih[i] = NULL; 5043 } 5044 pci_release_msi(dev); 5045 } else { 5046 if (acb->ih[0]) 5047 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5048 if (acb->irqres[0] != NULL) 5049 bus_release_resource(dev, SYS_RES_IRQ, 5050 acb->irq_id[0], acb->irqres[0]); 5051 acb->ih[0] = NULL; 5052 } 5053 5054 } 5055 /* 5056 ************************************************************************ 5057 ************************************************************************ 5058 */ 5059 static int arcmsr_detach(device_t dev) 5060 { 5061 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5062 int i; 5063 5064 callout_stop(&acb->devmap_callout); 5065 arcmsr_teardown_intr(dev, acb); 5066 arcmsr_shutdown(dev); 5067 arcmsr_free_resource(acb); 5068 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5069 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 5070 } 5071 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5072 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5073 xpt_free_path(acb->ppath); 5074 xpt_bus_deregister(cam_sim_path(acb->psim)); 5075 cam_sim_free(acb->psim, TRUE); 5076 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5077 arcmsr_mutex_destroy(acb); 5078 return (0); 5079 } 5080 5081 #ifdef ARCMSR_DEBUG1 5082 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5083 { 5084 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5085 return; 5086 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5087 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5088 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5089 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5090 } 5091 #endif 5092 5093