1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 #if 0 30 #define ATA_LEGACY_SUPPORT /* Enable obsolete features that break 31 * some modern devices */ 32 #endif 33 34 /* ATA register defines */ 35 #define ATA_DATA 0 /* (RW) data */ 36 37 #define ATA_FEATURE 1 /* (W) feature */ 38 #define ATA_F_DMA 0x01 /* enable DMA */ 39 #define ATA_F_OVL 0x02 /* enable overlap */ 40 41 #define ATA_COUNT 2 /* (W) sector count */ 42 43 #define ATA_SECTOR 3 /* (RW) sector # */ 44 #define ATA_CYL_LSB 4 /* (RW) cylinder# LSB */ 45 #define ATA_CYL_MSB 5 /* (RW) cylinder# MSB */ 46 #define ATA_DRIVE 6 /* (W) Sector/Drive/Head */ 47 #define ATA_D_LBA 0x40 /* use LBA addressing */ 48 #define ATA_D_IBM 0xa0 /* 512 byte sectors, ECC */ 49 50 #define ATA_COMMAND 7 /* (W) command */ 51 52 #define ATA_ERROR 8 /* (R) error */ 53 #define ATA_E_ILI 0x01 /* illegal length */ 54 #define ATA_E_NM 0x02 /* no media */ 55 #define ATA_E_ABORT 0x04 /* command aborted */ 56 #define ATA_E_MCR 0x08 /* media change request */ 57 #define ATA_E_IDNF 0x10 /* ID not found */ 58 #define ATA_E_MC 0x20 /* media changed */ 59 #define ATA_E_UNC 0x40 /* uncorrectable data */ 60 #define ATA_E_ICRC 0x80 /* UDMA crc error */ 61 #define ATA_E_ATAPI_SENSE_MASK 0xf0 /* ATAPI sense key mask */ 62 63 #define ATA_IREASON 9 /* (R) interrupt reason */ 64 #define ATA_I_CMD 0x01 /* cmd (1) | data (0) */ 65 #define ATA_I_IN 0x02 /* read (1) | write (0) */ 66 #define ATA_I_RELEASE 0x04 /* released bus (1) */ 67 #define ATA_I_TAGMASK 0xf8 /* tag mask */ 68 69 #define ATA_STATUS 10 /* (R) status */ 70 #define ATA_ALTSTAT 11 /* (R) alternate status */ 71 #define ATA_S_ERROR 0x01 /* error */ 72 #define ATA_S_INDEX 0x02 /* index */ 73 #define ATA_S_CORR 0x04 /* data corrected */ 74 #define ATA_S_DRQ 0x08 /* data request */ 75 #define ATA_S_DSC 0x10 /* drive seek completed */ 76 #define ATA_S_SERVICE 0x10 /* drive needs service */ 77 #define ATA_S_DWF 0x20 /* drive write fault */ 78 #define ATA_S_DMA 0x20 /* DMA ready */ 79 #define ATA_S_READY 0x40 /* drive ready */ 80 #define ATA_S_BUSY 0x80 /* busy */ 81 82 #define ATA_CONTROL 12 /* (W) control */ 83 84 #define ATA_CTLOFFSET 0x206 /* control register offset */ 85 #define ATA_PCCARD_CTLOFFSET 0x0e /* do for PCCARD devices */ 86 #define ATA_A_IDS 0x02 /* disable interrupts */ 87 #define ATA_A_RESET 0x04 /* RESET controller */ 88 #ifdef ATA_LEGACY_SUPPORT 89 #define ATA_A_4BIT 0x08 /* 4 head bits: obsolete 1996 */ 90 #else 91 #define ATA_A_4BIT 0x00 92 #endif 93 #define ATA_A_HOB 0x80 /* High Order Byte enable */ 94 95 /* SATA register defines */ 96 #define ATA_SSTATUS 13 97 #define ATA_SS_DET_MASK 0x0000000f 98 #define ATA_SS_DET_NO_DEVICE 0x00000000 99 #define ATA_SS_DET_DEV_PRESENT 0x00000001 100 #define ATA_SS_DET_PHY_ONLINE 0x00000003 101 #define ATA_SS_DET_PHY_OFFLINE 0x00000004 102 103 #define ATA_SS_SPD_MASK 0x000000f0 104 #define ATA_SS_SPD_NO_SPEED 0x00000000 105 #define ATA_SS_SPD_GEN1 0x00000010 106 #define ATA_SS_SPD_GEN2 0x00000020 107 #define ATA_SS_SPD_GEN3 0x00000030 108 109 #define ATA_SS_IPM_MASK 0x00000f00 110 #define ATA_SS_IPM_NO_DEVICE 0x00000000 111 #define ATA_SS_IPM_ACTIVE 0x00000100 112 #define ATA_SS_IPM_PARTIAL 0x00000200 113 #define ATA_SS_IPM_SLUMBER 0x00000600 114 115 #define ATA_SERROR 14 116 #define ATA_SE_DATA_CORRECTED 0x00000001 117 #define ATA_SE_COMM_CORRECTED 0x00000002 118 #define ATA_SE_DATA_ERR 0x00000100 119 #define ATA_SE_COMM_ERR 0x00000200 120 #define ATA_SE_PROT_ERR 0x00000400 121 #define ATA_SE_HOST_ERR 0x00000800 122 #define ATA_SE_PHY_CHANGED 0x00010000 123 #define ATA_SE_PHY_IERROR 0x00020000 124 #define ATA_SE_COMM_WAKE 0x00040000 125 #define ATA_SE_DECODE_ERR 0x00080000 126 #define ATA_SE_PARITY_ERR 0x00100000 127 #define ATA_SE_CRC_ERR 0x00200000 128 #define ATA_SE_HANDSHAKE_ERR 0x00400000 129 #define ATA_SE_LINKSEQ_ERR 0x00800000 130 #define ATA_SE_TRANSPORT_ERR 0x01000000 131 #define ATA_SE_UNKNOWN_FIS 0x02000000 132 133 #define ATA_SCONTROL 15 134 #define ATA_SC_DET_MASK 0x0000000f 135 #define ATA_SC_DET_IDLE 0x00000000 136 #define ATA_SC_DET_RESET 0x00000001 137 #define ATA_SC_DET_DISABLE 0x00000004 138 139 #define ATA_SC_SPD_MASK 0x000000f0 140 #define ATA_SC_SPD_NO_SPEED 0x00000000 141 #define ATA_SC_SPD_SPEED_GEN1 0x00000010 142 #define ATA_SC_SPD_SPEED_GEN2 0x00000020 143 #define ATA_SC_SPD_SPEED_GEN3 0x00000030 144 145 #define ATA_SC_IPM_MASK 0x00000f00 146 #define ATA_SC_IPM_NONE 0x00000000 147 #define ATA_SC_IPM_DIS_PARTIAL 0x00000100 148 #define ATA_SC_IPM_DIS_SLUMBER 0x00000200 149 150 #define ATA_SACTIVE 16 151 152 /* DMA register defines */ 153 #define ATA_DMA_ENTRIES 256 154 #define ATA_DMA_EOT 0x80000000 155 156 #define ATA_BMCMD_PORT 17 157 #define ATA_BMCMD_START_STOP 0x01 158 #define ATA_BMCMD_WRITE_READ 0x08 159 160 #define ATA_BMDEVSPEC_0 18 161 #define ATA_BMSTAT_PORT 19 162 #define ATA_BMSTAT_ACTIVE 0x01 163 #define ATA_BMSTAT_ERROR 0x02 164 #define ATA_BMSTAT_INTERRUPT 0x04 165 #define ATA_BMSTAT_MASK 0x07 166 #define ATA_BMSTAT_DMA_MASTER 0x20 167 #define ATA_BMSTAT_DMA_SLAVE 0x40 168 #define ATA_BMSTAT_DMA_SIMPLEX 0x80 169 170 #define ATA_BMDEVSPEC_1 20 171 #define ATA_BMDTP_PORT 21 172 173 #define ATA_IDX_ADDR 22 174 #define ATA_IDX_DATA 23 175 #define ATA_MAX_RES 24 176 177 /* misc defines */ 178 #define ATA_PRIMARY 0x1f0 179 #define ATA_SECONDARY 0x170 180 #define ATA_IOSIZE 0x08 181 #define ATA_CTLIOSIZE 0x01 182 #define ATA_BMIOSIZE 0x08 183 #define ATA_IOADDR_RID 0 184 #define ATA_CTLADDR_RID 1 185 #define ATA_BMADDR_RID 0x20 186 #define ATA_IRQ_RID 0 187 #define ATA_DEV(unit) ((unit > 0) ? 0x10 : 0) 188 #define ATA_CFA_MAGIC1 0x844A 189 #define ATA_CFA_MAGIC2 0x848A 190 #define ATA_CFA_MAGIC3 0x8400 191 #define ATAPI_MAGIC_LSB 0x14 192 #define ATAPI_MAGIC_MSB 0xeb 193 #define ATAPI_P_READ (ATA_S_DRQ | ATA_I_IN) 194 #define ATAPI_P_WRITE (ATA_S_DRQ) 195 #define ATAPI_P_CMDOUT (ATA_S_DRQ | ATA_I_CMD) 196 #define ATAPI_P_DONEDRQ (ATA_S_DRQ | ATA_I_CMD | ATA_I_IN) 197 #define ATAPI_P_DONE (ATA_I_CMD | ATA_I_IN) 198 #define ATAPI_P_ABORT 0 199 #define ATA_INTR_FLAGS (INTR_MPSAFE|INTR_TYPE_BIO|INTR_ENTROPY) 200 #define ATA_OP_CONTINUES 0 201 #define ATA_OP_FINISHED 1 202 #define ATA_MAX_28BIT_LBA 268435455UL 203 204 #ifndef ATA_REQUEST_TIMEOUT 205 #define ATA_REQUEST_TIMEOUT 10 206 #endif 207 208 /* structure used for composite atomic operations */ 209 #define MAX_COMPOSITES 32 /* u_int32_t bits */ 210 struct ata_composite { 211 struct mtx lock; /* control lock */ 212 u_int32_t rd_needed; /* needed read subdisks */ 213 u_int32_t rd_done; /* done read subdisks */ 214 u_int32_t wr_needed; /* needed write subdisks */ 215 u_int32_t wr_depend; /* write depends on subdisks */ 216 u_int32_t wr_done; /* done write subdisks */ 217 struct ata_request *request[MAX_COMPOSITES]; 218 u_int32_t residual; /* bytes still to transfer */ 219 caddr_t data_1; 220 caddr_t data_2; 221 }; 222 223 /* structure used to queue an ATA/ATAPI request */ 224 struct ata_request { 225 device_t dev; /* device handle */ 226 device_t parent; /* channel handle */ 227 int unit; /* physical unit */ 228 union { 229 struct { 230 u_int8_t command; /* command reg */ 231 u_int16_t feature; /* feature reg */ 232 u_int16_t count; /* count reg */ 233 u_int64_t lba; /* lba reg */ 234 } ata; 235 struct { 236 u_int8_t ccb[16]; /* ATAPI command block */ 237 struct atapi_sense sense; /* ATAPI request sense data */ 238 u_int8_t saved_cmd; /* ATAPI saved command */ 239 } atapi; 240 } u; 241 u_int32_t bytecount; /* bytes to transfer */ 242 u_int32_t transfersize; /* bytes pr transfer */ 243 caddr_t data; /* pointer to data buf */ 244 u_int32_t tag; /* HW tag of this request */ 245 int flags; 246 #define ATA_R_CONTROL 0x00000001 247 #define ATA_R_READ 0x00000002 248 #define ATA_R_WRITE 0x00000004 249 #define ATA_R_ATAPI 0x00000008 250 #define ATA_R_DMA 0x00000010 251 #define ATA_R_QUIET 0x00000020 252 #define ATA_R_TIMEOUT 0x00000040 253 #define ATA_R_48BIT 0x00000080 254 255 #define ATA_R_ORDERED 0x00000100 256 #define ATA_R_AT_HEAD 0x00000200 257 #define ATA_R_REQUEUE 0x00000400 258 #define ATA_R_THREAD 0x00000800 259 #define ATA_R_DIRECT 0x00001000 260 #define ATA_R_NEEDRESULT 0x00002000 261 #define ATA_R_DATA_IN_CCB 0x00004000 262 263 #define ATA_R_ATAPI16 0x00010000 264 #define ATA_R_ATAPI_INTR 0x00020000 265 266 #define ATA_R_DEBUG 0x10000000 267 #define ATA_R_DANGER1 0x20000000 268 #define ATA_R_DANGER2 0x40000000 269 270 struct ata_dmaslot *dma; /* DMA slot of this request */ 271 u_int8_t status; /* ATA status */ 272 u_int8_t error; /* ATA error */ 273 u_int32_t donecount; /* bytes transferred */ 274 int result; /* result error code */ 275 void (*callback)(struct ata_request *request); 276 struct sema done; /* request done sema */ 277 int retries; /* retry count */ 278 int timeout; /* timeout for this cmd */ 279 struct callout callout; /* callout management */ 280 struct task task; /* task management */ 281 struct bio *bio; /* bio for this request */ 282 int this; /* this request ID */ 283 struct ata_composite *composite; /* for composite atomic ops */ 284 void *driver; /* driver specific */ 285 TAILQ_ENTRY(ata_request) chain; /* list management */ 286 union ccb *ccb; 287 }; 288 289 /* define this for debugging request processing */ 290 #if 0 291 #define ATA_DEBUG_RQ(request, string) \ 292 { \ 293 if (request->flags & ATA_R_DEBUG) \ 294 device_printf(request->parent, "req=%p %s " string "\n", \ 295 request, ata_cmd2str(request)); \ 296 } 297 #else 298 #define ATA_DEBUG_RQ(request, string) 299 #endif 300 301 302 /* structure describing an ATA/ATAPI device */ 303 struct ata_device { 304 device_t dev; /* device handle */ 305 int unit; /* physical unit */ 306 #define ATA_MASTER 0x00 307 #define ATA_SLAVE 0x01 308 #define ATA_PM 0x0f 309 310 struct ata_params param; /* ata param structure */ 311 int mode; /* current transfermode */ 312 u_int32_t max_iosize; /* max IO size */ 313 int spindown; /* idle spindown timeout */ 314 struct callout spindown_timer; 315 int spindown_state; 316 int flags; 317 #define ATA_D_USE_CHS 0x0001 318 #define ATA_D_MEDIA_CHANGED 0x0002 319 #define ATA_D_ENC_PRESENT 0x0004 320 }; 321 322 /* structure for holding DMA Physical Region Descriptors (PRD) entries */ 323 struct ata_dma_prdentry { 324 u_int32_t addr; 325 u_int32_t count; 326 }; 327 328 /* structure used by the setprd function */ 329 struct ata_dmasetprd_args { 330 void *dmatab; 331 int nsegs; 332 int error; 333 }; 334 335 struct ata_dmaslot { 336 u_int8_t status; /* DMA status */ 337 bus_dma_tag_t sg_tag; /* SG list DMA tag */ 338 bus_dmamap_t sg_map; /* SG list DMA map */ 339 void *sg; /* DMA transfer table */ 340 bus_addr_t sg_bus; /* bus address of dmatab */ 341 bus_dma_tag_t data_tag; /* data DMA tag */ 342 bus_dmamap_t data_map; /* data DMA map */ 343 }; 344 345 /* structure holding DMA related information */ 346 struct ata_dma { 347 bus_dma_tag_t dmatag; /* parent DMA tag */ 348 bus_dma_tag_t work_tag; /* workspace DMA tag */ 349 bus_dmamap_t work_map; /* workspace DMA map */ 350 u_int8_t *work; /* workspace */ 351 bus_addr_t work_bus; /* bus address of dmatab */ 352 353 #define ATA_DMA_SLOTS 1 354 int dma_slots; /* DMA slots allocated */ 355 struct ata_dmaslot slot[ATA_DMA_SLOTS]; 356 u_int32_t alignment; /* DMA SG list alignment */ 357 u_int32_t boundary; /* DMA SG list boundary */ 358 u_int32_t segsize; /* DMA SG list segment size */ 359 u_int32_t max_iosize; /* DMA data max IO size */ 360 u_int64_t max_address; /* highest DMA'able address */ 361 int flags; 362 #define ATA_DMA_ACTIVE 0x01 /* DMA transfer in progress */ 363 364 void (*alloc)(device_t dev); 365 void (*free)(device_t dev); 366 void (*setprd)(void *xsc, bus_dma_segment_t *segs, int nsegs, int error); 367 int (*load)(struct ata_request *request, void *addr, int *nsegs); 368 int (*unload)(struct ata_request *request); 369 int (*start)(struct ata_request *request); 370 int (*stop)(struct ata_request *request); 371 void (*reset)(device_t dev); 372 }; 373 374 /* structure holding lowlevel functions */ 375 struct ata_lowlevel { 376 u_int32_t (*softreset)(device_t dev, int pmport); 377 int (*pm_read)(device_t dev, int port, int reg, u_int32_t *result); 378 int (*pm_write)(device_t dev, int port, int reg, u_int32_t value); 379 int (*status)(device_t dev); 380 int (*begin_transaction)(struct ata_request *request); 381 int (*end_transaction)(struct ata_request *request); 382 int (*command)(struct ata_request *request); 383 void (*tf_read)(struct ata_request *request); 384 void (*tf_write)(struct ata_request *request); 385 }; 386 387 /* structure holding resources for an ATA channel */ 388 struct ata_resource { 389 struct resource *res; 390 int offset; 391 }; 392 393 struct ata_cam_device { 394 u_int revision; 395 int mode; 396 u_int bytecount; 397 u_int atapi; 398 u_int caps; 399 }; 400 401 /* structure describing an ATA channel */ 402 struct ata_channel { 403 device_t dev; /* device handle */ 404 int unit; /* physical channel */ 405 int attached; /* channel is attached */ 406 struct ata_resource r_io[ATA_MAX_RES];/* I/O resources */ 407 struct resource *r_irq; /* interrupt of this channel */ 408 void *ih; /* interrupt handle */ 409 struct ata_lowlevel hw; /* lowlevel HW functions */ 410 struct ata_dma dma; /* DMA data / functions */ 411 int flags; /* channel flags */ 412 #define ATA_NO_SLAVE 0x01 413 #define ATA_USE_16BIT 0x02 414 #define ATA_ATAPI_DMA_RO 0x04 415 #define ATA_NO_48BIT_DMA 0x08 416 #define ATA_ALWAYS_DMASTAT 0x10 417 #define ATA_CHECKS_CABLE 0x20 418 #define ATA_NO_ATAPI_DMA 0x40 419 #define ATA_SATA 0x80 420 #define ATA_DMA_BEFORE_CMD 0x100 421 #define ATA_KNOWN_PRESENCE 0x200 422 #define ATA_STATUS_IS_LONG 0x400 423 #define ATA_PERIODIC_POLL 0x800 424 425 int pm_level; /* power management level */ 426 int devices; /* what is present */ 427 #define ATA_ATA_MASTER 0x00000001 428 #define ATA_ATA_SLAVE 0x00000002 429 #define ATA_PORTMULTIPLIER 0x00008000 430 #define ATA_ATAPI_MASTER 0x00010000 431 #define ATA_ATAPI_SLAVE 0x00020000 432 433 struct mtx state_mtx; /* state lock */ 434 int state; /* ATA channel state */ 435 #define ATA_IDLE 0x0000 436 #define ATA_ACTIVE 0x0001 437 #define ATA_STALL_QUEUE 0x0002 438 439 struct ata_request *running; /* currently running request */ 440 struct task conntask; /* PHY events handling task */ 441 struct cam_sim *sim; 442 struct cam_path *path; 443 struct ata_cam_device user[16]; /* User-specified settings */ 444 struct ata_cam_device curr[16]; /* Current settings */ 445 int requestsense; /* CCB waiting for SENSE. */ 446 struct callout poll_callout; /* Periodic status poll. */ 447 struct ata_request request; 448 }; 449 450 /* disk bay/enclosure related */ 451 #define ATA_LED_OFF 0x00 452 #define ATA_LED_RED 0x01 453 #define ATA_LED_GREEN 0x02 454 #define ATA_LED_ORANGE 0x03 455 #define ATA_LED_MASK 0x03 456 457 /* externs */ 458 extern int (*ata_raid_ioctl_func)(u_long cmd, caddr_t data); 459 extern struct intr_config_hook *ata_delayed_attach; 460 extern devclass_t ata_devclass; 461 extern int ata_wc; 462 extern int ata_setmax; 463 extern int ata_dma_check_80pin; 464 465 /* public prototypes */ 466 /* ata-all.c: */ 467 int ata_probe(device_t dev); 468 int ata_attach(device_t dev); 469 int ata_detach(device_t dev); 470 int ata_reinit(device_t dev); 471 int ata_suspend(device_t dev); 472 int ata_resume(device_t dev); 473 void ata_interrupt(void *data); 474 int ata_getparam(struct ata_device *atadev, int init); 475 void ata_default_registers(device_t dev); 476 void ata_udelay(int interval); 477 const char *ata_cmd2str(struct ata_request *request); 478 const char *ata_mode2str(int mode); 479 void ata_setmode(device_t dev); 480 void ata_print_cable(device_t dev, u_int8_t *who); 481 int ata_atapi(device_t dev, int target); 482 void ata_timeout(struct ata_request *); 483 484 /* ata-lowlevel.c: */ 485 void ata_generic_hw(device_t dev); 486 int ata_begin_transaction(struct ata_request *); 487 int ata_end_transaction(struct ata_request *); 488 void ata_generic_reset(device_t dev); 489 int ata_generic_command(struct ata_request *request); 490 491 /* ata-dma.c: */ 492 void ata_dmainit(device_t); 493 void ata_dmafini(device_t dev); 494 495 /* ata-sata.c: */ 496 void ata_sata_phy_check_events(device_t dev, int port); 497 int ata_sata_scr_read(struct ata_channel *ch, int port, int reg, uint32_t *val); 498 int ata_sata_scr_write(struct ata_channel *ch, int port, int reg, uint32_t val); 499 int ata_sata_phy_reset(device_t dev, int port, int quick); 500 int ata_sata_setmode(device_t dev, int target, int mode); 501 int ata_sata_getrev(device_t dev, int target); 502 int ata_request2fis_h2d(struct ata_request *request, u_int8_t *fis); 503 void ata_pm_identify(device_t dev); 504 505 MALLOC_DECLARE(M_ATA); 506 507 /* misc newbus defines */ 508 #define GRANDPARENT(dev) device_get_parent(device_get_parent(dev)) 509 510 /* macros to hide busspace uglyness */ 511 #define ATA_INB(res, offset) \ 512 bus_read_1((res), (offset)) 513 514 #define ATA_INW(res, offset) \ 515 bus_read_2((res), (offset)) 516 #define ATA_INW_STRM(res, offset) \ 517 bus_read_stream_2((res), (offset)) 518 #define ATA_INL(res, offset) \ 519 bus_read_4((res), (offset)) 520 #define ATA_INSW(res, offset, addr, count) \ 521 bus_read_multi_2((res), (offset), (addr), (count)) 522 #define ATA_INSW_STRM(res, offset, addr, count) \ 523 bus_read_multi_stream_2((res), (offset), (addr), (count)) 524 #define ATA_INSL(res, offset, addr, count) \ 525 bus_read_multi_4((res), (offset), (addr), (count)) 526 #define ATA_INSL_STRM(res, offset, addr, count) \ 527 bus_read_multi_stream_4((res), (offset), (addr), (count)) 528 #define ATA_OUTB(res, offset, value) \ 529 bus_write_1((res), (offset), (value)) 530 #define ATA_OUTW(res, offset, value) \ 531 bus_write_2((res), (offset), (value)) 532 #define ATA_OUTW_STRM(res, offset, value) \ 533 bus_write_stream_2((res), (offset), (value)) 534 #define ATA_OUTL(res, offset, value) \ 535 bus_write_4((res), (offset), (value)) 536 #define ATA_OUTSW(res, offset, addr, count) \ 537 bus_write_multi_2((res), (offset), (addr), (count)) 538 #define ATA_OUTSW_STRM(res, offset, addr, count) \ 539 bus_write_multi_stream_2((res), (offset), (addr), (count)) 540 #define ATA_OUTSL(res, offset, addr, count) \ 541 bus_write_multi_4((res), (offset), (addr), (count)) 542 #define ATA_OUTSL_STRM(res, offset, addr, count) \ 543 bus_write_multi_stream_4((res), (offset), (addr), (count)) 544 545 #define ATA_IDX_INB(ch, idx) \ 546 ATA_INB(ch->r_io[idx].res, ch->r_io[idx].offset) 547 548 #define ATA_IDX_INW(ch, idx) \ 549 ATA_INW(ch->r_io[idx].res, ch->r_io[idx].offset) 550 551 #define ATA_IDX_INW_STRM(ch, idx) \ 552 ATA_INW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset) 553 554 #define ATA_IDX_INL(ch, idx) \ 555 ATA_INL(ch->r_io[idx].res, ch->r_io[idx].offset) 556 557 #define ATA_IDX_INSW(ch, idx, addr, count) \ 558 ATA_INSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 559 560 #define ATA_IDX_INSW_STRM(ch, idx, addr, count) \ 561 ATA_INSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 562 563 #define ATA_IDX_INSL(ch, idx, addr, count) \ 564 ATA_INSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 565 566 #define ATA_IDX_INSL_STRM(ch, idx, addr, count) \ 567 ATA_INSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 568 569 #define ATA_IDX_OUTB(ch, idx, value) \ 570 ATA_OUTB(ch->r_io[idx].res, ch->r_io[idx].offset, value) 571 572 #define ATA_IDX_OUTW(ch, idx, value) \ 573 ATA_OUTW(ch->r_io[idx].res, ch->r_io[idx].offset, value) 574 575 #define ATA_IDX_OUTW_STRM(ch, idx, value) \ 576 ATA_OUTW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, value) 577 578 #define ATA_IDX_OUTL(ch, idx, value) \ 579 ATA_OUTL(ch->r_io[idx].res, ch->r_io[idx].offset, value) 580 581 #define ATA_IDX_OUTSW(ch, idx, addr, count) \ 582 ATA_OUTSW(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 583 584 #define ATA_IDX_OUTSW_STRM(ch, idx, addr, count) \ 585 ATA_OUTSW_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 586 587 #define ATA_IDX_OUTSL(ch, idx, addr, count) \ 588 ATA_OUTSL(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 589 590 #define ATA_IDX_OUTSL_STRM(ch, idx, addr, count) \ 591 ATA_OUTSL_STRM(ch->r_io[idx].res, ch->r_io[idx].offset, addr, count) 592