1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_serverworks_chipinit(device_t dev); 55 static int ata_serverworks_ch_attach(device_t dev); 56 static int ata_serverworks_ch_detach(device_t dev); 57 static void ata_serverworks_tf_read(struct ata_request *request); 58 static void ata_serverworks_tf_write(struct ata_request *request); 59 static int ata_serverworks_setmode(device_t dev, int target, int mode); 60 static void ata_serverworks_sata_reset(device_t dev); 61 static int ata_serverworks_status(device_t dev); 62 63 /* misc defines */ 64 #define SWKS_33 0 65 #define SWKS_66 1 66 #define SWKS_100 2 67 #define SWKS_MIO 3 68 69 70 /* 71 * ServerWorks chipset support functions 72 */ 73 static int 74 ata_serverworks_probe(device_t dev) 75 { 76 struct ata_pci_controller *ctlr = device_get_softc(dev); 77 static const struct ata_chip_id ids[] = 78 {{ ATA_ROSB4, 0x00, SWKS_33, 0, ATA_WDMA2, "ROSB4" }, 79 { ATA_CSB5, 0x92, SWKS_100, 0, ATA_UDMA5, "CSB5" }, 80 { ATA_CSB5, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB5" }, 81 { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, 82 { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, 83 { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, 84 { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 85 { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, 86 { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, 87 { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, 88 { ATA_FRODO8, 0x00, SWKS_MIO, 8, ATA_SA150, "Frodo8" }, 89 { 0, 0, 0, 0, 0, 0}}; 90 91 if (pci_get_vendor(dev) != ATA_SERVERWORKS_ID) 92 return ENXIO; 93 94 if (!(ctlr->chip = ata_match_chip(dev, ids))) 95 return ENXIO; 96 97 ata_set_desc(dev); 98 ctlr->chipinit = ata_serverworks_chipinit; 99 return (BUS_PROBE_LOW_PRIORITY); 100 } 101 102 static int 103 ata_serverworks_status(device_t dev) 104 { 105 struct ata_channel *ch = device_get_softc(dev); 106 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 107 108 /* 109 * Check if this interrupt belongs to our channel. 110 */ 111 if (!(ATA_INL(ctlr->r_res2, 0x1f80) & (1 << ch->unit))) 112 return (0); 113 114 /* 115 * We need to do a 4-byte read on the status reg before the values 116 * will report correctly 117 */ 118 119 ATA_IDX_INL(ch,ATA_STATUS); 120 121 return ata_pci_status(dev); 122 } 123 124 static int 125 ata_serverworks_chipinit(device_t dev) 126 { 127 struct ata_pci_controller *ctlr = device_get_softc(dev); 128 129 if (ata_setup_interrupt(dev, ata_generic_intr)) 130 return ENXIO; 131 132 if (ctlr->chip->cfg1 == SWKS_MIO) { 133 ctlr->r_type2 = SYS_RES_MEMORY; 134 ctlr->r_rid2 = PCIR_BAR(5); 135 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2, 136 &ctlr->r_rid2, RF_ACTIVE))) 137 return ENXIO; 138 139 ctlr->channels = ctlr->chip->cfg2; 140 ctlr->ch_attach = ata_serverworks_ch_attach; 141 ctlr->ch_detach = ata_serverworks_ch_detach; 142 ctlr->setmode = ata_sata_setmode; 143 ctlr->getrev = ata_sata_getrev; 144 ctlr->reset = ata_serverworks_sata_reset; 145 return 0; 146 } 147 else if (ctlr->chip->cfg1 == SWKS_33) { 148 device_t *children; 149 int nchildren, i; 150 151 /* locate the ISA part in the southbridge and enable UDMA33 */ 152 if (!device_get_children(device_get_parent(dev), &children,&nchildren)){ 153 for (i = 0; i < nchildren; i++) { 154 if (pci_get_devid(children[i]) == ATA_ROSB4_ISA) { 155 pci_write_config(children[i], 0x64, 156 (pci_read_config(children[i], 0x64, 4) & 157 ~0x00002000) | 0x00004000, 4); 158 break; 159 } 160 } 161 free(children, M_TEMP); 162 } 163 } 164 else { 165 pci_write_config(dev, 0x5a, (pci_read_config(dev, 0x5a, 1) & ~0x40) | 166 ((ctlr->chip->cfg1 == SWKS_100) ? 0x03 : 0x02), 1); 167 } 168 ctlr->setmode = ata_serverworks_setmode; 169 return 0; 170 } 171 172 static int 173 ata_serverworks_ch_attach(device_t dev) 174 { 175 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev)); 176 struct ata_channel *ch = device_get_softc(dev); 177 int ch_offset; 178 int i; 179 180 ch_offset = ch->unit * 0x100; 181 182 for (i = ATA_DATA; i < ATA_MAX_RES; i++) 183 ch->r_io[i].res = ctlr->r_res2; 184 185 /* setup ATA registers */ 186 ch->r_io[ATA_DATA].offset = ch_offset + 0x00; 187 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x04; 188 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08; 189 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c; 190 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10; 191 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14; 192 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18; 193 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1c; 194 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x20; 195 ata_default_registers(dev); 196 197 /* setup DMA registers */ 198 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x30; 199 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x32; 200 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x34; 201 202 /* setup SATA registers */ 203 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x40; 204 ch->r_io[ATA_SERROR].offset = ch_offset + 0x44; 205 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x48; 206 207 ch->flags |= ATA_NO_SLAVE | ATA_SATA | ATA_KNOWN_PRESENCE; 208 ata_pci_hw(dev); 209 ch->hw.tf_read = ata_serverworks_tf_read; 210 ch->hw.tf_write = ata_serverworks_tf_write; 211 212 if (ctlr->chip->chipid == ATA_K2) { 213 /* 214 * Set SICR registers to turn off waiting for a status message 215 * before sending FIS. Values obtained from the Darwin driver. 216 */ 217 218 ATA_OUTL(ctlr->r_res2, ch_offset + 0x80, 219 ATA_INL(ctlr->r_res2, ch_offset + 0x80) & ~0x00040000); 220 ATA_OUTL(ctlr->r_res2, ch_offset + 0x88, 0); 221 222 /* 223 * Some controllers have a bug where they will send the command 224 * to the drive before seeing a DMA start, and then can begin 225 * receiving data before the DMA start arrives. The controller 226 * will then become confused and either corrupt the data or crash. 227 * Remedy this by starting DMA before sending the drive command. 228 */ 229 230 ch->flags |= ATA_DMA_BEFORE_CMD; 231 232 /* 233 * The status register must be read as a long to fill the other 234 * registers. 235 */ 236 237 ch->hw.status = ata_serverworks_status; 238 ch->flags |= ATA_STATUS_IS_LONG; 239 } 240 241 /* chip does not reliably do 64K DMA transfers */ 242 ch->dma.max_iosize = 64 * DEV_BSIZE; 243 244 ata_pci_dmainit(dev); 245 246 return 0; 247 } 248 249 static int 250 ata_serverworks_ch_detach(device_t dev) 251 { 252 253 ata_pci_dmafini(dev); 254 return (0); 255 } 256 257 static void 258 ata_serverworks_tf_read(struct ata_request *request) 259 { 260 struct ata_channel *ch = device_get_softc(request->parent); 261 262 if (request->flags & ATA_R_48BIT) { 263 u_int16_t temp; 264 265 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT); 266 temp = ATA_IDX_INW(ch, ATA_SECTOR); 267 request->u.ata.lba = (u_int64_t)(temp & 0x00ff) | 268 ((u_int64_t)(temp & 0xff00) << 24); 269 temp = ATA_IDX_INW(ch, ATA_CYL_LSB); 270 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 8) | 271 ((u_int64_t)(temp & 0xff00) << 32); 272 temp = ATA_IDX_INW(ch, ATA_CYL_MSB); 273 request->u.ata.lba |= ((u_int64_t)(temp & 0x00ff) << 16) | 274 ((u_int64_t)(temp & 0xff00) << 40); 275 } 276 else { 277 request->u.ata.count = ATA_IDX_INW(ch, ATA_COUNT) & 0x00ff; 278 request->u.ata.lba = (ATA_IDX_INW(ch, ATA_SECTOR) & 0x00ff) | 279 ((ATA_IDX_INW(ch, ATA_CYL_LSB) & 0x00ff) << 8) | 280 ((ATA_IDX_INW(ch, ATA_CYL_MSB) & 0x00ff) << 16) | 281 ((ATA_IDX_INW(ch, ATA_DRIVE) & 0xf) << 24); 282 } 283 } 284 285 static void 286 ata_serverworks_tf_write(struct ata_request *request) 287 { 288 struct ata_channel *ch = device_get_softc(request->parent); 289 290 if (request->flags & ATA_R_48BIT) { 291 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 292 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 293 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) | 294 (request->u.ata.lba & 0x00ff)); 295 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) | 296 ((request->u.ata.lba >> 8) & 0x00ff)); 297 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) | 298 ((request->u.ata.lba >> 16) & 0x00ff)); 299 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit)); 300 } 301 else { 302 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature); 303 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count); 304 ATA_IDX_OUTW(ch, ATA_SECTOR, request->u.ata.lba); 305 ATA_IDX_OUTW(ch, ATA_CYL_LSB, request->u.ata.lba >> 8); 306 ATA_IDX_OUTW(ch, ATA_CYL_MSB, request->u.ata.lba >> 16); 307 ATA_IDX_OUTW(ch, ATA_DRIVE, 308 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) | 309 ((request->u.ata.lba >> 24) & 0x0f)); 310 } 311 } 312 313 static int 314 ata_serverworks_setmode(device_t dev, int target, int mode) 315 { 316 device_t parent = device_get_parent(dev); 317 struct ata_pci_controller *ctlr = device_get_softc(parent); 318 struct ata_channel *ch = device_get_softc(dev); 319 int devno = (ch->unit << 1) + target; 320 int offset = (devno ^ 0x01) << 3; 321 int piomode; 322 static const uint8_t piotimings[] = { 0x5d, 0x47, 0x34, 0x22, 0x20 }; 323 static const uint8_t dmatimings[] = { 0x77, 0x21, 0x20 }; 324 325 mode = min(mode, ctlr->chip->max_dma); 326 if (mode >= ATA_UDMA0) { 327 /* Set UDMA mode, enable UDMA, set WDMA2/PIO4 */ 328 pci_write_config(parent, 0x56, 329 (pci_read_config(parent, 0x56, 2) & 330 ~(0xf << (devno << 2))) | 331 ((mode & ATA_MODE_MASK) << (devno << 2)), 2); 332 pci_write_config(parent, 0x54, 333 pci_read_config(parent, 0x54, 1) | 334 (0x01 << devno), 1); 335 pci_write_config(parent, 0x44, 336 (pci_read_config(parent, 0x44, 4) & 337 ~(0xff << offset)) | 338 (dmatimings[2] << offset), 4); 339 piomode = ATA_PIO4; 340 } else if (mode >= ATA_WDMA0) { 341 /* Disable UDMA, set WDMA mode and timings, calculate PIO. */ 342 pci_write_config(parent, 0x54, 343 pci_read_config(parent, 0x54, 1) & 344 ~(0x01 << devno), 1); 345 pci_write_config(parent, 0x44, 346 (pci_read_config(parent, 0x44, 4) & 347 ~(0xff << offset)) | 348 (dmatimings[mode & ATA_MODE_MASK] << offset), 4); 349 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 : 350 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4; 351 } else { 352 /* Disable UDMA, set requested PIO. */ 353 pci_write_config(parent, 0x54, 354 pci_read_config(parent, 0x54, 1) & 355 ~(0x01 << devno), 1); 356 piomode = mode; 357 } 358 /* Set PIO mode and timings, calculated above. */ 359 if (ctlr->chip->cfg1 != SWKS_33) { 360 pci_write_config(parent, 0x4a, 361 (pci_read_config(parent, 0x4a, 2) & 362 ~(0xf << (devno << 2))) | 363 ((piomode - ATA_PIO0) << (devno<<2)),2); 364 } 365 pci_write_config(parent, 0x40, 366 (pci_read_config(parent, 0x40, 4) & 367 ~(0xff << offset)) | 368 (piotimings[ata_mode2idx(piomode)] << offset), 4); 369 return (mode); 370 } 371 372 static void 373 ata_serverworks_sata_reset(device_t dev) 374 { 375 struct ata_channel *ch = device_get_softc(dev); 376 377 if (ata_sata_phy_reset(dev, -1, 0)) 378 ata_generic_reset(dev); 379 else 380 ch->devices = 0; 381 } 382 383 ATA_DECLARE_DRIVER(ata_serverworks); 384