16e778a7eSPedro F. Giffuni /*- 26e778a7eSPedro F. Giffuni * SPDX-License-Identifier: ISC 36e778a7eSPedro F. Giffuni * 414779705SSam Leffler * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 514779705SSam Leffler * Copyright (c) 2002-2008 Atheros Communications, Inc. 614779705SSam Leffler * 714779705SSam Leffler * Permission to use, copy, modify, and/or distribute this software for any 814779705SSam Leffler * purpose with or without fee is hereby granted, provided that the above 914779705SSam Leffler * copyright notice and this permission notice appear in all copies. 1014779705SSam Leffler * 1114779705SSam Leffler * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 1214779705SSam Leffler * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 1314779705SSam Leffler * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 1414779705SSam Leffler * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 1514779705SSam Leffler * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 1614779705SSam Leffler * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 1714779705SSam Leffler * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 1814779705SSam Leffler */ 1914779705SSam Leffler #ifndef _ATH_AH_DECODE_H_ 2014779705SSam Leffler #define _ATH_AH_DECODE_H_ 2114779705SSam Leffler /* 2214779705SSam Leffler * Register tracing support. 2314779705SSam Leffler * 2414779705SSam Leffler * Setting hw.ath.hal.alq=1 enables tracing of all register reads and 2514779705SSam Leffler * writes to the file /tmp/ath_hal.log. The file format is a simple 2614779705SSam Leffler * fixed-size array of records. When done logging set hw.ath.hal.alq=0 2714779705SSam Leffler * and then decode the file with the arcode program (that is part of the 2814779705SSam Leffler * HAL). If you start+stop tracing the data will be appended to an 2914779705SSam Leffler * existing file. 3014779705SSam Leffler */ 3114779705SSam Leffler struct athregrec { 322fe1131cSAdrian Chadd uint32_t threadid; 3314779705SSam Leffler uint32_t op : 8, 3414779705SSam Leffler reg : 24; 3514779705SSam Leffler uint32_t val; 3614779705SSam Leffler }; 3714779705SSam Leffler 3814779705SSam Leffler enum { 3914779705SSam Leffler OP_READ = 0, /* register read */ 4014779705SSam Leffler OP_WRITE = 1, /* register write */ 4114779705SSam Leffler OP_DEVICE = 2, /* device identification */ 4214779705SSam Leffler OP_MARK = 3, /* application marker */ 4314779705SSam Leffler }; 4414779705SSam Leffler 4514779705SSam Leffler enum { 4614779705SSam Leffler AH_MARK_RESET, /* ar*Reset entry, bChannelChange */ 4714779705SSam Leffler AH_MARK_RESET_LINE, /* ar*_reset.c, line %d */ 4814779705SSam Leffler AH_MARK_RESET_DONE, /* ar*Reset exit, error code */ 4914779705SSam Leffler AH_MARK_CHIPRESET, /* ar*ChipReset, channel num */ 5014779705SSam Leffler AH_MARK_PERCAL, /* ar*PerCalibration, channel num */ 5114779705SSam Leffler AH_MARK_SETCHANNEL, /* ar*SetChannel, channel num */ 5214779705SSam Leffler AH_MARK_ANI_RESET, /* ar*AniReset, opmode */ 5314779705SSam Leffler AH_MARK_ANI_POLL, /* ar*AniReset, listen time */ 5414779705SSam Leffler AH_MARK_ANI_CONTROL, /* ar*AniReset, cmd */ 555e7d0e64SAdrian Chadd AH_MARK_RX_CTL, /* RX DMA control */ 56d77c4024SAdrian Chadd AH_MARK_CHIP_POWER, /* chip power control, mode */ 57d77c4024SAdrian Chadd AH_MARK_CHIP_POWER_DONE, /* chip power control done, status */ 5814779705SSam Leffler }; 595e7d0e64SAdrian Chadd 605e7d0e64SAdrian Chadd enum { 615e7d0e64SAdrian Chadd AH_MARK_RX_CTL_PCU_START, 625e7d0e64SAdrian Chadd AH_MARK_RX_CTL_PCU_STOP, 635e7d0e64SAdrian Chadd AH_MARK_RX_CTL_DMA_START, 645e7d0e64SAdrian Chadd AH_MARK_RX_CTL_DMA_STOP, 655e7d0e64SAdrian Chadd AH_MARK_RX_CTL_DMA_STOP_ERR, 66d77c4024SAdrian Chadd AH_MARK_RX_CTL_DMA_STOP_OK, 675e7d0e64SAdrian Chadd }; 685e7d0e64SAdrian Chadd 6914779705SSam Leffler #endif /* _ATH_AH_DECODE_H_ */ 70