1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2006 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #include "opt_ah.h" 22 23 #include "ah.h" 24 #include "ah_internal.h" 25 #include "ah_desc.h" 26 27 #include "ar5211/ar5211.h" 28 #include "ar5211/ar5211reg.h" 29 #include "ar5211/ar5211desc.h" 30 31 /* 32 * Get the RXDP. 33 */ 34 uint32_t 35 ar5211GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype) 36 { 37 38 HALASSERT(qtype == HAL_RX_QUEUE_HP); 39 return OS_REG_READ(ah, AR_RXDP); 40 } 41 42 /* 43 * Set the RxDP. 44 */ 45 void 46 ar5211SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype) 47 { 48 49 HALASSERT(qtype == HAL_RX_QUEUE_HP); 50 OS_REG_WRITE(ah, AR_RXDP, rxdp); 51 HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp); 52 } 53 54 55 /* 56 * Set Receive Enable bits. 57 */ 58 void 59 ar5211EnableReceive(struct ath_hal *ah) 60 { 61 OS_REG_WRITE(ah, AR_CR, AR_CR_RXE); 62 } 63 64 /* 65 * Stop Receive at the DMA engine 66 */ 67 HAL_BOOL 68 ar5211StopDmaReceive(struct ath_hal *ah) 69 { 70 OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */ 71 if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) { 72 #ifdef AH_DEBUG 73 ath_hal_printf(ah, "%s failed to stop in 10ms\n" 74 "AR_CR=0x%08X\nAR_DIAG_SW=0x%08X\n" 75 , __func__ 76 , OS_REG_READ(ah, AR_CR) 77 , OS_REG_READ(ah, AR_DIAG_SW) 78 ); 79 #endif 80 return AH_FALSE; 81 } else { 82 return AH_TRUE; 83 } 84 } 85 86 /* 87 * Start Transmit at the PCU engine (unpause receive) 88 */ 89 void 90 ar5211StartPcuReceive(struct ath_hal *ah, HAL_BOOL is_scanning) 91 { 92 OS_REG_WRITE(ah, AR_DIAG_SW, 93 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX)); 94 } 95 96 /* 97 * Stop Transmit at the PCU engine (pause receive) 98 */ 99 void 100 ar5211StopPcuReceive(struct ath_hal *ah) 101 { 102 OS_REG_WRITE(ah, AR_DIAG_SW, 103 OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX); 104 } 105 106 /* 107 * Set multicast filter 0 (lower 32-bits) 108 * filter 1 (upper 32-bits) 109 */ 110 void 111 ar5211SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1) 112 { 113 OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0); 114 OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1); 115 } 116 117 /* 118 * Clear multicast filter by index 119 */ 120 HAL_BOOL 121 ar5211ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 122 { 123 uint32_t val; 124 125 if (ix >= 64) 126 return AH_FALSE; 127 if (ix >= 32) { 128 val = OS_REG_READ(ah, AR_MCAST_FIL1); 129 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32)))); 130 } else { 131 val = OS_REG_READ(ah, AR_MCAST_FIL0); 132 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix))); 133 } 134 return AH_TRUE; 135 } 136 137 /* 138 * Set multicast filter by index 139 */ 140 HAL_BOOL 141 ar5211SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix) 142 { 143 uint32_t val; 144 145 if (ix >= 64) 146 return AH_FALSE; 147 if (ix >= 32) { 148 val = OS_REG_READ(ah, AR_MCAST_FIL1); 149 OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32)))); 150 } else { 151 val = OS_REG_READ(ah, AR_MCAST_FIL0); 152 OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix))); 153 } 154 return AH_TRUE; 155 } 156 157 /* 158 * Get receive filter. 159 */ 160 uint32_t 161 ar5211GetRxFilter(struct ath_hal *ah) 162 { 163 return OS_REG_READ(ah, AR_RX_FILTER); 164 } 165 166 /* 167 * Set receive filter. 168 */ 169 void 170 ar5211SetRxFilter(struct ath_hal *ah, uint32_t bits) 171 { 172 OS_REG_WRITE(ah, AR_RX_FILTER, bits); 173 } 174 175 /* 176 * Initialize RX descriptor, by clearing the status and clearing 177 * the size. This is not strictly HW dependent, but we want the 178 * control and status words to be opaque above the hal. 179 */ 180 HAL_BOOL 181 ar5211SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds, 182 uint32_t size, u_int flags) 183 { 184 struct ar5211_desc *ads = AR5211DESC(ds); 185 186 ads->ds_ctl0 = 0; 187 ads->ds_ctl1 = size & AR_BufLen; 188 if (ads->ds_ctl1 != size) { 189 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n", 190 __func__, size); 191 return AH_FALSE; 192 } 193 if (flags & HAL_RXDESC_INTREQ) 194 ads->ds_ctl1 |= AR_RxInterReq; 195 ads->ds_status0 = ads->ds_status1 = 0; 196 197 return AH_TRUE; 198 } 199 200 /* 201 * Process an RX descriptor, and return the status to the caller. 202 * Copy some hardware specific items into the software portion 203 * of the descriptor. 204 * 205 * NB: the caller is responsible for validating the memory contents 206 * of the descriptor (e.g. flushing any cached copy). 207 */ 208 HAL_STATUS 209 ar5211ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds, 210 uint32_t pa, struct ath_desc *nds, uint64_t tsf, 211 struct ath_rx_status *rs) 212 { 213 struct ar5211_desc *ads = AR5211DESC(ds); 214 struct ar5211_desc *ands = AR5211DESC(nds); 215 216 if ((ads->ds_status1 & AR_Done) == 0) 217 return HAL_EINPROGRESS; 218 /* 219 * Given the use of a self-linked tail be very sure that the hw is 220 * done with this descriptor; the hw may have done this descriptor 221 * once and picked it up again...make sure the hw has moved on. 222 */ 223 if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa) 224 return HAL_EINPROGRESS; 225 226 rs->rs_datalen = ads->ds_status0 & AR_DataLen; 227 rs->rs_tstamp = MS(ads->ds_status1, AR_RcvTimestamp); 228 rs->rs_status = 0; 229 if ((ads->ds_status1 & AR_FrmRcvOK) == 0) { 230 if (ads->ds_status1 & AR_CRCErr) 231 rs->rs_status |= HAL_RXERR_CRC; 232 else if (ads->ds_status1 & AR_DecryptCRCErr) 233 rs->rs_status |= HAL_RXERR_DECRYPT; 234 else { 235 rs->rs_status |= HAL_RXERR_PHY; 236 rs->rs_phyerr = MS(ads->ds_status1, AR_PHYErr); 237 } 238 } 239 /* XXX what about KeyCacheMiss? */ 240 rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength); 241 if (ads->ds_status1 & AR_KeyIdxValid) 242 rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx); 243 else 244 rs->rs_keyix = HAL_RXKEYIX_INVALID; 245 /* NB: caller expected to do rate table mapping */ 246 rs->rs_rate = MS(ads->ds_status0, AR_RcvRate); 247 rs->rs_antenna = MS(ads->ds_status0, AR_RcvAntenna); 248 rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0; 249 250 return HAL_OK; 251 } 252