1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting 5 * Copyright (c) 2002-2008 Atheros Communications, Inc. 6 * 7 * Permission to use, copy, modify, and/or distribute this software for any 8 * purpose with or without fee is hereby granted, provided that the above 9 * copyright notice and this permission notice appear in all copies. 10 * 11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 18 * 19 * $FreeBSD$ 20 */ 21 #ifndef _DEV_ATH_AR5212REG_H_ 22 #define _DEV_ATH_AR5212REG_H_ 23 24 /* 25 * Definitions for the Atheros 5212 chipset. 26 */ 27 28 /* DMA Control and Interrupt Registers */ 29 #define AR_CR 0x0008 /* MAC control register */ 30 #define AR_RXDP 0x000C /* MAC receive queue descriptor pointer */ 31 #define AR_CFG 0x0014 /* MAC configuration and status register */ 32 #define AR_IER 0x0024 /* MAC Interrupt enable register */ 33 /* 0x28 is RTSD0 on the 5211 */ 34 /* 0x2c is RTSD1 on the 5211 */ 35 #define AR_TXCFG 0x0030 /* MAC tx DMA size config register */ 36 #define AR_RXCFG 0x0034 /* MAC rx DMA size config register */ 37 /* 0x38 is the jumbo descriptor address on the 5211 */ 38 #define AR_MIBC 0x0040 /* MAC MIB control register */ 39 #define AR_TOPS 0x0044 /* MAC timeout prescale count */ 40 #define AR_RXNPTO 0x0048 /* MAC no frame received timeout */ 41 #define AR_TXNPTO 0x004C /* MAC no frame trasmitted timeout */ 42 #define AR_RPGTO 0x0050 /* MAC receive frame gap timeout */ 43 #define AR_RPCNT 0x0054 /* MAC receive frame count limit */ 44 #define AR_MACMISC 0x0058 /* MAC miscellaneous control/status register */ 45 #define AR_SPC_0 0x005c /* MAC sleep performance (awake cycles) */ 46 #define AR_SPC_1 0x0060 /* MAC sleep performance (asleep cycles) */ 47 /* 0x5c is for QCU/DCU clock gating control on 5311 */ 48 #define AR_ISR 0x0080 /* MAC Primary interrupt status register */ 49 #define AR_ISR_S0 0x0084 /* MAC Secondary interrupt status register 0 */ 50 #define AR_ISR_S1 0x0088 /* MAC Secondary interrupt status register 1 */ 51 #define AR_ISR_S2 0x008c /* MAC Secondary interrupt status register 2 */ 52 #define AR_ISR_S3 0x0090 /* MAC Secondary interrupt status register 3 */ 53 #define AR_ISR_S4 0x0094 /* MAC Secondary interrupt status register 4 */ 54 #define AR_IMR 0x00a0 /* MAC Primary interrupt mask register */ 55 #define AR_IMR_S0 0x00a4 /* MAC Secondary interrupt mask register 0 */ 56 #define AR_IMR_S1 0x00a8 /* MAC Secondary interrupt mask register 1 */ 57 #define AR_IMR_S2 0x00ac /* MAC Secondary interrupt mask register 2 */ 58 #define AR_IMR_S3 0x00b0 /* MAC Secondary interrupt mask register 3 */ 59 #define AR_IMR_S4 0x00b4 /* MAC Secondary interrupt mask register 4 */ 60 #define AR_ISR_RAC 0x00c0 /* ISR read-and-clear access */ 61 /* Shadow copies with read-and-clear access */ 62 #define AR_ISR_S0_S 0x00c4 /* ISR_S0 shadow copy */ 63 #define AR_ISR_S1_S 0x00c8 /* ISR_S1 shadow copy */ 64 #define AR_ISR_S2_S 0x00cc /* ISR_S2 shadow copy */ 65 #define AR_ISR_S3_S 0x00d0 /* ISR_S3 shadow copy */ 66 #define AR_ISR_S4_S 0x00d4 /* ISR_S4 shadow copy */ 67 #define AR_DMADBG_0 0x00e0 /* DMA debug 0 */ 68 #define AR_DMADBG_1 0x00e4 /* DMA debug 1 */ 69 #define AR_DMADBG_2 0x00e8 /* DMA debug 2 */ 70 #define AR_DMADBG_3 0x00ec /* DMA debug 3 */ 71 #define AR_DMADBG_4 0x00f0 /* DMA debug 4 */ 72 #define AR_DMADBG_5 0x00f4 /* DMA debug 5 */ 73 #define AR_DMADBG_6 0x00f8 /* DMA debug 6 */ 74 #define AR_DMADBG_7 0x00fc /* DMA debug 7 */ 75 #define AR_DCM_A 0x0400 /* Decompression mask address */ 76 #define AR_DCM_D 0x0404 /* Decompression mask data */ 77 #define AR_DCCFG 0x0420 /* Decompression configuration */ 78 #define AR_CCFG 0x0600 /* Compression configuration */ 79 #define AR_CCUCFG 0x0604 /* Compression catchup configuration */ 80 #define AR_CPC_0 0x0610 /* Compression performance counter 0 */ 81 #define AR_CPC_1 0x0614 /* Compression performance counter 1 */ 82 #define AR_CPC_2 0x0618 /* Compression performance counter 2 */ 83 #define AR_CPC_3 0x061c /* Compression performance counter 3 */ 84 #define AR_CPCOVF 0x0620 /* Compression performance overflow status */ 85 86 #define AR_Q0_TXDP 0x0800 /* MAC Transmit Queue descriptor pointer */ 87 #define AR_Q1_TXDP 0x0804 /* MAC Transmit Queue descriptor pointer */ 88 #define AR_Q2_TXDP 0x0808 /* MAC Transmit Queue descriptor pointer */ 89 #define AR_Q3_TXDP 0x080c /* MAC Transmit Queue descriptor pointer */ 90 #define AR_Q4_TXDP 0x0810 /* MAC Transmit Queue descriptor pointer */ 91 #define AR_Q5_TXDP 0x0814 /* MAC Transmit Queue descriptor pointer */ 92 #define AR_Q6_TXDP 0x0818 /* MAC Transmit Queue descriptor pointer */ 93 #define AR_Q7_TXDP 0x081c /* MAC Transmit Queue descriptor pointer */ 94 #define AR_Q8_TXDP 0x0820 /* MAC Transmit Queue descriptor pointer */ 95 #define AR_Q9_TXDP 0x0824 /* MAC Transmit Queue descriptor pointer */ 96 #define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 97 98 #define AR_Q_TXE 0x0840 /* MAC Transmit Queue enable */ 99 #define AR_Q_TXE_M 0x000003FF /* Mask for TXE (QCU 0-9) */ 100 #define AR_Q_TXD 0x0880 /* MAC Transmit Queue disable */ 101 #define AR_Q_TXD_M 0x000003FF /* Mask for TXD (QCU 0-9) */ 102 103 #define AR_Q0_CBRCFG 0x08c0 /* MAC CBR configuration */ 104 #define AR_Q1_CBRCFG 0x08c4 /* MAC CBR configuration */ 105 #define AR_Q2_CBRCFG 0x08c8 /* MAC CBR configuration */ 106 #define AR_Q3_CBRCFG 0x08cc /* MAC CBR configuration */ 107 #define AR_Q4_CBRCFG 0x08d0 /* MAC CBR configuration */ 108 #define AR_Q5_CBRCFG 0x08d4 /* MAC CBR configuration */ 109 #define AR_Q6_CBRCFG 0x08d8 /* MAC CBR configuration */ 110 #define AR_Q7_CBRCFG 0x08dc /* MAC CBR configuration */ 111 #define AR_Q8_CBRCFG 0x08e0 /* MAC CBR configuration */ 112 #define AR_Q9_CBRCFG 0x08e4 /* MAC CBR configuration */ 113 #define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 114 115 #define AR_Q0_RDYTIMECFG 0x0900 /* MAC ReadyTime configuration */ 116 #define AR_Q1_RDYTIMECFG 0x0904 /* MAC ReadyTime configuration */ 117 #define AR_Q2_RDYTIMECFG 0x0908 /* MAC ReadyTime configuration */ 118 #define AR_Q3_RDYTIMECFG 0x090c /* MAC ReadyTime configuration */ 119 #define AR_Q4_RDYTIMECFG 0x0910 /* MAC ReadyTime configuration */ 120 #define AR_Q5_RDYTIMECFG 0x0914 /* MAC ReadyTime configuration */ 121 #define AR_Q6_RDYTIMECFG 0x0918 /* MAC ReadyTime configuration */ 122 #define AR_Q7_RDYTIMECFG 0x091c /* MAC ReadyTime configuration */ 123 #define AR_Q8_RDYTIMECFG 0x0920 /* MAC ReadyTime configuration */ 124 #define AR_Q9_RDYTIMECFG 0x0924 /* MAC ReadyTime configuration */ 125 #define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 126 127 #define AR_Q_ONESHOTARM_SC 0x0940 /* MAC OneShotArm set control */ 128 #define AR_Q_ONESHOTARM_CC 0x0980 /* MAC OneShotArm clear control */ 129 130 #define AR_Q0_MISC 0x09c0 /* MAC Miscellaneous QCU settings */ 131 #define AR_Q1_MISC 0x09c4 /* MAC Miscellaneous QCU settings */ 132 #define AR_Q2_MISC 0x09c8 /* MAC Miscellaneous QCU settings */ 133 #define AR_Q3_MISC 0x09cc /* MAC Miscellaneous QCU settings */ 134 #define AR_Q4_MISC 0x09d0 /* MAC Miscellaneous QCU settings */ 135 #define AR_Q5_MISC 0x09d4 /* MAC Miscellaneous QCU settings */ 136 #define AR_Q6_MISC 0x09d8 /* MAC Miscellaneous QCU settings */ 137 #define AR_Q7_MISC 0x09dc /* MAC Miscellaneous QCU settings */ 138 #define AR_Q8_MISC 0x09e0 /* MAC Miscellaneous QCU settings */ 139 #define AR_Q9_MISC 0x09e4 /* MAC Miscellaneous QCU settings */ 140 #define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 141 142 #define AR_Q0_STS 0x0a00 /* MAC Miscellaneous QCU status */ 143 #define AR_Q1_STS 0x0a04 /* MAC Miscellaneous QCU status */ 144 #define AR_Q2_STS 0x0a08 /* MAC Miscellaneous QCU status */ 145 #define AR_Q3_STS 0x0a0c /* MAC Miscellaneous QCU status */ 146 #define AR_Q4_STS 0x0a10 /* MAC Miscellaneous QCU status */ 147 #define AR_Q5_STS 0x0a14 /* MAC Miscellaneous QCU status */ 148 #define AR_Q6_STS 0x0a18 /* MAC Miscellaneous QCU status */ 149 #define AR_Q7_STS 0x0a1c /* MAC Miscellaneous QCU status */ 150 #define AR_Q8_STS 0x0a20 /* MAC Miscellaneous QCU status */ 151 #define AR_Q9_STS 0x0a24 /* MAC Miscellaneous QCU status */ 152 #define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 153 154 #define AR_Q_RDYTIMESHDN 0x0a40 /* MAC ReadyTimeShutdown status */ 155 #define AR_Q_CBBS 0xb00 /* Compression buffer base select */ 156 #define AR_Q_CBBA 0xb04 /* Compression buffer base access */ 157 #define AR_Q_CBC 0xb08 /* Compression buffer configuration */ 158 159 #define AR_D0_QCUMASK 0x1000 /* MAC QCU Mask */ 160 #define AR_D1_QCUMASK 0x1004 /* MAC QCU Mask */ 161 #define AR_D2_QCUMASK 0x1008 /* MAC QCU Mask */ 162 #define AR_D3_QCUMASK 0x100c /* MAC QCU Mask */ 163 #define AR_D4_QCUMASK 0x1010 /* MAC QCU Mask */ 164 #define AR_D5_QCUMASK 0x1014 /* MAC QCU Mask */ 165 #define AR_D6_QCUMASK 0x1018 /* MAC QCU Mask */ 166 #define AR_D7_QCUMASK 0x101c /* MAC QCU Mask */ 167 #define AR_D8_QCUMASK 0x1020 /* MAC QCU Mask */ 168 #define AR_D9_QCUMASK 0x1024 /* MAC QCU Mask */ 169 #define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 170 171 #define AR_D0_LCL_IFS 0x1040 /* MAC DCU-specific IFS settings */ 172 #define AR_D1_LCL_IFS 0x1044 /* MAC DCU-specific IFS settings */ 173 #define AR_D2_LCL_IFS 0x1048 /* MAC DCU-specific IFS settings */ 174 #define AR_D3_LCL_IFS 0x104c /* MAC DCU-specific IFS settings */ 175 #define AR_D4_LCL_IFS 0x1050 /* MAC DCU-specific IFS settings */ 176 #define AR_D5_LCL_IFS 0x1054 /* MAC DCU-specific IFS settings */ 177 #define AR_D6_LCL_IFS 0x1058 /* MAC DCU-specific IFS settings */ 178 #define AR_D7_LCL_IFS 0x105c /* MAC DCU-specific IFS settings */ 179 #define AR_D8_LCL_IFS 0x1060 /* MAC DCU-specific IFS settings */ 180 #define AR_D9_LCL_IFS 0x1064 /* MAC DCU-specific IFS settings */ 181 #define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 182 183 #define AR_D0_RETRY_LIMIT 0x1080 /* MAC Retry limits */ 184 #define AR_D1_RETRY_LIMIT 0x1084 /* MAC Retry limits */ 185 #define AR_D2_RETRY_LIMIT 0x1088 /* MAC Retry limits */ 186 #define AR_D3_RETRY_LIMIT 0x108c /* MAC Retry limits */ 187 #define AR_D4_RETRY_LIMIT 0x1090 /* MAC Retry limits */ 188 #define AR_D5_RETRY_LIMIT 0x1094 /* MAC Retry limits */ 189 #define AR_D6_RETRY_LIMIT 0x1098 /* MAC Retry limits */ 190 #define AR_D7_RETRY_LIMIT 0x109c /* MAC Retry limits */ 191 #define AR_D8_RETRY_LIMIT 0x10a0 /* MAC Retry limits */ 192 #define AR_D9_RETRY_LIMIT 0x10a4 /* MAC Retry limits */ 193 #define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 194 195 #define AR_D0_CHNTIME 0x10c0 /* MAC ChannelTime settings */ 196 #define AR_D1_CHNTIME 0x10c4 /* MAC ChannelTime settings */ 197 #define AR_D2_CHNTIME 0x10c8 /* MAC ChannelTime settings */ 198 #define AR_D3_CHNTIME 0x10cc /* MAC ChannelTime settings */ 199 #define AR_D4_CHNTIME 0x10d0 /* MAC ChannelTime settings */ 200 #define AR_D5_CHNTIME 0x10d4 /* MAC ChannelTime settings */ 201 #define AR_D6_CHNTIME 0x10d8 /* MAC ChannelTime settings */ 202 #define AR_D7_CHNTIME 0x10dc /* MAC ChannelTime settings */ 203 #define AR_D8_CHNTIME 0x10e0 /* MAC ChannelTime settings */ 204 #define AR_D9_CHNTIME 0x10e4 /* MAC ChannelTime settings */ 205 #define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 206 207 #define AR_D0_MISC 0x1100 /* MAC Miscellaneous DCU-specific settings */ 208 #define AR_D1_MISC 0x1104 /* MAC Miscellaneous DCU-specific settings */ 209 #define AR_D2_MISC 0x1108 /* MAC Miscellaneous DCU-specific settings */ 210 #define AR_D3_MISC 0x110c /* MAC Miscellaneous DCU-specific settings */ 211 #define AR_D4_MISC 0x1110 /* MAC Miscellaneous DCU-specific settings */ 212 #define AR_D5_MISC 0x1114 /* MAC Miscellaneous DCU-specific settings */ 213 #define AR_D6_MISC 0x1118 /* MAC Miscellaneous DCU-specific settings */ 214 #define AR_D7_MISC 0x111c /* MAC Miscellaneous DCU-specific settings */ 215 #define AR_D8_MISC 0x1120 /* MAC Miscellaneous DCU-specific settings */ 216 #define AR_D9_MISC 0x1124 /* MAC Miscellaneous DCU-specific settings */ 217 #define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 218 219 #define AR_D_SEQNUM 0x1140 /* MAC Frame sequence number */ 220 221 /* MAC DCU-global IFS settings */ 222 #define AR_D_GBL_IFS_SIFS 0x1030 /* DCU global SIFS settings */ 223 #define AR_D_GBL_IFS_SLOT 0x1070 /* DC global slot interval */ 224 #define AR_D_GBL_IFS_EIFS 0x10b0 /* DCU global EIFS setting */ 225 #define AR_D_GBL_IFS_MISC 0x10f0 /* DCU global misc. IFS settings */ 226 #define AR_D_FPCTL 0x1230 /* DCU frame prefetch settings */ 227 #define AR_D_TXPSE 0x1270 /* DCU transmit pause control/status */ 228 #define AR_D_TXBLK_CMD 0x1038 /* DCU transmit filter cmd (w/only) */ 229 #define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) /* DCU transmit filter data */ 230 #define AR_D_TXBLK_CLR 0x143c /* DCU clear tx filter (w/only) */ 231 #define AR_D_TXBLK_SET 0x147c /* DCU set tx filter (w/only) */ 232 233 #define AR_RC 0x4000 /* Warm reset control register */ 234 #define AR_SCR 0x4004 /* Sleep control register */ 235 #define AR_INTPEND 0x4008 /* Interrupt Pending register */ 236 #define AR_SFR 0x400C /* Sleep force register */ 237 #define AR_PCICFG 0x4010 /* PCI configuration register */ 238 #define AR_GPIOCR 0x4014 /* GPIO control register */ 239 #define AR_GPIODO 0x4018 /* GPIO data output access register */ 240 #define AR_GPIODI 0x401C /* GPIO data input access register */ 241 #define AR_SREV 0x4020 /* Silicon Revision register */ 242 #define AR_TXEPOST 0x4028 /* TXE write posting resgister */ 243 #define AR_QSM 0x402C /* QCU sleep mask */ 244 245 #define AR_PCIE_PMC 0x4068 /* PCIe power mgt config and status register */ 246 #define AR_PCIE_SERDES 0x4080 /* PCIe Serdes register */ 247 #define AR_PCIE_SERDES2 0x4084 /* PCIe Serdes register */ 248 249 #define AR_EEPROM_ADDR 0x6000 /* EEPROM address register (10 bit) */ 250 #define AR_EEPROM_DATA 0x6004 /* EEPROM data register (16 bit) */ 251 #define AR_EEPROM_CMD 0x6008 /* EEPROM command register */ 252 #define AR_EEPROM_STS 0x600c /* EEPROM status register */ 253 #define AR_EEPROM_CFG 0x6010 /* EEPROM configuration register */ 254 255 #define AR_STA_ID0 0x8000 /* MAC station ID0 register - low 32 bits */ 256 #define AR_STA_ID1 0x8004 /* MAC station ID1 register - upper 16 bits */ 257 #define AR_BSS_ID0 0x8008 /* MAC BSSID low 32 bits */ 258 #define AR_BSS_ID1 0x800C /* MAC BSSID upper 16 bits / AID */ 259 #define AR_SLOT_TIME 0x8010 /* MAC Time-out after a collision */ 260 #define AR_TIME_OUT 0x8014 /* MAC ACK & CTS time-out */ 261 #define AR_RSSI_THR 0x8018 /* MAC RSSI warning & missed beacon threshold */ 262 #define AR_USEC 0x801c /* MAC transmit latency register */ 263 #define AR_BEACON 0x8020 /* MAC beacon control value/mode bits */ 264 #define AR_CFP_PERIOD 0x8024 /* MAC CFP Interval (TU/msec) */ 265 #define AR_TIMER0 0x8028 /* MAC Next beacon time (TU/msec) */ 266 #define AR_TIMER1 0x802c /* MAC DMA beacon alert time (1/8 TU) */ 267 #define AR_TIMER2 0x8030 /* MAC Software beacon alert (1/8 TU) */ 268 #define AR_TIMER3 0x8034 /* MAC ATIM window time */ 269 #define AR_CFP_DUR 0x8038 /* MAC maximum CFP duration in TU */ 270 #define AR_RX_FILTER 0x803C /* MAC receive filter register */ 271 #define AR_MCAST_FIL0 0x8040 /* MAC multicast filter lower 32 bits */ 272 #define AR_MCAST_FIL1 0x8044 /* MAC multicast filter upper 32 bits */ 273 #define AR_DIAG_SW 0x8048 /* MAC PCU control register */ 274 #define AR_TSF_L32 0x804c /* MAC local clock lower 32 bits */ 275 #define AR_TSF_U32 0x8050 /* MAC local clock upper 32 bits */ 276 #define AR_TST_ADDAC 0x8054 /* ADDAC test register */ 277 #define AR_DEF_ANTENNA 0x8058 /* default antenna register */ 278 #define AR_QOS_MASK 0x805c /* MAC AES mute mask: QoS field */ 279 #define AR_SEQ_MASK 0x8060 /* MAC AES mute mask: seqnum field */ 280 #define AR_OBSERV_2 0x8068 /* Observation bus 2 */ 281 #define AR_OBSERV_1 0x806c /* Observation bus 1 */ 282 283 #define AR_LAST_TSTP 0x8080 /* MAC Time stamp of the last beacon received */ 284 #define AR_NAV 0x8084 /* MAC current NAV value */ 285 #define AR_RTS_OK 0x8088 /* MAC RTS exchange success counter */ 286 #define AR_RTS_FAIL 0x808c /* MAC RTS exchange failure counter */ 287 #define AR_ACK_FAIL 0x8090 /* MAC ACK failure counter */ 288 #define AR_FCS_FAIL 0x8094 /* FCS check failure counter */ 289 #define AR_BEACON_CNT 0x8098 /* Valid beacon counter */ 290 291 #define AR_SLEEP1 0x80d4 /* Enhanced sleep control 1 */ 292 #define AR_SLEEP2 0x80d8 /* Enhanced sleep control 2 */ 293 #define AR_SLEEP3 0x80dc /* Enhanced sleep control 3 */ 294 #define AR_BSSMSKL 0x80e0 /* BSSID mask lower 32 bits */ 295 #define AR_BSSMSKU 0x80e4 /* BSSID mask upper 16 bits */ 296 #define AR_TPC 0x80e8 /* Transmit power control for self gen frames */ 297 #define AR_TFCNT 0x80ec /* Profile count, transmit frames */ 298 #define AR_RFCNT 0x80f0 /* Profile count, receive frames */ 299 #define AR_RCCNT 0x80f4 /* Profile count, receive clear */ 300 #define AR_CCCNT 0x80f8 /* Profile count, cycle counter */ 301 302 #define AR_QUIET1 0x80fc /* Quiet time programming for TGh */ 303 #define AR_QUIET1_NEXT_QUIET_S 0 /* TSF of next quiet period (TU) */ 304 #define AR_QUIET1_NEXT_QUIET 0xffff 305 #define AR_QUIET1_QUIET_ENABLE 0x10000 /* Enable Quiet time operation */ 306 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x20000 /* Do we ack/cts during quiet period */ 307 #define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 308 309 #define AR_QUIET2 0x8100 /* More Quiet time programming */ 310 #define AR_QUIET2_QUIET_PER_S 0 /* Periodicity of quiet period (TU) */ 311 #define AR_QUIET2_QUIET_PER 0xffff 312 #define AR_QUIET2_QUIET_DUR_S 16 /* Duration of quiet period (TU) */ 313 #define AR_QUIET2_QUIET_DUR 0xffff0000 314 315 #define AR_TSF_PARM 0x8104 /* TSF parameters */ 316 #define AR_NOACK 0x8108 /* No ack policy in QoS Control Field */ 317 #define AR_PHY_ERR 0x810c /* Phy error filter */ 318 319 #define AR_QOS_CONTROL 0x8118 /* Control TKIP MIC for QoS */ 320 #define AR_QOS_SELECT 0x811c /* MIC QoS select */ 321 #define AR_MISC_MODE 0x8120 /* PCU Misc. mode control */ 322 323 /* Hainan MIB counter registers */ 324 #define AR_FILTOFDM 0x8124 /* Count of filtered OFDM frames */ 325 #define AR_FILTCCK 0x8128 /* Count of filtered CCK frames */ 326 #define AR_PHYCNT1 0x812c /* Phy Error 1 counter */ 327 #define AR_PHYCNTMASK1 0x8130 /* Phy Error 1 counter mask */ 328 #define AR_PHYCNT2 0x8134 /* Phy Error 2 counter */ 329 #define AR_PHYCNTMASK2 0x8138 /* Phy Error 2 counter mask */ 330 #define AR_PHY_COUNTMAX (3 << 22) /* Max value in counter before intr */ 331 #define AR_MIBCNT_INTRMASK (3<<22) /* Mask for top two bits of counters */ 332 333 #define AR_RATE_DURATION_0 0x8700 /* base of multi-rate retry */ 334 #define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 335 336 #define AR_KEYTABLE_0 0x8800 /* MAC Key Cache */ 337 #define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 338 339 #define AR_CFP_MASK 0x0000ffff /* Mask for next beacon time */ 340 341 #define AR_CR_RXE 0x00000004 /* Receive enable */ 342 #define AR_CR_RXD 0x00000020 /* Receive disable */ 343 #define AR_CR_SWI 0x00000040 /* One-shot software interrupt */ 344 345 #define AR_CFG_SWTD 0x00000001 /* byteswap tx descriptor words */ 346 #define AR_CFG_SWTB 0x00000002 /* byteswap tx data buffer words */ 347 #define AR_CFG_SWRD 0x00000004 /* byteswap rx descriptor words */ 348 #define AR_CFG_SWRB 0x00000008 /* byteswap rx data buffer words */ 349 #define AR_CFG_SWRG 0x00000010 /* byteswap register access data words */ 350 #define AR_CFG_AP_ADHOC_INDICATION 0x00000020 /* AP/adhoc indication (0-AP, 1-Adhoc) */ 351 #define AR_CFG_PHOK 0x00000100 /* PHY OK status */ 352 #define AR_CFG_EEBS 0x00000200 /* EEPROM busy */ 353 #define AR_5211_CFG_CLK_GATE_DIS 0x00000400 /* Clock gating disable (Oahu only) */ 354 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 /* Mask of PCI core master request queue full threshold */ 355 #define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 /* Shift for PCI core master request queue full threshold */ 356 357 #define AR_IER_ENABLE 0x00000001 /* Global interrupt enable */ 358 #define AR_IER_DISABLE 0x00000000 /* Global interrupt disable */ 359 360 #define AR_DMASIZE_4B 0x00000000 /* DMA size 4 bytes (TXCFG + RXCFG) */ 361 #define AR_DMASIZE_8B 0x00000001 /* DMA size 8 bytes */ 362 #define AR_DMASIZE_16B 0x00000002 /* DMA size 16 bytes */ 363 #define AR_DMASIZE_32B 0x00000003 /* DMA size 32 bytes */ 364 #define AR_DMASIZE_64B 0x00000004 /* DMA size 64 bytes */ 365 #define AR_DMASIZE_128B 0x00000005 /* DMA size 128 bytes */ 366 #define AR_DMASIZE_256B 0x00000006 /* DMA size 256 bytes */ 367 #define AR_DMASIZE_512B 0x00000007 /* DMA size 512 bytes */ 368 369 #define AR_FTRIG 0x000003F0 /* Mask for Frame trigger level */ 370 #define AR_FTRIG_S 4 /* Shift for Frame trigger level */ 371 #define AR_FTRIG_IMMED 0x00000000 /* bytes in PCU TX FIFO before air */ 372 #define AR_FTRIG_64B 0x00000010 /* default */ 373 #define AR_FTRIG_128B 0x00000020 374 #define AR_FTRIG_192B 0x00000030 375 #define AR_FTRIG_256B 0x00000040 /* 5 bits total */ 376 377 #define AR_RXCFG_ZLFDMA 0x00000010 /* Enable DMA of zero-length frame */ 378 379 #define AR_MIBC_COW 0x00000001 /* counter overflow warning */ 380 #define AR_MIBC_FMC 0x00000002 /* freeze MIB counters */ 381 #define AR_MIBC_CMC 0x00000004 /* clear MIB counters */ 382 #define AR_MIBC_MCS 0x00000008 /* MIB counter strobe, increment all */ 383 384 #define AR_TOPS_MASK 0x0000FFFF /* Mask for timeout prescale */ 385 386 #define AR_RXNPTO_MASK 0x000003FF /* Mask for no frame received timeout */ 387 388 #define AR_TXNPTO_MASK 0x000003FF /* Mask for no frame transmitted timeout */ 389 #define AR_TXNPTO_QCU_MASK 0x000FFC00 /* Mask indicating the set of QCUs */ 390 /* for which frame completions will cause */ 391 /* a reset of the no frame xmit'd timeout */ 392 393 #define AR_RPGTO_MASK 0x000003FF /* Mask for receive frame gap timeout */ 394 395 #define AR_RPCNT_MASK 0x0000001F /* Mask for receive frame count limit */ 396 397 #define AR_MACMISC_DMA_OBS 0x000001E0 /* Mask for DMA observation bus mux select */ 398 #define AR_MACMISC_DMA_OBS_S 5 /* Shift for DMA observation bus mux select */ 399 #define AR_MACMISC_MISC_OBS 0x00000E00 /* Mask for MISC observation bus mux select */ 400 #define AR_MACMISC_MISC_OBS_S 9 /* Shift for MISC observation bus mux select */ 401 #define AR_MACMISC_MAC_OBS_BUS_LSB 0x00007000 /* Mask for MAC observation bus mux select (lsb) */ 402 #define AR_MACMISC_MAC_OBS_BUS_LSB_S 12 /* Shift for MAC observation bus mux select (lsb) */ 403 #define AR_MACMISC_MAC_OBS_BUS_MSB 0x00038000 /* Mask for MAC observation bus mux select (msb) */ 404 #define AR_MACMISC_MAC_OBS_BUS_MSB_S 15 /* Shift for MAC observation bus mux select (msb) */ 405 406 /* 407 * Interrupt Status Registers 408 * 409 * Only the bits in the ISR_P register and the IMR_P registers 410 * control whether the MAC's INTA# output is asserted. The bits in 411 * the secondary interrupt status/mask registers control what bits 412 * are set in the primary interrupt status register; however the 413 * IMR_S* registers DO NOT determine whether INTA# is asserted. 414 * That is INTA# is asserted only when the logical AND of ISR_P 415 * and IMR_P is non-zero. The secondary interrupt mask/status 416 * registers affect what bits are set in ISR_P but they do not 417 * directly affect whether INTA# is asserted. 418 */ 419 #define AR_ISR_RXOK 0x00000001 /* At least one frame received sans errors */ 420 #define AR_ISR_RXDESC 0x00000002 /* Receive interrupt request */ 421 #define AR_ISR_RXERR 0x00000004 /* Receive error interrupt */ 422 #define AR_ISR_RXNOPKT 0x00000008 /* No frame received within timeout clock */ 423 #define AR_ISR_RXEOL 0x00000010 /* Received descriptor empty interrupt */ 424 #define AR_ISR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */ 425 #define AR_ISR_TXOK 0x00000040 /* Transmit okay interrupt */ 426 #define AR_ISR_TXDESC 0x00000080 /* Transmit interrupt request */ 427 #define AR_ISR_TXERR 0x00000100 /* Transmit error interrupt */ 428 #define AR_ISR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */ 429 #define AR_ISR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */ 430 #define AR_ISR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */ 431 #define AR_ISR_MIB 0x00001000 /* MIB interrupt - see MIBC */ 432 #define AR_ISR_SWI 0x00002000 /* Software interrupt */ 433 #define AR_ISR_RXPHY 0x00004000 /* PHY receive error interrupt */ 434 #define AR_ISR_RXKCM 0x00008000 /* Key-cache miss interrupt */ 435 #define AR_ISR_SWBA 0x00010000 /* Software beacon alert interrupt */ 436 #define AR_ISR_BRSSI 0x00020000 /* Beacon threshold interrupt */ 437 #define AR_ISR_BMISS 0x00040000 /* Beacon missed interrupt */ 438 #define AR_ISR_HIUERR 0x00080000 /* An unexpected bus error has occurred */ 439 #define AR_ISR_BNR 0x00100000 /* Beacon not ready interrupt */ 440 #define AR_ISR_RXCHIRP 0x00200000 /* Phy received a 'chirp' */ 441 #define AR_ISR_RXDOPPL 0x00400000 /* Phy received a 'doppler chirp' */ 442 #define AR_ISR_BCNMISC 0x00800000 /* 'or' of TIM, CABEND, DTIMSYNC, BCNTO, 443 CABTO, DTIM bits from ISR_S2 */ 444 #define AR_ISR_TIM 0x00800000 /* TIM interrupt */ 445 #define AR_ISR_GPIO 0x01000000 /* GPIO Interrupt */ 446 #define AR_ISR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */ 447 #define AR_ISR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */ 448 #define AR_ISR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */ 449 #define AR_ISR_RESV0 0xF0000000 /* Reserved */ 450 451 #define AR_ISR_S0_QCU_TXOK 0x000003FF /* Mask for TXOK (QCU 0-9) */ 452 #define AR_ISR_S0_QCU_TXOK_S 0 453 #define AR_ISR_S0_QCU_TXDESC 0x03FF0000 /* Mask for TXDESC (QCU 0-9) */ 454 #define AR_ISR_S0_QCU_TXDESC_S 16 455 456 #define AR_ISR_S1_QCU_TXERR 0x000003FF /* Mask for TXERR (QCU 0-9) */ 457 #define AR_ISR_S1_QCU_TXERR_S 0 458 #define AR_ISR_S1_QCU_TXEOL 0x03FF0000 /* Mask for TXEOL (QCU 0-9) */ 459 #define AR_ISR_S1_QCU_TXEOL_S 16 460 461 #define AR_ISR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */ 462 #define AR_ISR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */ 463 #define AR_ISR_S2_SSERR 0x00020000 /* SERR interrupt */ 464 #define AR_ISR_S2_DPERR 0x00040000 /* PCI bus parity error */ 465 #define AR_ISR_S2_TIM 0x01000000 /* TIM */ 466 #define AR_ISR_S2_CABEND 0x02000000 /* CABEND */ 467 #define AR_ISR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */ 468 #define AR_ISR_S2_BCNTO 0x08000000 /* BCNTO */ 469 #define AR_ISR_S2_CABTO 0x10000000 /* CABTO */ 470 #define AR_ISR_S2_DTIM 0x20000000 /* DTIM */ 471 #define AR_ISR_S2_TSFOOR 0x40000000 /* TSF OOR */ 472 #define AR_ISR_S2_TBTT 0x80000000 /* TBTT timer */ 473 474 #define AR_ISR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 475 #define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 476 477 #define AR_ISR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 478 #define AR_ISR_S4_RESV0 0xFFFFFC00 /* Reserved */ 479 480 /* 481 * Interrupt Mask Registers 482 * 483 * Only the bits in the IMR control whether the MAC's INTA# 484 * output will be asserted. The bits in the secondary interrupt 485 * mask registers control what bits get set in the primary 486 * interrupt status register; however the IMR_S* registers 487 * DO NOT determine whether INTA# is asserted. 488 */ 489 #define AR_IMR_RXOK 0x00000001 /* At least one frame received sans errors */ 490 #define AR_IMR_RXDESC 0x00000002 /* Receive interrupt request */ 491 #define AR_IMR_RXERR 0x00000004 /* Receive error interrupt */ 492 #define AR_IMR_RXNOPKT 0x00000008 /* No frame received within timeout clock */ 493 #define AR_IMR_RXEOL 0x00000010 /* Received descriptor empty interrupt */ 494 #define AR_IMR_RXORN 0x00000020 /* Receive FIFO overrun interrupt */ 495 #define AR_IMR_TXOK 0x00000040 /* Transmit okay interrupt */ 496 #define AR_IMR_TXDESC 0x00000080 /* Transmit interrupt request */ 497 #define AR_IMR_TXERR 0x00000100 /* Transmit error interrupt */ 498 #define AR_IMR_TXNOPKT 0x00000200 /* No frame transmitted interrupt */ 499 #define AR_IMR_TXEOL 0x00000400 /* Transmit descriptor empty interrupt */ 500 #define AR_IMR_TXURN 0x00000800 /* Transmit FIFO underrun interrupt */ 501 #define AR_IMR_MIB 0x00001000 /* MIB interrupt - see MIBC */ 502 #define AR_IMR_SWI 0x00002000 /* Software interrupt */ 503 #define AR_IMR_RXPHY 0x00004000 /* PHY receive error interrupt */ 504 #define AR_IMR_RXKCM 0x00008000 /* Key-cache miss interrupt */ 505 #define AR_IMR_SWBA 0x00010000 /* Software beacon alert interrupt */ 506 #define AR_IMR_BRSSI 0x00020000 /* Beacon threshold interrupt */ 507 #define AR_IMR_BMISS 0x00040000 /* Beacon missed interrupt */ 508 #define AR_IMR_HIUERR 0x00080000 /* An unexpected bus error has occurred */ 509 #define AR_IMR_BNR 0x00100000 /* BNR interrupt */ 510 #define AR_IMR_RXCHIRP 0x00200000 /* RXCHIRP interrupt */ 511 #define AR_IMR_BCNMISC 0x00800000 /* Venice: BCNMISC */ 512 #define AR_IMR_TIM 0x00800000 /* TIM interrupt */ 513 #define AR_IMR_GPIO 0x01000000 /* GPIO Interrupt */ 514 #define AR_IMR_QCBROVF 0x02000000 /* QCU CBR overflow interrupt */ 515 #define AR_IMR_QCBRURN 0x04000000 /* QCU CBR underrun interrupt */ 516 #define AR_IMR_QTRIG 0x08000000 /* QCU scheduling trigger interrupt */ 517 #define AR_IMR_RESV0 0xF0000000 /* Reserved */ 518 519 #define AR_IMR_S0_QCU_TXOK 0x000003FF /* TXOK (QCU 0-9) */ 520 #define AR_IMR_S0_QCU_TXOK_S 0 521 #define AR_IMR_S0_QCU_TXDESC 0x03FF0000 /* TXDESC (QCU 0-9) */ 522 #define AR_IMR_S0_QCU_TXDESC_S 16 523 524 #define AR_IMR_S1_QCU_TXERR 0x000003FF /* TXERR (QCU 0-9) */ 525 #define AR_IMR_S1_QCU_TXERR_S 0 526 #define AR_IMR_S1_QCU_TXEOL 0x03FF0000 /* TXEOL (QCU 0-9) */ 527 #define AR_IMR_S1_QCU_TXEOL_S 16 528 529 #define AR_IMR_S2_QCU_TXURN 0x000003FF /* Mask for TXURN (QCU 0-9) */ 530 #define AR_IMR_S2_QCU_TXURN_S 0 531 #define AR_IMR_S2_MCABT 0x00010000 /* Master cycle abort interrupt */ 532 #define AR_IMR_S2_SSERR 0x00020000 /* SERR interrupt */ 533 #define AR_IMR_S2_DPERR 0x00040000 /* PCI bus parity error */ 534 #define AR_IMR_S2_TIM 0x01000000 /* TIM */ 535 #define AR_IMR_S2_CABEND 0x02000000 /* CABEND */ 536 #define AR_IMR_S2_DTIMSYNC 0x04000000 /* DTIMSYNC */ 537 #define AR_IMR_S2_BCNTO 0x08000000 /* BCNTO */ 538 #define AR_IMR_S2_CABTO 0x10000000 /* CABTO */ 539 #define AR_IMR_S2_DTIM 0x20000000 /* DTIM */ 540 #define AR_IMR_S2_TSFOOR 0x40000000 /* TSF OOR */ 541 #define AR_IMR_S2_TBTT 0x80000000 /* TBTT timer */ 542 543 /* AR_IMR_SR2 bits that correspond to AR_IMR_BCNMISC */ 544 #define AR_IMR_SR2_BCNMISC \ 545 (AR_IMR_S2_TIM | AR_IMR_S2_DTIM | AR_IMR_S2_DTIMSYNC | \ 546 AR_IMR_S2_CABEND | AR_IMR_S2_CABTO | AR_IMR_S2_TSFOOR | \ 547 AR_IMR_S2_TBTT) 548 549 #define AR_IMR_S3_QCU_QCBROVF 0x000003FF /* Mask for QCBROVF (QCU 0-9) */ 550 #define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 /* Mask for QCBRURN (QCU 0-9) */ 551 #define AR_IMR_S3_QCU_QCBRURN_S 16 /* Shift for QCBRURN (QCU 0-9) */ 552 553 #define AR_IMR_S4_QCU_QTRIG 0x000003FF /* Mask for QTRIG (QCU 0-9) */ 554 #define AR_IMR_S4_RESV0 0xFFFFFC00 /* Reserved */ 555 556 /* QCU registers */ 557 #define AR_NUM_QCU 10 /* Only use QCU 0-9 for forward QCU compatibility */ 558 #define AR_QCU_0 0x0001 559 #define AR_QCU_1 0x0002 560 #define AR_QCU_2 0x0004 561 #define AR_QCU_3 0x0008 562 #define AR_QCU_4 0x0010 563 #define AR_QCU_5 0x0020 564 #define AR_QCU_6 0x0040 565 #define AR_QCU_7 0x0080 566 #define AR_QCU_8 0x0100 567 #define AR_QCU_9 0x0200 568 569 #define AR_Q_CBRCFG_CBR_INTERVAL 0x00FFFFFF /* Mask for CBR interval (us) */ 570 #define AR_Q_CBRCFG_CBR_INTERVAL_S 0 /* Shift for CBR interval */ 571 #define AR_Q_CBRCFG_CBR_OVF_THRESH 0xFF000000 /* Mask for CBR overflow threshold */ 572 #define AR_Q_CBRCFG_CBR_OVF_THRESH_S 24 /* Shift for CBR overflow thresh */ 573 574 #define AR_Q_RDYTIMECFG_INT 0x00FFFFFF /* CBR interval (us) */ 575 #define AR_Q_RDYTIMECFG_INT_S 0 // Shift for ReadyTime Interval (us) */ 576 #define AR_Q_RDYTIMECFG_ENA 0x01000000 /* CBR enable */ 577 /* bits 25-31 are reserved */ 578 579 #define AR_Q_MISC_FSP 0x0000000F /* Frame Scheduling Policy mask */ 580 #define AR_Q_MISC_FSP_ASAP 0 /* ASAP */ 581 #define AR_Q_MISC_FSP_CBR 1 /* CBR */ 582 #define AR_Q_MISC_FSP_DBA_GATED 2 /* DMA Beacon Alert gated */ 583 #define AR_Q_MISC_FSP_TIM_GATED 3 /* TIM gated */ 584 #define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 /* Beacon-sent-gated */ 585 #define AR_Q_MISC_FSP_S 0 586 #define AR_Q_MISC_ONE_SHOT_EN 0x00000010 /* OneShot enable */ 587 #define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 /* Disable CBR expired counter incr 588 (empty q) */ 589 #define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 /* Disable CBR expired counter incr 590 (empty beacon q) */ 591 #define AR_Q_MISC_BEACON_USE 0x00000080 /* Beacon use indication */ 592 #define AR_Q_MISC_CBR_EXP_CNTR_LIMIT 0x00000100 /* CBR expired counter limit enable */ 593 #define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 /* Enable TXE cleared on ReadyTime expired or VEOL */ 594 #define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 /* Reset CBR expired counter */ 595 #define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 /* DCU frame early termination request control */ 596 #define AR_Q_MISC_QCU_COMP_EN 0x00001000 /* QCU frame compression enable */ 597 #define AR_Q_MISC_RESV0 0xFFFFF000 /* Reserved */ 598 599 #define AR_Q_STS_PEND_FR_CNT 0x00000003 /* Mask for Pending Frame Count */ 600 #define AR_Q_STS_RESV0 0x000000FC /* Reserved */ 601 #define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 /* Mask for CBR expired counter */ 602 #define AR_Q_STS_RESV1 0xFFFF0000 /* Reserved */ 603 604 /* DCU registers */ 605 #define AR_NUM_DCU 10 /* Only use 10 DCU's for forward QCU/DCU compatibility */ 606 #define AR_DCU_0 0x0001 607 #define AR_DCU_1 0x0002 608 #define AR_DCU_2 0x0004 609 #define AR_DCU_3 0x0008 610 #define AR_DCU_4 0x0010 611 #define AR_DCU_5 0x0020 612 #define AR_DCU_6 0x0040 613 #define AR_DCU_7 0x0080 614 #define AR_DCU_8 0x0100 615 #define AR_DCU_9 0x0200 616 617 #define AR_D_QCUMASK 0x000003FF /* Mask for QCU Mask (QCU 0-9) */ 618 #define AR_D_QCUMASK_RESV0 0xFFFFFC00 /* Reserved */ 619 620 #define AR_D_LCL_IFS_CWMIN 0x000003FF /* Mask for CW_MIN */ 621 #define AR_D_LCL_IFS_CWMIN_S 0 622 #define AR_D_LCL_IFS_CWMAX 0x000FFC00 /* Mask for CW_MAX */ 623 #define AR_D_LCL_IFS_CWMAX_S 10 624 #define AR_D_LCL_IFS_AIFS 0x0FF00000 /* Mask for AIFS */ 625 #define AR_D_LCL_IFS_AIFS_S 20 626 /* 627 * Note: even though this field is 8 bits wide the 628 * maximum supported AIFS value is 0xfc. Setting the AIFS value 629 * to 0xfd 0xfe, or 0xff will not work correctly and will cause 630 * the DCU to hang. 631 */ 632 #define AR_D_LCL_IFS_RESV0 0xF0000000 /* Reserved */ 633 634 #define AR_D_RETRY_LIMIT_FR_SH 0x0000000F /* frame short retry limit */ 635 #define AR_D_RETRY_LIMIT_FR_SH_S 0 636 #define AR_D_RETRY_LIMIT_FR_LG 0x000000F0 /* frame long retry limit */ 637 #define AR_D_RETRY_LIMIT_FR_LG_S 4 638 #define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 /* station short retry limit */ 639 #define AR_D_RETRY_LIMIT_STA_SH_S 8 640 #define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 /* station short retry limit */ 641 #define AR_D_RETRY_LIMIT_STA_LG_S 14 642 #define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 /* Reserved */ 643 644 #define AR_D_CHNTIME_DUR 0x000FFFFF /* ChannelTime duration (us) */ 645 #define AR_D_CHNTIME_DUR_S 0 /* Shift for ChannelTime duration */ 646 #define AR_D_CHNTIME_EN 0x00100000 /* ChannelTime enable */ 647 #define AR_D_CHNTIME_RESV0 0xFFE00000 /* Reserved */ 648 649 #define AR_D_MISC_BKOFF_THRESH 0x0000003F /* Backoff threshold */ 650 #define AR_D_MISC_ETS_RTS 0x00000040 /* End of transmission series 651 station RTS/data failure 652 count reset policy */ 653 #define AR_D_MISC_ETS_CW 0x00000080 /* End of transmission series 654 CW reset policy */ 655 #define AR_D_MISC_FRAG_WAIT_EN 0x00000100 /* Wait for next fragment */ 656 #define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 /* Backoff during a frag burst */ 657 #define AR_D_MISC_HCF_POLL_EN 0x00000800 /* HFC poll enable */ 658 #define AR_D_MISC_BKOFF_PERSISTENCE 0x00001000 /* Backoff persistence factor 659 setting */ 660 #define AR_D_MISC_FR_PREFETCH_EN 0x00002000 /* Frame prefetch enable */ 661 #define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 /* Mask for Virtual collision 662 handling policy */ 663 #define AR_D_MISC_VIR_COL_HANDLING_S 14 664 /* FOO redefined for venice CW increment policy */ 665 #define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 /* Normal */ 666 #define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 /* Ignore */ 667 #define AR_D_MISC_BEACON_USE 0x00010000 /* Beacon use indication */ 668 #define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 /* DCU arbiter lockout ctl */ 669 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 /* DCU arbiter lockout ctl */ 670 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 /* No lockout */ 671 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 /* Intra-frame */ 672 #define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 /* Global */ 673 #define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 /* DCU arbiter lockout ignore control */ 674 #define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 /* Sequence number increment disable */ 675 #define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 /* Post-frame backoff disable */ 676 #define AR_D_MISC_VIRT_COLL_POLICY 0x00400000 /* Virtual coll. handling policy */ 677 #define AR_D_MISC_BLOWN_IFS_POLICY 0x00800000 /* Blown IFS handling policy */ 678 #define AR_D_MISC_RESV0 0xFE000000 /* Reserved */ 679 680 #define AR_D_SEQNUM_RESV0 0xFFFFF000 /* Reserved */ 681 682 #define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 /* LFSR slice select */ 683 #define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 /* Turbo mode indication */ 684 #define AR_D_GBL_IFS_MISC_SIFS_DURATION_USEC 0x000003F0 /* SIFS duration (us) */ 685 #define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 /* microsecond duration */ 686 #define AR_D_GBL_IFS_MISC_USEC_DURATION_S 10 687 #define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 /* DCU arbiter delay */ 688 #define AR_D_GBL_IFS_MISC_RESV0 0xFFC00000 /* Reserved */ 689 690 /* DMA & PCI Registers in PCI space (usable during sleep) */ 691 #define AR_RC_MAC 0x00000001 /* MAC reset */ 692 #define AR_RC_BB 0x00000002 /* Baseband reset */ 693 #define AR_RC_RESV0 0x00000004 /* Reserved */ 694 #define AR_RC_RESV1 0x00000008 /* Reserved */ 695 #define AR_RC_PCI 0x00000010 /* PCI-core reset */ 696 697 #define AR_SCR_SLDUR 0x0000ffff /* sleep duration, units of 128us */ 698 #define AR_SCR_SLDUR_S 0 699 #define AR_SCR_SLE 0x00030000 /* sleep enable */ 700 #define AR_SCR_SLE_S 16 701 #define AR_SCR_SLE_WAKE 0 /* force wake */ 702 #define AR_SCR_SLE_SLP 1 /* force sleep */ 703 #define AR_SCR_SLE_NORM 2 /* sleep logic normal operation */ 704 #define AR_SCR_SLDTP 0x00040000 /* sleep duration timing policy */ 705 #define AR_SCR_SLDWP 0x00080000 /* sleep duration write policy */ 706 #define AR_SCR_SLEPOL 0x00100000 /* sleep policy mode */ 707 #define AR_SCR_MIBIE 0x00200000 /* sleep perf cntrs MIB intr ena */ 708 #define AR_SCR_UNKNOWN 0x00400000 709 710 #define AR_INTPEND_TRUE 0x00000001 /* interrupt pending */ 711 712 #define AR_SFR_SLEEP 0x00000001 /* force sleep */ 713 714 #define AR_PCICFG_SCLK_SEL 0x00000002 /* sleep clock select */ 715 #define AR_PCICFG_SCLK_SEL_S 1 716 #define AR_PCICFG_CLKRUNEN 0x00000004 /* enable PCI CLKRUN function */ 717 #define AR_PCICFG_EEPROM_SIZE 0x00000018 /* Mask for EEPROM size */ 718 #define AR_PCICFG_EEPROM_SIZE_4 0 /* EEPROM size 4 Kbit */ 719 #define AR_PCICFG_EEPROM_SIZE_8K 1 /* EEPROM size 8 Kbit */ 720 #define AR_PCICFG_EEPROM_SIZE_16K 2 /* EEPROM size 16 Kbit */ 721 #define AR_PCICFG_EEPROM_SIZE_FAILED 3 /* Failure */ 722 #define AR_PCICFG_EEPROM_SIZE_S 3 723 #define AR_PCICFG_LEDCTL 0x00000060 /* LED control Status */ 724 #define AR_PCICFG_LEDCTL_NONE 0 /* STA is not associated or trying */ 725 #define AR_PCICFG_LEDCTL_PEND 1 /* STA is trying to associate */ 726 #define AR_PCICFG_LEDCTL_ASSOC 2 /* STA is associated */ 727 #define AR_PCICFG_LEDCTL_S 5 728 #define AR_PCICFG_PCI_BUS_SEL 0x00000380 /* PCI observation bus mux select */ 729 #define AR_PCICFG_DIS_CBE_FIX 0x00000400 /* Disable fix for bad PCI CBE# generation */ 730 #define AR_PCICFG_SL_INTEN 0x00000800 /* enable interrupt line assertion when asleep */ 731 #define AR_PCICFG_RETRYFIXEN 0x00001000 /* Enable PCI core retry fix */ 732 #define AR_PCICFG_SL_INPEN 0x00002000 /* Force asleep when an interrupt is pending */ 733 #define AR_PCICFG_RESV1 0x0000C000 /* Reserved */ 734 #define AR_PCICFG_SPWR_DN 0x00010000 /* mask for sleep/awake indication */ 735 #define AR_PCICFG_LEDMODE 0x000E0000 /* LED mode */ 736 #define AR_PCICFG_LEDMODE_PROP 0 /* Blink prop to filtered tx/rx */ 737 #define AR_PCICFG_LEDMODE_RPROP 1 /* Blink prop to unfiltered tx/rx */ 738 #define AR_PCICFG_LEDMODE_SPLIT 2 /* Blink power for tx/net for rx */ 739 #define AR_PCICFG_LEDMODE_RAND 3 /* Blink randomly */ 740 /* NB: s/w led control present in Hainan 1.1 and above */ 741 #define AR_PCICFG_LEDMODE_OFF 4 /* s/w control + both led's off */ 742 #define AR_PCICFG_LEDMODE_POWON 5 /* s/w control + power led on */ 743 #define AR_PCICFG_LEDMODE_NETON 6 /* s/w control + network led on */ 744 #define AR_PCICFG_LEDMODE_S 17 745 #define AR_PCICFG_LEDBLINK 0x00700000 /* LED blink threshold select */ 746 #define AR_PCICFG_LEDBLINK_S 20 747 #define AR_PCICFG_LEDSLOW 0x00800000 /* LED slowest blink rate mode */ 748 #define AR_PCICFG_LEDSLOW_S 23 749 #define AR_PCICFG_SCLK_RATE_IND 0x03000000 /* Sleep clock rate */ 750 #define AR_PCICFG_SCLK_RATE_IND_S 24 751 #define AR_PCICFG_RESV2 0xFC000000 /* Reserved */ 752 753 #define AR_GPIOCR_CR_SHIFT 2 /* Each CR is 2 bits */ 754 #define AR_GPIOCR_CR_N(_g) (0 << (AR_GPIOCR_CR_SHIFT * (_g))) 755 #define AR_GPIOCR_CR_0(_g) (1 << (AR_GPIOCR_CR_SHIFT * (_g))) 756 #define AR_GPIOCR_CR_1(_g) (2 << (AR_GPIOCR_CR_SHIFT * (_g))) 757 #define AR_GPIOCR_CR_A(_g) (3 << (AR_GPIOCR_CR_SHIFT * (_g))) 758 #define AR_GPIOCR_INT_SHIFT 12 /* Interrupt select field shifter */ 759 #define AR_GPIOCR_INT(_g) ((_g) << AR_GPIOCR_INT_SHIFT) 760 #define AR_GPIOCR_INT_MASK 0x00007000 /* Interrupt select field mask */ 761 #define AR_GPIOCR_INT_ENA 0x00008000 /* Enable GPIO Interrupt */ 762 #define AR_GPIOCR_INT_SELL 0x00000000 /* Generate int if pin is low */ 763 #define AR_GPIOCR_INT_SELH 0x00010000 /* Generate int if pin is high */ 764 #define AR_GPIOCR_INT_SEL AR_GPIOCR_INT_SELH 765 766 #define AR_SREV_ID 0x000000FF /* Mask to read SREV info */ 767 #define AR_SREV_ID_S 4 /* Mask to shift Major Rev Info */ 768 #define AR_SREV_REVISION 0x0000000F /* Mask for Chip revision level */ 769 #define AR_SREV_REVISION_MIN 0 /* lowest revision level */ 770 #define AR_SREV_REVISION_MAX 0xF /* highest revision level */ 771 #define AR_SREV_FPGA 1 772 #define AR_SREV_D2PLUS 2 773 #define AR_SREV_D2PLUS_MS 3 /* metal spin */ 774 #define AR_SREV_CRETE 4 775 #define AR_SREV_CRETE_MS 5 /* FCS metal spin */ 776 #define AR_SREV_CRETE_MS23 7 /* 2.3 metal spin (6 skipped) */ 777 #define AR_SREV_CRETE_23 8 /* 2.3 full tape out */ 778 #define AR_SREV_GRIFFIN_LITE 8 779 #define AR_SREV_HAINAN 9 780 #define AR_SREV_CONDOR 11 781 #define AR_SREV_VERSION 0x000000F0 /* Mask for Chip version */ 782 #define AR_SREV_VERSION_CRETE 0 783 #define AR_SREV_VERSION_MAUI_1 1 784 #define AR_SREV_VERSION_MAUI_2 2 785 #define AR_SREV_VERSION_SPIRIT 3 786 #define AR_SREV_VERSION_OAHU 4 787 #define AR_SREV_VERSION_VENICE 5 788 #define AR_SREV_VERSION_GRIFFIN 7 789 #define AR_SREV_VERSION_CONDOR 9 790 #define AR_SREV_VERSION_EAGLE 10 791 #define AR_SREV_VERSION_COBRA 11 792 #define AR_SREV_2413 AR_SREV_VERSION_GRIFFIN 793 #define AR_SREV_5413 AR_SREV_VERSION_EAGLE 794 #define AR_SREV_2415 AR_SREV_VERSION_COBRA 795 #define AR_SREV_5424 AR_SREV_VERSION_CONDOR 796 #define AR_SREV_2425 14 /* SWAN */ 797 #define AR_SREV_2417 15 /* Nala */ 798 #define AR_SREV_OAHU_ES 0 /* Engineering Sample */ 799 #define AR_SREV_OAHU_PROD 2 /* Production */ 800 801 #define AR_PHYREV_HAINAN 0x43 802 #define AR_ANALOG5REV_HAINAN 0x46 803 804 #define AR_RADIO_SREV_MAJOR 0xF0 805 #define AR_RADIO_SREV_MINOR 0x0F 806 #define AR_RAD5111_SREV_MAJOR 0x10 /* All current supported ar5211 5 GHz 807 radios are rev 0x10 */ 808 #define AR_RAD5111_SREV_PROD 0x15 /* Current production level radios */ 809 #define AR_RAD2111_SREV_MAJOR 0x20 /* All current supported ar5211 2 GHz 810 radios are rev 0x10 */ 811 #define AR_RAD5112_SREV_MAJOR 0x30 /* 5112 Major Rev */ 812 #define AR_RAD5112_SREV_2_0 0x35 /* AR5112 Revision 2.0 */ 813 #define AR_RAD5112_SREV_2_1 0x36 /* AR5112 Revision 2.1 */ 814 #define AR_RAD2112_SREV_MAJOR 0x40 /* 2112 Major Rev */ 815 #define AR_RAD2112_SREV_2_0 0x45 /* AR2112 Revision 2.0 */ 816 #define AR_RAD2112_SREV_2_1 0x46 /* AR2112 Revision 2.1 */ 817 #define AR_RAD2413_SREV_MAJOR 0x50 /* 2413 Major Rev */ 818 #define AR_RAD5413_SREV_MAJOR 0x60 /* 5413 Major Rev */ 819 #define AR_RAD2316_SREV_MAJOR 0x70 /* 2316 Major Rev */ 820 #define AR_RAD2317_SREV_MAJOR 0x80 /* 2317 Major Rev */ 821 #define AR_RAD5424_SREV_MAJOR 0xa0 /* Mostly same as 5413 Major Rev */ 822 823 #define AR_PCIE_PMC_ENA_L1 0x01 /* enable PCIe core enter L1 when 824 d2_sleep_en is asserted */ 825 #define AR_PCIE_PMC_ENA_RESET 0x08 /* enable reset on link going down */ 826 827 /* EEPROM Registers in the MAC */ 828 #define AR_EEPROM_CMD_READ 0x00000001 829 #define AR_EEPROM_CMD_WRITE 0x00000002 830 #define AR_EEPROM_CMD_RESET 0x00000004 831 832 #define AR_EEPROM_STS_READ_ERROR 0x00000001 833 #define AR_EEPROM_STS_READ_COMPLETE 0x00000002 834 #define AR_EEPROM_STS_WRITE_ERROR 0x00000004 835 #define AR_EEPROM_STS_WRITE_COMPLETE 0x00000008 836 837 #define AR_EEPROM_CFG_SIZE 0x00000003 /* size determination override */ 838 #define AR_EEPROM_CFG_SIZE_AUTO 0 839 #define AR_EEPROM_CFG_SIZE_4KBIT 1 840 #define AR_EEPROM_CFG_SIZE_8KBIT 2 841 #define AR_EEPROM_CFG_SIZE_16KBIT 3 842 #define AR_EEPROM_CFG_DIS_WWRCL 0x00000004 /* Disable wait for write completion */ 843 #define AR_EEPROM_CFG_CLOCK 0x00000018 /* clock rate control */ 844 #define AR_EEPROM_CFG_CLOCK_S 3 /* clock rate control */ 845 #define AR_EEPROM_CFG_CLOCK_156KHZ 0 846 #define AR_EEPROM_CFG_CLOCK_312KHZ 1 847 #define AR_EEPROM_CFG_CLOCK_625KHZ 2 848 #define AR_EEPROM_CFG_RESV0 0x000000E0 /* Reserved */ 849 #define AR_EEPROM_CFG_PKEY 0x00FFFF00 /* protection key */ 850 #define AR_EEPROM_CFG_PKEY_S 8 851 #define AR_EEPROM_CFG_EN_L 0x01000000 /* EPRM_EN_L setting */ 852 853 /* MAC PCU Registers */ 854 855 #define AR_STA_ID1_SADH_MASK 0x0000FFFF /* upper 16 bits of MAC addr */ 856 #define AR_STA_ID1_STA_AP 0x00010000 /* Device is AP */ 857 #define AR_STA_ID1_ADHOC 0x00020000 /* Device is ad-hoc */ 858 #define AR_STA_ID1_PWR_SAV 0x00040000 /* Power save reporting in 859 self-generated frames */ 860 #define AR_STA_ID1_KSRCHDIS 0x00080000 /* Key search disable */ 861 #define AR_STA_ID1_PCF 0x00100000 /* Observe PCF */ 862 #define AR_STA_ID1_USE_DEFANT 0x00200000 /* Use default antenna */ 863 #define AR_STA_ID1_UPD_DEFANT 0x00400000 /* Update default antenna w/ 864 TX antenna */ 865 #define AR_STA_ID1_RTS_USE_DEF 0x00800000 /* Use default antenna to send RTS */ 866 #define AR_STA_ID1_ACKCTS_6MB 0x01000000 /* Use 6Mb/s rate for ACK & CTS */ 867 #define AR_STA_ID1_BASE_RATE_11B 0x02000000/* Use 11b base rate for ACK & CTS */ 868 #define AR_STA_ID1_USE_DA_SG 0x04000000 /* Use default antenna for 869 self-generated frames */ 870 #define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 /* Enable Michael */ 871 #define AR_STA_ID1_KSRCH_MODE 0x10000000 /* Look-up key when keyID != 0 */ 872 #define AR_STA_ID1_PRE_SEQNUM 0x20000000 /* Preserve s/w sequence number */ 873 #define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 874 #define AR_STA_ID1_MCAST_KSRCH 0x80000000 /* Do keycache search for mcast */ 875 876 #define AR_BSS_ID1_U16 0x0000FFFF /* Upper 16 bits of BSSID */ 877 #define AR_BSS_ID1_AID 0xFFFF0000 /* Association ID */ 878 #define AR_BSS_ID1_AID_S 16 879 880 #define AR_SLOT_TIME_MASK 0x000007FF /* Slot time mask */ 881 882 #define AR_TIME_OUT_ACK 0x00003FFF /* ACK time-out */ 883 #define AR_TIME_OUT_ACK_S 0 884 #define AR_TIME_OUT_CTS 0x3FFF0000 /* CTS time-out */ 885 #define AR_TIME_OUT_CTS_S 16 886 887 #define AR_RSSI_THR_MASK 0x000000FF /* Beacon RSSI warning threshold */ 888 #define AR_RSSI_THR_BM_THR 0x0000FF00 /* Missed beacon threshold */ 889 #define AR_RSSI_THR_BM_THR_S 8 890 891 #define AR_USEC_USEC 0x0000007F /* clock cycles in 1 usec */ 892 #define AR_USEC_USEC_S 0 893 #define AR_USEC_USEC32 0x00003F80 /* 32MHz clock cycles in 1 usec */ 894 #define AR_USEC_USEC32_S 7 895 896 #define AR5212_USEC_TX_LAT_M 0x007FC000 /* Tx latency */ 897 #define AR5212_USEC_TX_LAT_S 14 898 #define AR5212_USEC_RX_LAT_M 0x1F800000 /* Rx latency */ 899 #define AR5212_USEC_RX_LAT_S 23 900 901 #define AR_BEACON_PERIOD 0x0000FFFF /* Beacon period mask in TU/msec */ 902 #define AR_BEACON_PERIOD_S 0 903 #define AR_BEACON_TIM 0x007F0000 /* byte offset of TIM start */ 904 #define AR_BEACON_TIM_S 16 905 #define AR_BEACON_EN 0x00800000 /* Beacon enable */ 906 #define AR_BEACON_RESET_TSF 0x01000000 /* Clear TSF to 0 */ 907 908 #define AR_RX_NONE 0x00000000 /* Disallow all frames */ 909 #define AR_RX_UCAST 0x00000001 /* Allow unicast frames */ 910 #define AR_RX_MCAST 0x00000002 /* Allow multicast frames */ 911 #define AR_RX_BCAST 0x00000004 /* Allow broadcast frames */ 912 #define AR_RX_CONTROL 0x00000008 /* Allow control frames */ 913 #define AR_RX_BEACON 0x00000010 /* Allow beacon frames */ 914 #define AR_RX_PROM 0x00000020 /* Promiscuous mode, all packets */ 915 #define AR_RX_PROBE_REQ 0x00000080 /* Allow probe request frames */ 916 917 #define AR_DIAG_CACHE_ACK 0x00000001 /* No ACK if no valid key found */ 918 #define AR_DIAG_ACK_DIS 0x00000002 /* Disable ACK generation */ 919 #define AR_DIAG_CTS_DIS 0x00000004 /* Disable CTS generation */ 920 #define AR_DIAG_ENCRYPT_DIS 0x00000008 /* Disable encryption */ 921 #define AR_DIAG_DECRYPT_DIS 0x00000010 /* Disable decryption */ 922 #define AR_DIAG_RX_DIS 0x00000020 /* Disable receive */ 923 #define AR_DIAG_CORR_FCS 0x00000080 /* Corrupt FCS */ 924 #define AR_DIAG_CHAN_INFO 0x00000100 /* Dump channel info */ 925 #define AR_DIAG_EN_SCRAMSD 0x00000200 /* Enable fixed scrambler seed */ 926 #define AR_DIAG_SCRAM_SEED 0x0001FC00 /* Fixed scrambler seed */ 927 #define AR_DIAG_SCRAM_SEED_S 10 928 #define AR_DIAG_FRAME_NV0 0x00020000 /* Accept frames of non-zero 929 protocol version */ 930 #define AR_DIAG_OBS_PT_SEL 0x000C0000 /* Observation point select */ 931 #define AR_DIAG_OBS_PT_SEL_S 18 932 #define AR_DIAG_RX_CLR_HI 0x00100000 /* Force rx_clear high */ 933 #define AR_DIAG_IGNORE_CS 0x00200000 /* Force virtual carrier sense */ 934 #define AR_DIAG_CHAN_IDLE 0x00400000 /* Force channel idle high */ 935 #define AR_DIAG_PHEAR_ME 0x00800000 /* Uses framed and wait_wep in the pherr_enable_eifs if set to 0 */ 936 937 #define AR_SLEEP1_NEXT_DTIM 0x0007ffff /* Abs. time(1/8TU) for next DTIM */ 938 #define AR_SLEEP1_NEXT_DTIM_S 0 939 #define AR_SLEEP1_ASSUME_DTIM 0x00080000 /* Assume DTIM present on missent beacon */ 940 #define AR_SLEEP1_ENH_SLEEP_ENA 0x00100000 /* Enable enhanced sleep logic */ 941 #define AR_SLEEP1_CAB_TIMEOUT 0xff000000 /* CAB timeout(TU) */ 942 #define AR_SLEEP1_CAB_TIMEOUT_S 24 943 944 #define AR_SLEEP2_NEXT_TIM 0x0007ffff /* Abs. time(1/8TU) for next DTIM */ 945 #define AR_SLEEP2_NEXT_TIM_S 0 946 #define AR_SLEEP2_BEACON_TIMEOUT 0xff000000 /* Beacon timeout(TU) */ 947 #define AR_SLEEP2_BEACON_TIMEOUT_S 24 948 949 #define AR_SLEEP3_TIM_PERIOD 0x0000ffff /* Tim/Beacon period (TU) */ 950 #define AR_SLEEP3_TIM_PERIOD_S 0 951 #define AR_SLEEP3_DTIM_PERIOD 0xffff0000 /* DTIM period (TU) */ 952 #define AR_SLEEP3_DTIM_PERIOD_S 16 953 954 #define AR_TPC_ACK 0x0000003f /* ack frames */ 955 #define AR_TPC_ACK_S 0 956 #define AR_TPC_CTS 0x00003f00 /* cts frames */ 957 #define AR_TPC_CTS_S 8 958 #define AR_TPC_CHIRP 0x003f0000 /* chirp frames */ 959 #define AR_TPC_CHIRP_S 16 960 #define AR_TPC_DOPPLER 0x0f000000 /* doppler chirp span */ 961 #define AR_TPC_DOPPLER_S 24 962 963 #define AR_PHY_ERR_RADAR 0x00000020 /* Radar signal */ 964 #define AR_PHY_ERR_OFDM_TIMING 0x00020000 /* False detect for OFDM */ 965 #define AR_PHY_ERR_CCK_TIMING 0x02000000 /* False detect for CCK */ 966 967 #define AR_TSF_PARM_INCREMENT 0x000000ff 968 #define AR_TSF_PARM_INCREMENT_S 0 969 970 #define AR_NOACK_2BIT_VALUE 0x0000000f 971 #define AR_NOACK_2BIT_VALUE_S 0 972 #define AR_NOACK_BIT_OFFSET 0x00000070 973 #define AR_NOACK_BIT_OFFSET_S 4 974 #define AR_NOACK_BYTE_OFFSET 0x00000180 975 #define AR_NOACK_BYTE_OFFSET_S 7 976 977 #define AR_MISC_MODE_BSSID_MATCH_FORCE 0x1 /* Force BSSID match */ 978 #define AR_MISC_MODE_ACKSIFS_MEMORY 0x2 /* ACKSIFS use contents of Rate */ 979 #define AR_MISC_MODE_MIC_NEW_LOC_ENABLE 0x4 /* Xmit Michael Key same as Rcv */ 980 #define AR_MISC_MODE_TX_ADD_TSF 0x8 /* Beacon/Probe-Rsp timestamp add (not replace) */ 981 982 #define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) /* key bit 0-31 */ 983 #define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) /* key bit 32-47 */ 984 #define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) /* key bit 48-79 */ 985 #define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) /* key bit 80-95 */ 986 #define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) /* key bit 96-127 */ 987 #define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) /* key type */ 988 #define AR_KEYTABLE_TYPE_40 0x00000000 /* WEP 40 bit key */ 989 #define AR_KEYTABLE_TYPE_104 0x00000001 /* WEP 104 bit key */ 990 #define AR_KEYTABLE_TYPE_128 0x00000003 /* WEP 128 bit key */ 991 #define AR_KEYTABLE_TYPE_TKIP 0x00000004 /* TKIP and Michael */ 992 #define AR_KEYTABLE_TYPE_AES 0x00000005 /* AES/OCB 128 bit key */ 993 #define AR_KEYTABLE_TYPE_CCM 0x00000006 /* AES/CCM 128 bit key */ 994 #define AR_KEYTABLE_TYPE_CLR 0x00000007 /* no encryption */ 995 #define AR_KEYTABLE_ANT 0x00000008 /* previous transmit antenna */ 996 #define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) /* MAC address 1-32 */ 997 #define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) /* MAC address 33-47 */ 998 #define AR_KEYTABLE_VALID 0x00008000 /* key and MAC address valid */ 999 1000 /* Compress settings */ 1001 #define AR_CCFG_WIN_M 0x00000007 /* mask for AR_CCFG_WIN size */ 1002 #define AR_CCFG_MIB_INT_EN 0x00000008 /* compression performance MIB counter int enable */ 1003 #define AR_CCUCFG_RESET_VAL 0x00100200 /* the should be reset value */ 1004 #define AR_CCUCFG_CATCHUP_EN 0x00000001 /* Compression catchup enable */ 1005 #define AR_DCM_D_EN 0x00000001 /* all direct frames to be decompressed */ 1006 #define AR_COMPRESSION_WINDOW_SIZE 4096 /* default comp. window size */ 1007 1008 #endif /* _DEV_AR5212REG_H_ */ 1009