1 /*- 2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * Driver for the Atheros Wireless LAN controller. 35 * 36 * This software is derived from work of Atsushi Onoe; his contribution 37 * is greatly appreciated. 38 */ 39 40 #include "opt_inet.h" 41 #include "opt_ath.h" 42 /* 43 * This is needed for register operations which are performed 44 * by the driver - eg, calls to ath_hal_gettsf32(). 45 * 46 * It's also required for any AH_DEBUG checks in here, eg the 47 * module dependencies. 48 */ 49 #include "opt_ah.h" 50 #include "opt_wlan.h" 51 52 #include <sys/param.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/mbuf.h> 56 #include <sys/malloc.h> 57 #include <sys/lock.h> 58 #include <sys/mutex.h> 59 #include <sys/kernel.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/errno.h> 63 #include <sys/callout.h> 64 #include <sys/bus.h> 65 #include <sys/endian.h> 66 #include <sys/kthread.h> 67 #include <sys/taskqueue.h> 68 #include <sys/priv.h> 69 #include <sys/module.h> 70 #include <sys/ktr.h> 71 #include <sys/smp.h> /* for mp_ncpus */ 72 73 #include <machine/bus.h> 74 75 #include <net/if.h> 76 #include <net/if_dl.h> 77 #include <net/if_media.h> 78 #include <net/if_types.h> 79 #include <net/if_arp.h> 80 #include <net/ethernet.h> 81 #include <net/if_llc.h> 82 83 #include <net80211/ieee80211_var.h> 84 #include <net80211/ieee80211_regdomain.h> 85 #ifdef IEEE80211_SUPPORT_SUPERG 86 #include <net80211/ieee80211_superg.h> 87 #endif 88 #ifdef IEEE80211_SUPPORT_TDMA 89 #include <net80211/ieee80211_tdma.h> 90 #endif 91 92 #include <net/bpf.h> 93 94 #ifdef INET 95 #include <netinet/in.h> 96 #include <netinet/if_ether.h> 97 #endif 98 99 #include <dev/ath/if_athvar.h> 100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */ 101 #include <dev/ath/ath_hal/ah_diagcodes.h> 102 103 #include <dev/ath/if_ath_debug.h> 104 #include <dev/ath/if_ath_misc.h> 105 #include <dev/ath/if_ath_tsf.h> 106 #include <dev/ath/if_ath_tx.h> 107 #include <dev/ath/if_ath_sysctl.h> 108 #include <dev/ath/if_ath_led.h> 109 #include <dev/ath/if_ath_keycache.h> 110 #include <dev/ath/if_ath_rx.h> 111 #include <dev/ath/if_ath_beacon.h> 112 #include <dev/ath/if_athdfs.h> 113 114 #ifdef ATH_TX99_DIAG 115 #include <dev/ath/ath_tx99/ath_tx99.h> 116 #endif 117 118 #include <dev/ath/if_ath_tx_edma.h> 119 120 #ifdef ATH_DEBUG_ALQ 121 #include <dev/ath/if_ath_alq.h> 122 #endif 123 124 /* 125 * some general macros 126 */ 127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1) 128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1) 129 130 /* 131 * XXX doesn't belong here, and should be tunable 132 */ 133 #define ATH_TXSTATUS_RING_SIZE 512 134 135 MALLOC_DECLARE(M_ATHDEV); 136 137 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched); 138 139 static void 140 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq) 141 { 142 struct ath_buf *bf; 143 int i = 0; 144 145 ATH_TXQ_LOCK_ASSERT(txq); 146 147 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called\n", __func__); 148 149 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) { 150 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) 151 break; 152 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr); 153 #ifdef ATH_DEBUG 154 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 155 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0); 156 #endif/* ATH_DEBUG */ 157 #ifdef ATH_DEBUG_ALQ 158 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 159 ath_tx_alq_post(sc, bf); 160 #endif /* ATH_DEBUG_ALQ */ 161 txq->axq_fifo_depth++; 162 i++; 163 } 164 if (i > 0) 165 ath_hal_txstart(sc->sc_ah, txq->axq_qnum); 166 } 167 168 /* 169 * Re-initialise the DMA FIFO with the current contents of 170 * said TXQ. 171 * 172 * This should only be called as part of the chip reset path, as it 173 * assumes the FIFO is currently empty. 174 */ 175 static void 176 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq) 177 { 178 179 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called: txq=%p, qnum=%d\n", 180 __func__, 181 txq, 182 txq->axq_qnum); 183 184 ATH_TXQ_LOCK_ASSERT(txq); 185 ath_edma_tx_fifo_fill(sc, txq); 186 } 187 188 /* 189 * Hand off this frame to a hardware queue. 190 * 191 * Things are a bit hairy in the EDMA world. The TX FIFO is only 192 * 8 entries deep, so we need to keep track of exactly what we've 193 * pushed into the FIFO and what's just sitting in the TX queue, 194 * waiting to go out. 195 * 196 * So this is split into two halves - frames get appended to the 197 * TXQ; then a scheduler is called to push some frames into the 198 * actual TX FIFO. 199 */ 200 static void 201 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq, 202 struct ath_buf *bf) 203 { 204 struct ath_hal *ah = sc->sc_ah; 205 206 ATH_TXQ_LOCK(txq); 207 208 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 209 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 210 211 /* 212 * XXX TODO: write a hard-coded check to ensure that 213 * the queue id in the TX descriptor matches txq->axq_qnum. 214 */ 215 216 /* Update aggr stats */ 217 if (bf->bf_state.bfs_aggr) 218 txq->axq_aggr_depth++; 219 220 /* Push and update frame stats */ 221 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 222 223 /* Only schedule to the FIFO if there's space */ 224 if (txq->axq_fifo_depth < HAL_TXFIFO_DEPTH) { 225 #ifdef ATH_DEBUG 226 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC) 227 ath_printtxbuf(sc, bf, txq->axq_qnum, 0, 0); 228 #endif /* ATH_DEBUG */ 229 #ifdef ATH_DEBUG_ALQ 230 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 231 ath_tx_alq_post(sc, bf); 232 #endif /* ATH_DEBUG_ALQ */ 233 ath_hal_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 234 txq->axq_fifo_depth++; 235 ath_hal_txstart(ah, txq->axq_qnum); 236 } 237 ATH_TXQ_UNLOCK(txq); 238 } 239 240 /* 241 * Hand off this frame to a multicast software queue. 242 * 243 * The EDMA TX CABQ will get a list of chained frames, chained 244 * together using the next pointer. The single head of that 245 * particular queue is pushed to the hardware CABQ. 246 */ 247 static void 248 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq, 249 struct ath_buf *bf) 250 { 251 252 ATH_TX_LOCK_ASSERT(sc); 253 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0, 254 ("%s: busy status 0x%x", __func__, bf->bf_flags)); 255 256 ATH_TXQ_LOCK(txq); 257 /* 258 * XXX this is mostly duplicated in ath_tx_handoff_mcast(). 259 */ 260 if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) { 261 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s); 262 struct ieee80211_frame *wh; 263 264 /* mark previous frame */ 265 wh = mtod(bf_last->bf_m, struct ieee80211_frame *); 266 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA; 267 268 /* sync descriptor to memory */ 269 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap, 270 BUS_DMASYNC_PREWRITE); 271 272 /* link descriptor */ 273 ath_hal_settxdesclink(sc->sc_ah, 274 bf_last->bf_lastds, 275 bf->bf_daddr); 276 } 277 278 #ifdef ATH_DEBUG_ALQ 279 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC)) 280 ath_tx_alq_post(sc, bf); 281 #endif /* ATH_DEBUG_ALQ */ 282 283 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list); 284 ath_hal_gettxdesclinkptr(sc->sc_ah, bf->bf_lastds, &txq->axq_link); 285 ATH_TXQ_UNLOCK(txq); 286 } 287 288 /* 289 * Handoff this frame to the hardware. 290 * 291 * For the multicast queue, this will treat it as a software queue 292 * and append it to the list, after updating the MORE_DATA flag 293 * in the previous frame. The cabq processing code will ensure 294 * that the queue contents gets transferred over. 295 * 296 * For the hardware queues, this will queue a frame to the queue 297 * like before, then populate the FIFO from that. Since the 298 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that 299 * frames such as management frames don't get prematurely dropped. 300 * 301 * This does imply that a similar flush-hwq-to-fifoq method will 302 * need to be called from the processq function, before the 303 * per-node software scheduler is called. 304 */ 305 static void 306 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq, 307 struct ath_buf *bf) 308 { 309 310 DPRINTF(sc, ATH_DEBUG_XMIT_DESC, 311 "%s: called; bf=%p, txq=%p, qnum=%d\n", 312 __func__, 313 bf, 314 txq, 315 txq->axq_qnum); 316 317 if (txq->axq_qnum == ATH_TXQ_SWQ) 318 ath_edma_xmit_handoff_mcast(sc, txq, bf); 319 else 320 ath_edma_xmit_handoff_hw(sc, txq, bf); 321 322 #if 0 323 /* 324 * XXX For now this is a placeholder; free the buffer 325 * and inform the stack that the TX failed. 326 */ 327 ath_tx_default_comp(sc, bf, 1); 328 #endif 329 } 330 331 static int 332 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum) 333 { 334 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 335 336 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH, 337 M_ATHDEV, 338 M_NOWAIT | M_ZERO); 339 if (te->m_fifo == NULL) { 340 device_printf(sc->sc_dev, "%s: malloc failed\n", 341 __func__); 342 return (-ENOMEM); 343 } 344 345 /* 346 * Set initial "empty" state. 347 */ 348 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0; 349 350 return (0); 351 } 352 353 static int 354 ath_edma_free_txfifo(struct ath_softc *sc, int qnum) 355 { 356 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum]; 357 358 /* XXX TODO: actually deref the ath_buf entries? */ 359 free(te->m_fifo, M_ATHDEV); 360 return (0); 361 } 362 363 static int 364 ath_edma_dma_txsetup(struct ath_softc *sc) 365 { 366 int error; 367 int i; 368 369 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma, 370 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE); 371 if (error != 0) 372 return (error); 373 374 ath_hal_setuptxstatusring(sc->sc_ah, 375 (void *) sc->sc_txsdma.dd_desc, 376 sc->sc_txsdma.dd_desc_paddr, 377 ATH_TXSTATUS_RING_SIZE); 378 379 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 380 ath_edma_setup_txfifo(sc, i); 381 } 382 383 return (0); 384 } 385 386 static int 387 ath_edma_dma_txteardown(struct ath_softc *sc) 388 { 389 int i; 390 391 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 392 ath_edma_free_txfifo(sc, i); 393 } 394 395 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL); 396 return (0); 397 } 398 399 /* 400 * Drain all TXQs, potentially after completing the existing completed 401 * frames. 402 */ 403 static void 404 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type) 405 { 406 struct ifnet *ifp = sc->sc_ifp; 407 int i; 408 409 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__); 410 411 (void) ath_stoptxdma(sc); 412 413 /* 414 * If reset type is noloss, the TX FIFO needs to be serviced 415 * and those frames need to be handled. 416 * 417 * Otherwise, just toss everything in each TX queue. 418 */ 419 if (reset_type == ATH_RESET_NOLOSS) { 420 ath_edma_tx_processq(sc, 0); 421 } else { 422 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) { 423 if (ATH_TXQ_SETUP(sc, i)) 424 ath_tx_draintxq(sc, &sc->sc_txq[i]); 425 } 426 } 427 428 /* XXX dump out the TX completion FIFO contents */ 429 430 /* XXX dump out the frames */ 431 432 IF_LOCK(&ifp->if_snd); 433 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 434 IF_UNLOCK(&ifp->if_snd); 435 sc->sc_wd_timer = 0; 436 } 437 438 /* 439 * TX completion tasklet. 440 */ 441 442 static void 443 ath_edma_tx_proc(void *arg, int npending) 444 { 445 struct ath_softc *sc = (struct ath_softc *) arg; 446 447 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n", 448 __func__, npending); 449 ath_edma_tx_processq(sc, 1); 450 } 451 452 /* 453 * Process the TX status queue. 454 */ 455 static void 456 ath_edma_tx_processq(struct ath_softc *sc, int dosched) 457 { 458 struct ath_hal *ah = sc->sc_ah; 459 HAL_STATUS status; 460 struct ath_tx_status ts; 461 struct ath_txq *txq; 462 struct ath_buf *bf; 463 struct ieee80211_node *ni; 464 int nacked = 0; 465 int idx; 466 467 #ifdef ATH_DEBUG 468 /* XXX */ 469 uint32_t txstatus[32]; 470 #endif 471 472 for (idx = 0; ; idx++) { 473 bzero(&ts, sizeof(ts)); 474 475 ATH_TXSTATUS_LOCK(sc); 476 #ifdef ATH_DEBUG 477 ath_hal_gettxrawtxdesc(ah, txstatus); 478 #endif 479 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts); 480 ATH_TXSTATUS_UNLOCK(sc); 481 482 #ifdef ATH_DEBUG 483 if (sc->sc_debug & ATH_DEBUG_TX_PROC) 484 ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id, 485 idx, (status == HAL_OK)); 486 #endif 487 488 if (status == HAL_EINPROGRESS) 489 break; 490 491 /* 492 * If there is an error with this descriptor, continue 493 * processing. 494 * 495 * XXX TBD: log some statistics? 496 */ 497 if (status == HAL_EIO) { 498 device_printf(sc->sc_dev, "%s: invalid TX status?\n", 499 __func__); 500 continue; 501 } 502 503 #ifdef ATH_DEBUG_ALQ 504 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS)) 505 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS, 506 sc->sc_tx_statuslen, 507 (char *) txstatus); 508 #endif /* ATH_DEBUG_ALQ */ 509 510 /* 511 * At this point we have a valid status descriptor. 512 * The QID and descriptor ID (which currently isn't set) 513 * is part of the status. 514 * 515 * We then assume that the descriptor in question is the 516 * -head- of the given QID. Eventually we should verify 517 * this by using the descriptor ID. 518 */ 519 520 /* 521 * The beacon queue is not currently a "real" queue. 522 * Frames aren't pushed onto it and the lock isn't setup. 523 * So skip it for now; the beacon handling code will 524 * free and alloc more beacon buffers as appropriate. 525 */ 526 if (ts.ts_queue_id == sc->sc_bhalq) 527 continue; 528 529 txq = &sc->sc_txq[ts.ts_queue_id]; 530 531 ATH_TXQ_LOCK(txq); 532 bf = TAILQ_FIRST(&txq->axq_q); 533 534 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: qcuid=%d, bf=%p\n", 535 __func__, 536 ts.ts_queue_id, bf); 537 538 /* XXX TODO: actually output debugging info about this */ 539 540 #if 0 541 /* XXX assert the buffer/descriptor matches the status descid */ 542 if (ts.ts_desc_id != bf->bf_descid) { 543 device_printf(sc->sc_dev, 544 "%s: mismatched descid (qid=%d, tsdescid=%d, " 545 "bfdescid=%d\n", 546 __func__, 547 ts.ts_queue_id, 548 ts.ts_desc_id, 549 bf->bf_descid); 550 } 551 #endif 552 553 /* This removes the buffer and decrements the queue depth */ 554 ATH_TXQ_REMOVE(txq, bf, bf_list); 555 if (bf->bf_state.bfs_aggr) 556 txq->axq_aggr_depth--; 557 txq->axq_fifo_depth --; 558 /* XXX assert FIFO depth >= 0 */ 559 ATH_TXQ_UNLOCK(txq); 560 561 /* 562 * First we need to make sure ts_rate is valid. 563 * 564 * Pre-EDMA chips pass the whole TX descriptor to 565 * the proctxdesc function which will then fill out 566 * ts_rate based on the ts_finaltsi (final TX index) 567 * in the TX descriptor. However the TX completion 568 * FIFO doesn't have this information. So here we 569 * do a separate HAL call to populate that information. 570 * 571 * The same problem exists with ts_longretry. 572 * The FreeBSD HAL corrects ts_longretry in the HAL layer; 573 * the AR9380 HAL currently doesn't. So until the HAL 574 * is imported and this can be added, we correct for it 575 * here. 576 */ 577 /* XXX TODO */ 578 /* XXX faked for now. Ew. */ 579 if (ts.ts_finaltsi < 4) { 580 ts.ts_rate = 581 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode; 582 switch (ts.ts_finaltsi) { 583 case 3: ts.ts_longretry += 584 bf->bf_state.bfs_rc[2].tries; 585 case 2: ts.ts_longretry += 586 bf->bf_state.bfs_rc[1].tries; 587 case 1: ts.ts_longretry += 588 bf->bf_state.bfs_rc[0].tries; 589 } 590 } else { 591 device_printf(sc->sc_dev, "%s: finaltsi=%d\n", 592 __func__, 593 ts.ts_finaltsi); 594 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode; 595 } 596 597 /* 598 * XXX This is terrible. 599 * 600 * Right now, some code uses the TX status that is 601 * passed in here, but the completion handlers in the 602 * software TX path also use bf_status.ds_txstat. 603 * Ew. That should all go away. 604 * 605 * XXX It's also possible the rate control completion 606 * routine is called twice. 607 */ 608 memcpy(&bf->bf_status, &ts, sizeof(ts)); 609 610 ni = bf->bf_node; 611 612 /* Update RSSI */ 613 /* XXX duplicate from ath_tx_processq */ 614 if (ni != NULL && ts.ts_status == 0 && 615 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) { 616 nacked++; 617 sc->sc_stats.ast_tx_rssi = ts.ts_rssi; 618 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi, 619 ts.ts_rssi); 620 } 621 622 /* Handle frame completion and rate control update */ 623 ath_tx_process_buf_completion(sc, txq, &ts, bf); 624 625 /* bf is invalid at this point */ 626 627 /* 628 * Now that there's space in the FIFO, let's push some 629 * more frames into it. 630 * 631 * Unfortunately for now, the txq has FIFO and non-FIFO 632 * frames in the same linked list, so there's no way 633 * to quickly/easily populate frames without walking 634 * the queue and skipping 'axq_fifo_depth' frames. 635 * 636 * So for now, let's only repopulate the FIFO once it 637 * is empty. It's sucky for performance but it's enough 638 * to begin validating that things are somewhat 639 * working. 640 */ 641 ATH_TXQ_LOCK(txq); 642 if (dosched && txq->axq_fifo_depth == 0) { 643 ath_edma_tx_fifo_fill(sc, txq); 644 } 645 ATH_TXQ_UNLOCK(txq); 646 } 647 648 sc->sc_wd_timer = 0; 649 650 if (idx > 0) { 651 IF_LOCK(&sc->sc_ifp->if_snd); 652 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 653 IF_UNLOCK(&sc->sc_ifp->if_snd); 654 } 655 656 /* Kick software scheduler */ 657 /* 658 * XXX It's inefficient to do this if the FIFO queue is full, 659 * but there's no easy way right now to only populate 660 * the txq task for _one_ TXQ. This should be fixed. 661 */ 662 if (dosched) 663 ath_tx_swq_kick(sc); 664 } 665 666 static void 667 ath_edma_attach_comp_func(struct ath_softc *sc) 668 { 669 670 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc); 671 } 672 673 void 674 ath_xmit_setup_edma(struct ath_softc *sc) 675 { 676 677 /* Fetch EDMA field and buffer sizes */ 678 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen); 679 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen); 680 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps); 681 682 device_printf(sc->sc_dev, "TX descriptor length: %d\n", 683 sc->sc_tx_desclen); 684 device_printf(sc->sc_dev, "TX status length: %d\n", 685 sc->sc_tx_statuslen); 686 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n", 687 sc->sc_tx_nmaps); 688 689 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup; 690 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown; 691 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func; 692 693 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart; 694 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff; 695 sc->sc_tx.xmit_drain = ath_edma_tx_drain; 696 } 697